Searched refs:ctl_val (Results 1 – 7 of 7) sorted by relevance
98 u32 ctl_val[smc_max]; /* control settings */ member280 u32 ctl = chip->ctl_val[smc_base]; in aspeed_smc_start_user()300 u32 ctl = chip->ctl_val[smc_read]; in aspeed_smc_stop_user()642 chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B; in aspeed_smc_chip_set_4b_spi_2400()643 chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B; in aspeed_smc_chip_set_4b_spi_2400()687 chip->ctl_val[smc_base] = base_reg; in aspeed_smc_chip_setup_init()696 chip->ctl_val[smc_read] = reg; in aspeed_smc_chip_setup_init()698 chip->ctl_val[smc_read] = chip->ctl_val[smc_base] | in aspeed_smc_chip_setup_init()702 chip->ctl_val[smc_read]); in aspeed_smc_chip_setup_init()721 chip->ctl_val[smc_write] = chip->ctl_val[smc_base] | in aspeed_smc_chip_setup_finish()[all …]
150 u32 ctl_val; in spm_set_low_power_mode() local154 ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); in spm_set_low_power_mode()155 ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT); in spm_set_low_power_mode()156 ctl_val |= start_index << SPM_CTL_INDEX_SHIFT; in spm_set_low_power_mode()157 ctl_val |= SPM_CTL_EN; in spm_set_low_power_mode()158 spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); in spm_set_low_power_mode()
95 int ctl_val, cur_val; in bcm_kona_show() local105 ctl_val = secure_register_read(wdt, SECWDOG_CTRL_REG); in bcm_kona_show()109 if (ctl_val < 0 || cur_val < 0) { in bcm_kona_show()114 ctl = ctl_val & SECWDOG_COUNT_MASK; in bcm_kona_show()115 res = (ctl_val & SECWDOG_RES_MASK) >> SECWDOG_CLKS_SHIFT; in bcm_kona_show()
225 u32 ctl_val; in switchtec_ntb_mw_clr_direct() local227 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_clr_direct()228 ctl_val &= ~NTB_CTRL_BAR_DIR_WIN_EN; in switchtec_ntb_mw_clr_direct()229 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_clr_direct()248 u32 ctl_val; in switchtec_ntb_mw_set_direct() local250 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_set_direct()251 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN; in switchtec_ntb_mw_set_direct()253 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); in switchtec_ntb_mw_set_direct()915 u32 ctl_val; in config_rsvd_lut_win() local923 ctl_val = ioread32(&ctl->bar_entry[peer_bar].ctl); in config_rsvd_lut_win()[all …]
143 u32 ctl_val = 0; in cxd2880_tnrdmd_dvbt_mon_carrier_offset() local183 ctl_val = in cxd2880_tnrdmd_dvbt_mon_carrier_offset()186 *offset = cxd2880_convert2s_complement(ctl_val, 29); in cxd2880_tnrdmd_dvbt_mon_carrier_offset()
85 u32 ctl_val = 0; in cxd2880_tnrdmd_dvbt2_mon_carrier_offset() local136 ctl_val = in cxd2880_tnrdmd_dvbt2_mon_carrier_offset()139 *offset = cxd2880_convert2s_complement(ctl_val, 28); in cxd2880_tnrdmd_dvbt2_mon_carrier_offset()
2770 u8 *ctl_val = ee->ee_ctl; in ath5k_get_max_ctl_power() local2801 if (ctl_val[i] == ctl_mode) { in ath5k_get_max_ctl_power()