| /drivers/media/pci/cx18/ |
| D | cx18-cards.c | 74 .ddr = {
121 .ddr = {
168 .ddr = {
221 .ddr = {
274 .ddr = {
334 .ddr = {
390 .ddr = {
439 .ddr = {
487 .ddr = {
540 .ddr = {
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| D | cx18-firmware.c | 324 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); in cx18_init_memory()
328 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); in cx18_init_memory()
329 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); in cx18_init_memory()
330 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); in cx18_init_memory()
335 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); in cx18_init_memory()
336 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); in cx18_init_memory()
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| D | cx18-cards.h | 130 struct cx18_ddr ddr; member
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| /drivers/memory/ |
| D | renesas-rpc-if.c | 378 rpc->ddr = 0; in rpcif_prepare()
385 if (op->cmd.ddr) in rpcif_prepare()
386 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); in rpcif_prepare()
402 if (op->addr.ddr) in rpcif_prepare()
403 rpc->ddr |= RPCIF_SMDRENR_ADDRE; in rpcif_prepare()
421 if (op->option.ddr) in rpcif_prepare()
422 rpc->ddr |= RPCIF_SMDRENR_OPDRE; in rpcif_prepare()
441 if (op->data.ddr) in rpcif_prepare()
442 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; in rpcif_prepare()
469 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); in rpcif_manual_xfer()
[all …]
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| /drivers/mtd/hyperbus/ |
| D | rpc-if.c | 29 .ddr = true,
33 .ddr = true,
38 .ddr = true,
42 .ddr = true,
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| /drivers/mmc/host/ |
| D | meson-gx-mmc.c | 159 bool ddr; member
341 bool ddr) in meson_mmc_clk_set() argument
348 if (host->ddr == ddr && host->req_rate == rate) in meson_mmc_clk_set()
365 if (ddr) { in meson_mmc_clk_set()
373 host->ddr = ddr; in meson_mmc_clk_set()
386 if (ddr) { in meson_mmc_clk_set()
550 bool ddr; in meson_mmc_prepare_ios_clock() local
555 ddr = true; in meson_mmc_prepare_ios_clock()
559 ddr = false; in meson_mmc_prepare_ios_clock()
563 return meson_mmc_clk_set(host, ios->clock, ddr); in meson_mmc_prepare_ios_clock()
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| D | mmci_stm32_sdmmc.c | 274 unsigned int clk = 0, ddr = 0; in mmci_sdmmc_set_clkreg() local
278 ddr = MCI_STM32_CLK_DDR; in mmci_sdmmc_set_clkreg()
286 if (desired >= host->mclk && !ddr) { in mmci_sdmmc_set_clkreg()
317 clk |= ddr; in mmci_sdmmc_set_clkreg()
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| /drivers/staging/media/atomisp/pci/runtime/isp_param/src/ |
| D | isp_param.c | 186 struct ia_css_isp_param_css_segments *ddr, in ia_css_isp_param_copy_isp_mem_if_to_ddr() argument
194 ia_css_ptr ddr_mem_ptr = ddr->params[pclass][mem].address; in ia_css_isp_param_copy_isp_mem_if_to_ddr()
197 if (size != ddr->params[pclass][mem].size) in ia_css_isp_param_copy_isp_mem_if_to_ddr()
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| /drivers/pinctrl/nuvoton/ |
| D | pinctrl-npcm7xx.c | 584 NPCM7XX_GRP(ddr), \
727 NPCM7XX_SFUNC(ddr);
845 NPCM7XX_MKFUNC(ddr),
1037 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1038 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1039 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1040 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1138 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1139 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1140 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
[all …]
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| /drivers/clk/meson/ |
| D | Makefile | 21 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
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| /drivers/staging/media/atomisp/pci/runtime/isp_param/interface/ |
| D | ia_css_isp_param.h | 94 struct ia_css_isp_param_css_segments *ddr,
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| /drivers/clk/rockchip/ |
| D | Makefile | 15 clk-rockchip-y += clk-ddr.o
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| /drivers/gpio/ |
| D | gpio-adnp.c | 189 u8 ddr, plr, ier, isr; in adnp_gpio_dbg_show() local
193 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); in adnp_gpio_dbg_show()
218 if (ddr & BIT(j)) in adnp_gpio_dbg_show()
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| /drivers/mfd/ |
| D | sm501.c | 951 unsigned long ddr; in sm501_gpio_input() local
958 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); in sm501_gpio_input()
959 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); in sm501_gpio_input()
978 unsigned long ddr; in sm501_gpio_output() local
992 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); in sm501_gpio_output()
993 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); in sm501_gpio_output()
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| /drivers/devfreq/event/ |
| D | Kconfig | 40 (DDR Monitor Module) driver to count ddr load.
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| /drivers/clk/davinci/ |
| D | psc-da850.c | 111 LPSC(6, 0, ddr, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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| /drivers/soc/ti/ |
| D | Kconfig | 58 c-states on AM335x. Also required for rtc and ddr in self-refresh low
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| /drivers/mmc/core/ |
| D | mmc.c | 945 int err, ddr; in mmc_select_powerclass() local
956 ddr = card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_52; in mmc_select_powerclass()
957 if (ddr) in mmc_select_powerclass()
967 mmc_hostname(host), 1 << bus_width, ddr); in mmc_select_powerclass()
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| /drivers/video/fbdev/matrox/ |
| D | matroxfb_misc.c | 669 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; in parse_pins5()
706 minfo->values.memory.ddr = 1; in default_pins5()
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| D | matroxfb_base.h | 489 unsigned int ddr:1, member
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| D | matroxfb_DAC1064.c | 769 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) { in g450_memory_init()
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| /drivers/clk/ |
| D | Kconfig | 55 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
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| /drivers/infiniband/hw/qib/ |
| D | qib_iba7220.c | 2673 u64 val, ddr; in qib_7220_set_loopback() local
2691 ddr = ppd->cpspec->ibcddrctrl & ~(IBA7220_IBC_HRTBT_MASK in qib_7220_set_loopback()
2693 ppd->cpspec->ibcddrctrl = ddr | val; in qib_7220_set_loopback()
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dsi.c | 1858 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) in ddr2ns() argument
1863 return ddr * 1000 * 1000 / (ddr_clk / 1000); in ddr2ns()
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | dsi.c | 1742 static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr) in ddr2ns() argument
1746 return ddr * 1000 * 1000 / (ddr_clk / 1000); in ddr2ns()
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