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Searched refs:divider (Results 1 – 25 of 119) sorted by relevance

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/drivers/clk/tegra/
Dclk-divider.c21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
71 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
[all …]
/drivers/clk/ti/
Ddivider.c40 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
46 if (divider->table) { in _setup_mask()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
53 max_val = divider->max; in _setup_mask()
55 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
56 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
60 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
65 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
68 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
70 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
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Dclk-dra7-atl.c57 u32 divider; /* Cached divider value */ member
93 cdesc->divider - 1); in atl_clk_enable()
128 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
134 unsigned divider; in atl_clk_round_rate() local
136 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate()
137 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate()
138 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
140 return *parent_rate / divider; in atl_clk_round_rate()
147 u32 divider; in atl_clk_set_rate() local
153 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
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/drivers/clk/qcom/
Dclk-regmap-divider.c21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
46 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
[all …]
/drivers/clk/mvebu/
Ddove-divider.c53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
90 if (divider >= max) in dove_calc_divider()
[all …]
/drivers/clk/
Dclk-divider.c28 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
30 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
31 return ioread32be(divider->reg); in clk_div_readl()
33 return readl(divider->reg); in clk_div_readl()
36 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
38 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
39 iowrite32be(val, divider->reg); in clk_div_writel()
41 writel(val, divider->reg); in clk_div_writel()
151 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local
154 val = clk_div_readl(divider) >> divider->shift; in clk_divider_recalc_rate()
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Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
401 return divider_ro_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
[all …]
Dclk-cdce925.c381 unsigned long divider; in cdce925_calc_divider() local
388 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in cdce925_calc_divider()
389 if (divider > 0x7F) in cdce925_calc_divider()
390 divider = 0x7F; in cdce925_calc_divider()
392 return (u16)divider; in cdce925_calc_divider()
442 u16 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate() local
444 if (l_parent_rate / divider != rate) { in cdce925_clk_round_rate()
446 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate()
450 if (divider) in cdce925_clk_round_rate()
451 return (long)(l_parent_rate / divider); in cdce925_clk_round_rate()
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/drivers/clk/rockchip/
Dclk-half-divider.c25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
111 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
120 if (divider->lock) in clk_half_divider_set_rate()
121 spin_lock_irqsave(divider->lock, flags); in clk_half_divider_set_rate()
[all …]
/drivers/clk/imx/
Dclk-fixup-div.c24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
64 value = divider - 1; in clk_fixup_div_set_rate()
110 fixup_div->divider.reg = reg; in imx_clk_hw_fixup_divider()
111 fixup_div->divider.shift = shift; in imx_clk_hw_fixup_divider()
[all …]
Dclk-composite-8m.c31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 orig = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
[all …]
Dclk-divider-gate.c15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
201 div_gate->divider.reg = reg; in imx_clk_hw_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_hw_divider_gate()
203 div_gate->divider.width = width; in imx_clk_hw_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_hw_divider_gate()
205 div_gate->divider.table = table; in imx_clk_hw_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_hw_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
213 hw = &div_gate->divider.hw; in imx_clk_hw_divider_gate()
/drivers/clk/mxs/
Dclk-div.c22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
90 div->divider.reg = reg; in mxs_clk_div()
91 div->divider.shift = shift; in mxs_clk_div()
92 div->divider.width = width; in mxs_clk_div()
93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
[all …]
/drivers/clk/zynqmp/
Ddivider.c81 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
83 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
84 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
99 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
103 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in zynqmp_clk_divider_recalc_rate()
124 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_round_rate() local
126 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
127 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
133 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
144 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_round_rate()
[all …]
/drivers/clk/baikal-t1/
Dccu-div.c79 unsigned long divider) in ccu_div_var_update_clkdiv() argument
86 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
212 unsigned long divider; in ccu_div_var_recalc_rate() local
216 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
218 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
225 unsigned long divider; in ccu_div_var_calc_divider() local
227 divider = parent_rate / rate; in ccu_div_var_calc_divider()
228 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
236 unsigned long divider; in ccu_div_var_round_rate() local
238 divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask); in ccu_div_var_round_rate()
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/drivers/clk/davinci/
Dpll.c244 struct clk_divider *divider; in davinci_pll_div_register() local
255 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
256 if (!divider) { in davinci_pll_div_register()
261 divider->reg = reg; in davinci_pll_div_register()
262 divider->shift = DIV_RATIO_SHIFT; in davinci_pll_div_register()
263 divider->width = DIV_RATIO_WIDTH; in davinci_pll_div_register()
266 divider->flags |= CLK_DIVIDER_READ_ONLY; in davinci_pll_div_register()
271 NULL, NULL, &divider->hw, divider_ops, in davinci_pll_div_register()
281 kfree(divider); in davinci_pll_div_register()
579 struct clk_divider *divider; in davinci_pll_obsclk_register() local
[all …]
/drivers/media/i2c/cx25840/
Dcx25840-ir.c145 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
148 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
158 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
160 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
170 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
174 (divider + 1) * rollovers); in clock_divider_to_freq()
215 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
222 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
226 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
235 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
[all …]
/drivers/clk/x86/
Dclk-cgu.c125 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_recalc_rate() local
128 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
129 divider->shift, divider->width); in lgm_clk_divider_recalc_rate()
131 return divider_recalc_rate(hw, parent_rate, val, divider->table, in lgm_clk_divider_recalc_rate()
132 divider->flags, divider->width); in lgm_clk_divider_recalc_rate()
139 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_round_rate() local
141 return divider_round_rate(hw, rate, prate, divider->table, in lgm_clk_divider_round_rate()
142 divider->width, divider->flags); in lgm_clk_divider_round_rate()
149 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_set_rate() local
152 value = divider_get_val(rate, prate, divider->table, in lgm_clk_divider_set_rate()
[all …]
/drivers/i2c/busses/
Di2c-bcm2835.c93 u32 divider = DIV_ROUND_UP(parent_rate, rate); in clk_bcm2835_i2c_calc_divider() local
100 if (divider & 1) in clk_bcm2835_i2c_calc_divider()
101 divider++; in clk_bcm2835_i2c_calc_divider()
102 if ((divider < BCM2835_I2C_CDIV_MIN) || in clk_bcm2835_i2c_calc_divider()
103 (divider > BCM2835_I2C_CDIV_MAX)) in clk_bcm2835_i2c_calc_divider()
106 return divider; in clk_bcm2835_i2c_calc_divider()
114 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); in clk_bcm2835_i2c_set_rate() local
116 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); in clk_bcm2835_i2c_set_rate()
126 fedl = max(divider / 16, 1u); in clk_bcm2835_i2c_set_rate()
[all …]
Di2c-mxs.c695 uint32_t divider; in mxs_i2c_derive_timing() local
700 divider = DIV_ROUND_UP(clk, speed); in mxs_i2c_derive_timing()
702 if (divider < 25) { in mxs_i2c_derive_timing()
707 divider = 25; in mxs_i2c_derive_timing()
711 clk / divider / 1000, clk / divider % 1000); in mxs_i2c_derive_timing()
712 } else if (divider > 1897) { in mxs_i2c_derive_timing()
717 divider = 1897; in mxs_i2c_derive_timing()
721 clk / divider / 1000, clk / divider % 1000); in mxs_i2c_derive_timing()
740 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6)); in mxs_i2c_derive_timing()
741 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6)); in mxs_i2c_derive_timing()
[all …]
/drivers/media/pci/cx23885/
Dcx23888-ir.c184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
193 (divider + 1) * rollovers); in clock_divider_to_freq()
234 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
241 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
245 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
254 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider) in pulse_width_count_to_us() argument
270 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ in pulse_width_count_to_us()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_cdclk.c580 u32 divider; in vlv_set_cdclk() local
582 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
588 val |= divider; in vlv_set_cdclk()
592 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), in vlv_set_cdclk()
1186 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1187 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1188 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1189 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1190 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1195 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
[all …]
/drivers/video/fbdev/aty/
Dmach64_gx.c506 short divider = 0, tempA; in aty_var_to_pll_1703() local
523 divider = 0; in aty_var_to_pll_1703()
526 divider += 0x20; in aty_var_to_pll_1703()
544 divider &= ~0x1f; in aty_var_to_pll_1703()
545 divider |= tempA; in aty_var_to_pll_1703()
546 divider = in aty_var_to_pll_1703()
547 (divider & 0x00ff) + in aty_var_to_pll_1703()
555 program_bits = divider; in aty_var_to_pll_1703()
560 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
745 short divider = 0, tempA; in aty_var_to_pll_408() local
[all …]
Dmach64_ct.c123 u32 multiplier, divider, ras_multiplier, ras_divider, tmp; in aty_dsp_gt() local
128 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
134 divider = divider * (bpp >> 2); in aty_dsp_gt()
146 divider = divider * pll->xres & ~7; in aty_dsp_gt()
154 while (((multiplier | divider) & 1) == 0) { in aty_dsp_gt()
156 divider = divider >> 1; in aty_dsp_gt()
160 tmp = ((multiplier * pll->fifo_size) << vshift) / divider; in aty_dsp_gt()
173 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - in aty_dsp_gt()
180 dsp_on = ((multiplier << vshift) + divider) / divider; in aty_dsp_gt()
192 dsp_on = dsp_off - (multiplier << vshift) / divider; in aty_dsp_gt()
[all …]
/drivers/staging/comedi/drivers/
Ddt3000.c345 unsigned int divider, base, prescale; in dt3k_ns_to_timer() local
355 divider = DIV_ROUND_CLOSEST(*nanosec, base); in dt3k_ns_to_timer()
358 divider = (*nanosec) / base; in dt3k_ns_to_timer()
361 divider = DIV_ROUND_UP(*nanosec, base); in dt3k_ns_to_timer()
364 if (divider < 65536) { in dt3k_ns_to_timer()
365 *nanosec = divider * base; in dt3k_ns_to_timer()
366 return (prescale << 16) | (divider); in dt3k_ns_to_timer()
372 divider = 65535; in dt3k_ns_to_timer()
373 *nanosec = divider * base; in dt3k_ns_to_timer()
374 return (prescale << 16) | (divider); in dt3k_ns_to_timer()
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