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Searched refs:dwc (Results 1 – 25 of 26) sorted by relevance

12

/drivers/usb/dwc3/
Dcore.c47 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode() argument
50 struct device *dev = dwc->dev; in dwc3_get_dr_mode()
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()
54 dwc->dr_mode = USB_DR_MODE_OTG; in dwc3_get_dr_mode()
56 mode = dwc->dr_mode; in dwc3_get_dr_mode()
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); in dwc3_get_dr_mode()
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) && in dwc3_get_dr_mode()
94 if (mode != dwc->dr_mode) { in dwc3_get_dr_mode()
99 dwc->dr_mode = mode; in dwc3_get_dr_mode()
105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) in dwc3_set_prtcap() argument
[all …]
Ddrd.c19 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) in dwc3_otg_disable_events() argument
21 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_disable_events()
24 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_disable_events()
27 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) in dwc3_otg_enable_events() argument
29 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_enable_events()
32 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_enable_events()
35 static void dwc3_otg_clear_events(struct dwc3 *dwc) in dwc3_otg_clear_events() argument
37 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT); in dwc3_otg_clear_events()
39 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_clear_events()
54 struct dwc3 *dwc = _dwc; in dwc3_otg_thread_irq() local
[all …]
Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
38 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb() local
40 dwc = dep->dwc; in dwc3_ep0_prepare_one_trb()
41 trb = &dwc->ep0_trb[dep->trb_enqueue]; in dwc3_ep0_prepare_one_trb()
66 struct dwc3 *dwc; in dwc3_ep0_start_trans() local
72 dwc = dep->dwc; in dwc3_ep0_start_trans()
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr); in dwc3_ep0_start_trans()
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr); in dwc3_ep0_start_trans()
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE; in dwc3_ep0_start_trans()
[all …]
Dgadget.c41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode() argument
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL); in dwc3_gadget_set_test_mode()
60 dwc3_gadget_dctl_write_safe(dwc, reg); in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state() argument
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS); in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state() argument
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS); in dwc3_gadget_set_link_state()
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL); in dwc3_gadget_set_link_state()
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg); in dwc3_gadget_set_link_state()
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg); in dwc3_gadget_set_link_state()
[all …]
Ddebugfs.c282 struct dwc3 *dwc = s->private; in dwc3_host_lsp() local
288 dbc_enabled = !!(dwc->hwparams.hwparams1 & DWC3_GHWPARAMS1_ENDBC); in dwc3_host_lsp()
290 sel = dwc->dbg_lsp_select; in dwc3_host_lsp()
298 dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); in dwc3_host_lsp()
299 val = dwc3_readl(dwc->regs, DWC3_GDBGLSP); in dwc3_host_lsp()
304 dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); in dwc3_host_lsp()
305 val = dwc3_readl(dwc->regs, DWC3_GDBGLSP); in dwc3_host_lsp()
312 struct dwc3 *dwc = s->private; in dwc3_gadget_lsp() local
318 dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); in dwc3_gadget_lsp()
319 reg = dwc3_readl(dwc->regs, DWC3_GDBGLSP); in dwc3_gadget_lsp()
[all …]
Dhost.c15 static int dwc3_host_get_irq(struct dwc3 *dwc) in dwc3_host_get_irq() argument
17 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); in dwc3_host_get_irq()
45 int dwc3_host_init(struct dwc3 *dwc) in dwc3_host_init() argument
51 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); in dwc3_host_init()
54 irq = dwc3_host_get_irq(dwc); in dwc3_host_init()
67 dwc->xhci_resources[1].start = irq; in dwc3_host_init()
68 dwc->xhci_resources[1].end = irq; in dwc3_host_init()
69 dwc->xhci_resources[1].flags = res->flags; in dwc3_host_init()
70 dwc->xhci_resources[1].name = res->name; in dwc3_host_init()
74 dev_err(dwc->dev, "couldn't allocate xHCI device\n"); in dwc3_host_init()
[all …]
Ddwc3-pci.c162 static int dwc3_pci_quirks(struct dwc3_pci *dwc) in dwc3_pci_quirks() argument
164 struct pci_dev *pdev = dwc->pci; in dwc3_pci_quirks()
170 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); in dwc3_pci_quirks()
171 dwc->has_dsm_for_pm = true; in dwc3_pci_quirks()
227 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); in dwc3_pci_resume_work() local
228 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work()
244 struct dwc3_pci *dwc; in dwc3_pci_probe() local
257 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_pci_probe()
258 if (!dwc) in dwc3_pci_probe()
261 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_pci_probe()
[all …]
Dulpi.c24 static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read) in dwc3_ulpi_busyloop() argument
36 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); in dwc3_ulpi_busyloop()
42 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_busyloop()
53 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_read() local
58 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); in dwc3_ulpi_read()
60 ret = dwc3_ulpi_busyloop(dwc, addr, true); in dwc3_ulpi_read()
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_read()
71 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_write() local
76 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); in dwc3_ulpi_write()
78 return dwc3_ulpi_busyloop(dwc, addr, false); in dwc3_ulpi_write()
[all …]
Ddwc3-haps.c39 struct dwc3_haps *dwc; in dwc3_haps_probe() local
52 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_haps_probe()
53 if (!dwc) in dwc3_haps_probe()
56 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
57 if (!dwc->dwc3) in dwc3_haps_probe()
71 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dwc->pci = pci; in dwc3_haps_probe()
78 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
80 ret = platform_device_add_properties(dwc->dwc3, initial_properties); in dwc3_haps_probe()
84 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
[all …]
Dcore.h668 struct dwc3 *dwc; member
718 struct dwc3 *dwc; member
1333 struct dwc3 dwc; member
1499 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1500 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1504 (dwc->ip == _ip##_IP)
1507 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1510 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1514 dwc->revision >= _ip##_REVISION_##_from && \
1516 dwc->revision <= _ip##_REVISION_##_to))
[all …]
Dgadget.h110 void dwc3_ep0_interrupt(struct dwc3 *dwc,
112 void dwc3_ep0_out_start(struct dwc3 *dwc);
113 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep);
114 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc);
120 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc);
146 static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) in dwc3_gadget_dctl_write_safe() argument
149 dwc3_writel(dwc->regs, DWC3_DCTL, value); in dwc3_gadget_dctl_write_safe()
Ddwc3-imx8mp.c82 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt() local
90 if ((dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc->xhci) in dwc3_imx8mp_interrupt()
91 pm_runtime_resume(&dwc->xhci->dev); in dwc3_imx8mp_interrupt()
92 else if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) in dwc3_imx8mp_interrupt()
93 pm_runtime_get(dwc->dev); in dwc3_imx8mp_interrupt()
245 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_resume() local
257 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) { in dwc3_imx8mp_resume()
258 pm_runtime_mark_last_busy(dwc->dev); in dwc3_imx8mp_resume()
259 pm_runtime_put_autosuspend(dwc->dev); in dwc3_imx8mp_resume()
Dtrace.h50 TP_PROTO(u32 event, struct dwc3 *dwc),
51 TP_ARGS(event, dwc),
59 __entry->ep0state = dwc->ep0state;
67 TP_PROTO(u32 event, struct dwc3 *dwc),
68 TP_ARGS(event, dwc)
Ddwc3-qcom.c309 struct dwc3 *dwc; in dwc3_qcom_is_host() local
314 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
317 if (!dwc) in dwc3_qcom_is_host()
320 return dwc->xhci; in dwc3_qcom_is_host()
432 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq() local
443 pm_runtime_resume(&dwc->xhci->dev); in qcom_dwc3_resume_irq()
/drivers/dma/dw/
Dcore.c51 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) in dwc_first_active() argument
53 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
59 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); in dwc_tx_submit() local
63 spin_lock_irqsave(&dwc->lock, flags); in dwc_tx_submit()
72 list_add_tail(&desc->desc_node, &dwc->queue); in dwc_tx_submit()
73 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_tx_submit()
80 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) in dwc_desc_get() argument
82 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get()
90 dwc->descs_allocated++; in dwc_desc_get()
92 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); in dwc_desc_get()
[all …]
Ddw.c14 static void dw_dma_initialize_chan(struct dw_dma_chan *dwc) in dw_dma_initialize_chan() argument
16 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dw_dma_initialize_chan()
17 u32 cfghi = is_slave_direction(dwc->direction) ? 0 : DWC_CFGH_FIFO_MODE; in dw_dma_initialize_chan()
18 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); in dw_dma_initialize_chan()
19 bool hs_polarity = dwc->dws.hs_polarity; in dw_dma_initialize_chan()
21 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); in dw_dma_initialize_chan()
22 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); in dw_dma_initialize_chan()
28 channel_writel(dwc, CFG_LO, cfglo); in dw_dma_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in dw_dma_initialize_chan()
32 static void dw_dma_suspend_chan(struct dw_dma_chan *dwc, bool drain) in dw_dma_suspend_chan() argument
[all …]
Didma32.c12 static void idma32_initialize_chan(struct dw_dma_chan *dwc) in idma32_initialize_chan() argument
21 cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf); in idma32_initialize_chan()
22 cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf); in idma32_initialize_chan()
25 cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3); in idma32_initialize_chan()
26 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3); in idma32_initialize_chan()
28 channel_writel(dwc, CFG_LO, cfglo); in idma32_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in idma32_initialize_chan()
32 static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain) in idma32_suspend_chan() argument
34 u32 cfglo = channel_readl(dwc, CFG_LO); in idma32_suspend_chan()
39 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); in idma32_suspend_chan()
[all …]
Dregs.h298 __dwc_regs(struct dw_dma_chan *dwc) in __dwc_regs() argument
300 return dwc->ch_regs; in __dwc_regs()
303 #define channel_readl(dwc, name) \ argument
304 readl(&(__dwc_regs(dwc)->name))
305 #define channel_writel(dwc, name, val) \ argument
306 writel((val), &(__dwc_regs(dwc)->name))
326 void (*initialize_chan)(struct dw_dma_chan *dwc);
327 void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
328 void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
329 u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
[all …]
/drivers/net/ethernet/synopsys/
DMakefile6 obj-$(CONFIG_DWC_XLGMAC) += dwc-xlgmac.o
7 dwc-xlgmac-objs := dwc-xlgmac-net.o dwc-xlgmac-desc.o \
8 dwc-xlgmac-hw.o dwc-xlgmac-common.o \
9 dwc-xlgmac-ethtool.o
11 dwc-xlgmac-$(CONFIG_DWC_XLGMAC_PCI) += dwc-xlgmac-pci.o
DKconfig26 Ethernet (dwc-xlgmac).
34 This selects the pci bus support for the dwc-xlgmac driver.
/drivers/scsi/ufs/
DMakefile13 obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o
14 obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o
/drivers/net/ethernet/stmicro/stmmac/
DMakefile28 obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
DKconfig45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
/drivers/pci/controller/
DMakefile36 obj-y += dwc/
/drivers/mmc/host/
DMakefile16 sdhci-pci-dwc-mshc.o sdhci-pci-gli.o

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