1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2013,2018 Intel Corporation
3
4 #include <linux/bitops.h>
5 #include <linux/dmaengine.h>
6 #include <linux/errno.h>
7 #include <linux/slab.h>
8 #include <linux/types.h>
9
10 #include "internal.h"
11
idma32_initialize_chan(struct dw_dma_chan * dwc)12 static void idma32_initialize_chan(struct dw_dma_chan *dwc)
13 {
14 u32 cfghi = 0;
15 u32 cfglo = 0;
16
17 /* Set default burst alignment */
18 cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
19
20 /* Low 4 bits of the request lines */
21 cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
22 cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
23
24 /* Request line extension (2 bits) */
25 cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
26 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
27
28 channel_writel(dwc, CFG_LO, cfglo);
29 channel_writel(dwc, CFG_HI, cfghi);
30 }
31
idma32_suspend_chan(struct dw_dma_chan * dwc,bool drain)32 static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain)
33 {
34 u32 cfglo = channel_readl(dwc, CFG_LO);
35
36 if (drain)
37 cfglo |= IDMA32C_CFGL_CH_DRAIN;
38
39 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
40 }
41
idma32_resume_chan(struct dw_dma_chan * dwc,bool drain)42 static void idma32_resume_chan(struct dw_dma_chan *dwc, bool drain)
43 {
44 u32 cfglo = channel_readl(dwc, CFG_LO);
45
46 if (drain)
47 cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
48
49 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
50 }
51
idma32_bytes2block(struct dw_dma_chan * dwc,size_t bytes,unsigned int width,size_t * len)52 static u32 idma32_bytes2block(struct dw_dma_chan *dwc,
53 size_t bytes, unsigned int width, size_t *len)
54 {
55 u32 block;
56
57 if (bytes > dwc->block_size) {
58 block = dwc->block_size;
59 *len = dwc->block_size;
60 } else {
61 block = bytes;
62 *len = bytes;
63 }
64
65 return block;
66 }
67
idma32_block2bytes(struct dw_dma_chan * dwc,u32 block,u32 width)68 static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
69 {
70 return IDMA32C_CTLH_BLOCK_TS(block);
71 }
72
idma32_prepare_ctllo(struct dw_dma_chan * dwc)73 static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
74 {
75 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
76 u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
77 u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
78
79 return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
80 DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
81 }
82
idma32_encode_maxburst(struct dw_dma_chan * dwc,u32 * maxburst)83 static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
84 {
85 *maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
86 }
87
idma32_set_device_name(struct dw_dma * dw,int id)88 static void idma32_set_device_name(struct dw_dma *dw, int id)
89 {
90 snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);
91 }
92
93 /*
94 * Program FIFO size of channels.
95 *
96 * By default full FIFO (512 bytes) is assigned to channel 0. Here we
97 * slice FIFO on equal parts between channels.
98 */
idma32_fifo_partition(struct dw_dma * dw)99 static void idma32_fifo_partition(struct dw_dma *dw)
100 {
101 u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
102 IDMA32C_FP_UPDATE;
103 u64 fifo_partition = 0;
104
105 /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
106 fifo_partition |= value << 0;
107
108 /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
109 fifo_partition |= value << 32;
110
111 /* Program FIFO Partition registers - 64 bytes per channel */
112 idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
113 idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
114 }
115
idma32_disable(struct dw_dma * dw)116 static void idma32_disable(struct dw_dma *dw)
117 {
118 do_dw_dma_off(dw);
119 idma32_fifo_partition(dw);
120 }
121
idma32_enable(struct dw_dma * dw)122 static void idma32_enable(struct dw_dma *dw)
123 {
124 idma32_fifo_partition(dw);
125 do_dw_dma_on(dw);
126 }
127
idma32_dma_probe(struct dw_dma_chip * chip)128 int idma32_dma_probe(struct dw_dma_chip *chip)
129 {
130 struct dw_dma *dw;
131
132 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
133 if (!dw)
134 return -ENOMEM;
135
136 /* Channel operations */
137 dw->initialize_chan = idma32_initialize_chan;
138 dw->suspend_chan = idma32_suspend_chan;
139 dw->resume_chan = idma32_resume_chan;
140 dw->prepare_ctllo = idma32_prepare_ctllo;
141 dw->encode_maxburst = idma32_encode_maxburst;
142 dw->bytes2block = idma32_bytes2block;
143 dw->block2bytes = idma32_block2bytes;
144
145 /* Device operations */
146 dw->set_device_name = idma32_set_device_name;
147 dw->disable = idma32_disable;
148 dw->enable = idma32_enable;
149
150 chip->dw = dw;
151 return do_dma_probe(chip);
152 }
153 EXPORT_SYMBOL_GPL(idma32_dma_probe);
154
idma32_dma_remove(struct dw_dma_chip * chip)155 int idma32_dma_remove(struct dw_dma_chip *chip)
156 {
157 return do_dma_remove(chip);
158 }
159 EXPORT_SYMBOL_GPL(idma32_dma_remove);
160