| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | ctxgp100.c | 56 int gpc, ppc, b, n = 0; in gp100_grctx_generate_attrib() local
58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp100_grctx_generate_attrib()
59 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp100_grctx_generate_attrib()
72 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp100_grctx_generate_attrib()
73 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp100_grctx_generate_attrib()
74 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
77 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp100_grctx_generate_attrib()
78 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp100_grctx_generate_attrib()
86 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
104 const u8 gpc = gr->sm[sm].gpc; in gp100_grctx_generate_smid_config() local
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| D | gv100.c | 28 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_gr_trap_sm() argument
32 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); in gv100_gr_trap_sm()
33 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); in gv100_gr_trap_sm()
42 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); in gv100_gr_trap_sm()
44 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); in gv100_gr_trap_sm()
45 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); in gv100_gr_trap_sm()
49 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_trap_mp() argument
51 gv100_gr_trap_sm(gr, gpc, tpc, 0); in gv100_gr_trap_mp()
52 gv100_gr_trap_sm(gr, gpc, tpc, 1); in gv100_gr_trap_mp()
63 gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_init_shader_exceptions() argument
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| D | ctxgp102.c | 52 int gpc, ppc, b, n = 0; in gp102_grctx_generate_attrib() local
54 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp102_grctx_generate_attrib()
55 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp102_grctx_generate_attrib()
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_grctx_generate_attrib()
69 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp102_grctx_generate_attrib()
70 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
74 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp102_grctx_generate_attrib()
75 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); in gp102_grctx_generate_attrib()
76 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp102_grctx_generate_attrib()
85 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
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| D | ctxgm200.c | 55 const u8 gpc = gr->sm[sm].gpc; in gm200_grctx_generate_smid_config() local
57 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gm200_grctx_generate_smid_config()
58 gpcs[gpc] |= sm << (tpc * 8); in gm200_grctx_generate_smid_config()
87 int gpc, ppc, i; in gm200_grctx_generate_dist_skip_table() local
89 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm200_grctx_generate_dist_skip_table()
90 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gm200_grctx_generate_dist_skip_table()
91 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
92 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
95 ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
96 ((u8 *)data)[gpc] |= ppc_tpcm; in gm200_grctx_generate_dist_skip_table()
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| D | ctxgv100.c | 73 int gpc, ppc, b, n = 0; in gv100_grctx_generate_attrib() local
75 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gv100_grctx_generate_attrib()
76 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gv100_grctx_generate_attrib()
88 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_grctx_generate_attrib()
89 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gv100_grctx_generate_attrib()
90 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
94 const u32 o = PPC_UNIT(gpc, ppc, 0); in gv100_grctx_generate_attrib()
95 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gv100_grctx_generate_attrib()
103 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
157 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_grctx_generate_sm_id() argument
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| D | ctxgf100.c | 1072 int gpc, tpc; in gf100_grctx_generate_attrib() local
1079 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_attrib()
1080 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_grctx_generate_attrib()
1081 const u32 o = TPC_UNIT(gpc, tpc, 0x0520); in gf100_grctx_generate_attrib()
1106 data |= gr->sm[sm++].gpc << (j * 8); in gf100_grctx_generate_r4060a8()
1275 int i, gpc; in gf100_grctx_generate_alpha_beta_tables() local
1287 for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1288 if (abits[gpc] < gr->tpc_nr[gpc]) { in gf100_grctx_generate_alpha_beta_tables()
1289 abits[gpc]++; in gf100_grctx_generate_alpha_beta_tables()
1295 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
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| D | gf100.c | 1174 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) in gf100_gr_trap_gpc_rop() argument
1181 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; in gf100_gr_trap_gpc_rop()
1182 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
1183 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
1184 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
1190 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, in gf100_gr_trap_gpc_rop()
1192 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_trap_gpc_rop()
1235 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gf100_gr_trap_mp() argument
1239 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
1240 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); in gf100_gr_trap_mp()
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| D | ctxgm107.c | 921 int gpc, ppc, n = 0; in gm107_grctx_generate_attrib() local
929 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm107_grctx_generate_attrib()
930 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gm107_grctx_generate_attrib()
931 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
932 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
934 const u32 o = PPC_UNIT(gpc, ppc, 0); in gm107_grctx_generate_attrib()
935 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gm107_grctx_generate_attrib()
939 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
942 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
955 gm107_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in gm107_grctx_generate_sm_id() argument
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| D | ctxgf117.c | 257 int gpc, ppc; in gf117_grctx_generate_attrib() local
264 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_grctx_generate_attrib()
265 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gf117_grctx_generate_attrib()
266 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
267 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
269 const u32 o = PPC_UNIT(gpc, ppc, 0); in gf117_grctx_generate_attrib()
270 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gf117_grctx_generate_attrib()
274 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
276 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
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| D | gf117.c | 129 u8 bank[GPC_MAX] = {}, gpc, i, j; in gf117_gr_init_zcull() local
140 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_gr_init_zcull()
141 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf117_gr_init_zcull()
142 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in gf117_gr_init_zcull()
143 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf117_gr_init_zcull()
145 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf117_gr_init_zcull()
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| D | tu102.c | 43 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + in tu102_gr_init_fs()
57 u8 bank[GPC_MAX] = {}, gpc, i, j; in tu102_gr_init_zcull() local
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in tu102_gr_init_zcull()
69 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
70 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in tu102_gr_init_zcull()
71 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
73 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
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| D | ctxgk104.c | 935 int i, j, gpc, ppc; in gk104_grctx_generate_alpha_beta_tables() local
943 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_grctx_generate_alpha_beta_tables()
945 u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
956 pmask = gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
959 amask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
961 pmask ^= gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
962 bmask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
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| D | gk104.c | 418 int gpc, ppc; in gk104_gr_init_ppc_exceptions() local
420 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_gr_init_ppc_exceptions()
421 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gk104_gr_init_ppc_exceptions()
422 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gk104_gr_init_ppc_exceptions()
424 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); in gk104_gr_init_ppc_exceptions()
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| D | ctxgf108.c | 749 int gpc, tpc; in gf108_grctx_generate_attrib() local
756 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf108_grctx_generate_attrib()
757 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf108_grctx_generate_attrib()
761 const u32 o = TPC_UNIT(gpc, tpc, 0x500); in gf108_grctx_generate_attrib()
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| D | gp102.c | 89 u32 mask = 0, data, gpc; in gp102_gr_init_swdx_pes_mask() local
91 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_gr_init_swdx_pes_mask()
92 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; in gp102_gr_init_swdx_pes_mask()
93 mask |= data << (gpc * 4); in gp102_gr_init_swdx_pes_mask()
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| D | ctxtu102.c | 34 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in tu102_grctx_generate_sm_id() argument
37 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in tu102_grctx_generate_sm_id()
38 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); in tu102_grctx_generate_sm_id()
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| D | gm107.c | 294 gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_shader_exceptions() argument
297 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gm107_gr_init_shader_exceptions()
298 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); in gm107_gr_init_shader_exceptions()
302 gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_504430() argument
305 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); in gm107_gr_init_504430()
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| D | gp100.c | 72 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gp100_gr_init_shader_exceptions() argument
75 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gp100_gr_init_shader_exceptions()
76 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105); in gp100_gr_init_shader_exceptions()
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| D | gf100.h | 128 u8 gpc; member
174 void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc);
175 void (*init_504430)(struct gf100_gr *, int gpc, int tpc);
176 void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc);
179 void (*trap_mp)(struct gf100_gr *, int gpc, int tpc);
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_svm.c | 59 u8 gpc; member
395 u64 inst, u8 hub, u8 gpc, u8 client) in nouveau_svm_fault_cancel() argument
397 SVM_DBG(svm, "cancel %016llx %d %02x %02x", inst, hub, gpc, client); in nouveau_svm_fault_cancel()
402 .gpc = gpc, in nouveau_svm_fault_cancel()
414 fault->gpc, in nouveau_svm_fault_cancel_fault()
447 const u8 gpc = (info & 0x1f000000) >> 24; in nouveau_svm_fault_cache() local
461 nouveau_svm_fault_cancel(svm, inst, hub, gpc, client); in nouveau_svm_fault_cache()
472 fault->gpc = gpc; in nouveau_svm_fault_cache()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/ |
| D | gpcgk208.fuc5 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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| D | gpcgk104.fuc3 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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| D | gpcgf100.fuc3 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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| D | gpcgk110.fuc3 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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| D | gpcgf117.fuc3 | 33 #include "gpc.fuc"
40 #include "gpc.fuc"
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