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Searched refs:hdmi_read_reg (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_cec.c70 u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; in hdmi_cec_received_msg()
83 msg.msg[0] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
85 msg.msg[1] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
91 hdmi_read_reg(core->base, reg); in hdmi_cec_received_msg()
99 while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1) in hdmi_cec_received_msg()
105 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; in hdmi_cec_received_msg()
111 u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0); in hdmi4_cec_irq()
112 u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1); in hdmi4_cec_irq()
122 u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3); in hdmi4_cec_irq()
142 temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3); in hdmi_cec_clear_tx_fifo()
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Dhdmi_wp.c22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
46 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
53 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
122 v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); in hdmi_wp_video_stop()
153 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); in hdmi_wp_video_config_interface()
232 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); in hdmi_wp_audio_config_format()
253 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); in hdmi_wp_audio_config_dma()
258 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); in hdmi_wp_audio_config_dma()
Dhdmi4_core.c185 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); in hdmi_core_video_config()
196 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); in hdmi_core_video_config()
209 r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); in hdmi_core_video_config()
313 hdmi_read_reg(core->base, r)) in hdmi4_core_dump()
315 hdmi_read_reg(hdmi_av_base(core), r)) in hdmi4_core_dump()
318 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) in hdmi4_core_dump()
508 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); in hdmi_core_audio_config()
546 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); in hdmi_core_audio_config()
559 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); in hdmi_core_audio_config()
Dhdmi_phy.c22 hdmi_read_reg(phy->base, r)) in hdmi_phy_dump()
132 hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); in hdmi_phy_configure()
Dhdmi.h272 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) in hdmi_read_reg() function
278 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
281 FLD_GET(hdmi_read_reg(base, idx), start, end)
Dhdmi_pll.c26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
Dhdmi5_core.c178 hdmi_read_reg(core->base, r)) in hdmi5_core_dump()
284 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); in hdmi_core_video_config()
Dhdmi4.c92 u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4); in hdmi_irq_handler()
Dhdmi5.c90 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler()
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_wp.c23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
123 v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); in hdmi_wp_video_stop()
154 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); in hdmi_wp_video_config_interface()
210 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); in hdmi_wp_audio_config_format()
233 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); in hdmi_wp_audio_config_dma()
238 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); in hdmi_wp_audio_config_dma()
Dhdmi4_core.c227 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); in hdmi_core_video_config()
238 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); in hdmi_core_video_config()
251 r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); in hdmi_core_video_config()
358 hdmi_read_reg(core->base, r)) in hdmi4_core_dump()
360 hdmi_read_reg(hdmi_av_base(core), r)) in hdmi4_core_dump()
363 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) in hdmi4_core_dump()
552 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); in hdmi_core_audio_config()
590 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); in hdmi_core_audio_config()
603 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); in hdmi_core_audio_config()
Dhdmi.h253 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) in hdmi_read_reg() function
259 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
262 FLD_GET(hdmi_read_reg(base, idx), start, end)
Dhdmi_phy.c31 hdmi_read_reg(phy->base, r)) in hdmi_phy_dump()
141 hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); in hdmi_phy_configure()
Dhdmi_pll.c26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
Dhdmi5_core.c223 hdmi_read_reg(core->base, r)) in hdmi5_core_dump()
319 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); in hdmi_core_video_config()
Dhdmi5.c89 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler()