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Searched refs:uint32_t (Results 1 – 25 of 1720) sorted by relevance

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/drivers/gpu/drm/amd/include/
Dv10_structs.h29 uint32_t reserved_0; // offset: 0 (0x0)
30 uint32_t reserved_1; // offset: 1 (0x1)
31 uint32_t reserved_2; // offset: 2 (0x2)
32 uint32_t reserved_3; // offset: 3 (0x3)
33 uint32_t reserved_4; // offset: 4 (0x4)
34 uint32_t reserved_5; // offset: 5 (0x5)
35 uint32_t reserved_6; // offset: 6 (0x6)
36 uint32_t reserved_7; // offset: 7 (0x7)
37 uint32_t reserved_8; // offset: 8 (0x8)
38 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
Dv9_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_rptr_hi;
33 uint32_t sdmax_rlcx_rb_wptr;
34 uint32_t sdmax_rlcx_rb_wptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
[all …]
Dvi_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_wptr;
33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
[all …]
Dcik_structs.h28 uint32_t header;
29 uint32_t compute_dispatch_initiator;
30 uint32_t compute_dim_x;
31 uint32_t compute_dim_y;
32 uint32_t compute_dim_z;
33 uint32_t compute_start_x;
34 uint32_t compute_start_y;
35 uint32_t compute_start_z;
36 uint32_t compute_num_thread_x;
37 uint32_t compute_num_thread_y;
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/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h180 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP()
186 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR()
192 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR()
207 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP()
213 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR()
219 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) in MDP5_HW_VERSION_MAJOR()
227 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF0()
233 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF1()
239 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF2()
245 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF3()
[all …]
/drivers/gpu/drm/amd/amdkfd/
Dkfd_pm4_headers_ai.h31 uint32_t reserved1 : 8; /* < reserved */
32 uint32_t opcode : 8; /* < IT opcode */
33 uint32_t count : 14;/* < number of DWORDs - 1 in the
36 uint32_t type : 2; /* < packet identifier.
40 uint32_t u32All;
58 uint32_t ordinal1;
63 uint32_t vmid_mask:16;
64 uint32_t unmap_latency:8;
65 uint32_t reserved1:5;
68 uint32_t ordinal2;
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Dkfd_pm4_headers_vi.h31 uint32_t reserved1 : 8; /* < reserved */
32 uint32_t opcode : 8; /* < IT opcode */
33 uint32_t count : 14;/* < Number of DWORDS - 1 in the
36 uint32_t type : 2; /* < packet identifier
40 uint32_t u32All;
58 uint32_t ordinal1;
63 uint32_t vmid_mask:16;
64 uint32_t unmap_latency:8;
65 uint32_t reserved1:5;
68 uint32_t ordinal2;
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Dkfd_pm4_headers.h32 uint32_t reserved1:8;
34 uint32_t opcode:8;
36 uint32_t count:14;
38 uint32_t type:2;
40 uint32_t u32all;
53 uint32_t ordinal1;
58 uint32_t pasid:16;
59 uint32_t reserved1:8;
60 uint32_t diq_enable:1;
61 uint32_t process_quantum:7;
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/drivers/scsi/arcmsr/
Darcmsr.h102 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
103 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
111 uint32_t HeaderLength;
113 uint32_t Timeout;
114 uint32_t ControlCode;
115 uint32_t ReturnCode;
116 uint32_t Length;
194 uint32_t data_len;
204 uint32_t signature; /*0, 00-03*/
205 uint32_t request_len; /*1, 04-07*/
[all …]
/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h67 uint32_t enum_id:16; /* 1 based enum */
73 uint32_t clk_mask_register_index;
74 uint32_t clk_en_register_index;
75 uint32_t clk_y_register_index;
76 uint32_t clk_a_register_index;
77 uint32_t data_mask_register_index;
78 uint32_t data_en_register_index;
79 uint32_t data_y_register_index;
80 uint32_t data_a_register_index;
82 uint32_t clk_mask_shift;
[all …]
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT()
183 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
[all …]
/drivers/scsi/lpfc/
Dlpfc_hw.h80 uint32_t Revision:8;
81 uint32_t InId:24;
83 uint32_t word;
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
92 uint32_t word;
115 uint32_t PortID;
134 uint32_t PortId; /* For RFT_ID requests */
137 uint32_t rsvd0:16;
138 uint32_t rsvd1:7;
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Dlpfc.h94 #define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
95 #define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
142 uint32_t buffer_tag; /* used for tagged queue ring */
155 uint32_t max_count;
156 uint32_t current_count;
164 uint32_t tag;
188 uint32_t status; /* vpd status value */
189 uint32_t length; /* number of bytes actually returned */
191 uint32_t rsvd1; /* Revision numbers */
192 uint32_t biuRev;
[all …]
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ucode.h29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
51 uint32_t ucode_start_addr;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
[all …]
Damdgpu_socbb.h27 uint32_t state;
28 uint32_t dscclk_mhz;
29 uint32_t dcfclk_mhz;
30 uint32_t socclk_mhz;
31 uint32_t dram_speed_mts;
32 uint32_t fabricclk_mhz;
33 uint32_t dispclk_mhz;
34 uint32_t phyclk_mhz;
35 uint32_t dppclk_mhz;
39 uint32_t sr_exit_time_us;
[all …]
/drivers/gpu/drm/meson/
Dmeson_drv.h63 uint32_t osd1_ctrl_stat;
64 uint32_t osd1_ctrl_stat2;
65 uint32_t osd1_blk0_cfg[5];
66 uint32_t osd1_blk1_cfg4;
67 uint32_t osd1_blk2_cfg4;
68 uint32_t osd1_addr;
69 uint32_t osd1_stride;
70 uint32_t osd1_height;
71 uint32_t osd1_width;
72 uint32_t osd_sc_ctrl0;
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/drivers/gpu/drm/msm/adreno/
Da6xx.xml.h1021 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO()
1027 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI()
1033 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1039 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1047 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
1053 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE()
1068 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH()
1070 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG()
1072 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT()
1074 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG()
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Dadreno_pm4.xml.h475 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF()
481 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC()
487 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK()
493 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT()
501 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE()
507 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) in CP_LOAD_STATE_1_EXT_SRC_ADDR()
515 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) in CP_LOAD_STATE4_0_DST_OFF()
521 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) in CP_LOAD_STATE4_0_STATE_SRC()
527 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) in CP_LOAD_STATE4_0_STATE_BLOCK()
533 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE4_0_NUM_UNIT()
[all …]
Da4xx.xml.h844 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC()
901 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
907 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
923 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH()
929 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT()
943 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) in A4XX_RB_MSAA_CONTROL_SAMPLES()
951 static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val) in A4XX_RB_RENDER_CONTROL2_COORD_MASK()
960 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) in A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES()
970 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT()
972 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL()
[all …]
Da3xx.xml.h915 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT()
917 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT_REG()
947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE()
985 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) in A3XX_GRAS_CL_VPORT_YOFFSET()
993 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) in A3XX_GRAS_CL_VPORT_YSCALE()
1001 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) in A3XX_GRAS_CL_VPORT_ZOFFSET()
[all …]
Da5xx.xml.h1033 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH()
1035 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH_REG()
1037 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT()
1039 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT_REG()
1042 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR()
1048 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN()
1054 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1060 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ()
1837 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
1843 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP()
[all …]
/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR()
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR()
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP()
180 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL()
186 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT()
192 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) in DSI_VID_CFG0_TRAFFIC_MODE()
209 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) in DSI_VID_CFG1_RGB_SWAP()
217 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) in DSI_ACTIVE_H_START()
223 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) in DSI_ACTIVE_H_END()
231 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) in DSI_ACTIVE_V_START()
[all …]
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu8_hwmgr.h45 uint32_t soft_min_clk;
46 uint32_t hard_min_clk;
47 uint32_t soft_max_clk;
48 uint32_t hard_max_clk;
52 uint32_t bootup_uma_clock;
53 uint32_t bootup_engine_clock;
54 uint32_t dentist_vco_freq;
55 uint32_t nb_dpm_enable;
56 uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
57 uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
[all …]
Dsmu7_hwmgr.h47 uint32_t offset;
48 uint32_t mask;
49 uint32_t shift;
50 uint32_t value;
55 uint32_t memory_clock;
56 uint32_t engine_clock;
68 uint32_t vclk;
69 uint32_t dclk;
73 uint32_t evclk;
74 uint32_t ecclk;
[all …]
/drivers/scsi/qla2xxx/
Dqla_nx2.h239 uint32_t test_mask;
240 uint32_t test_value;
245 uint32_t test_mask;
246 uint32_t xor_value;
247 uint32_t or_value;
256 uint32_t arg1;
257 uint32_t arg2;
262 uint32_t dr_addr;
263 uint32_t dr_value;
264 uint32_t ar_addr;
[all …]

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