| /drivers/media/platform/qcom/camss/ |
| D | camss-vfe-4-1.c | 905 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) in vfe_isr_read() argument
907 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); in vfe_isr_read()
910 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); in vfe_isr_read()
934 u32 value0, value1; in vfe_isr() local
937 vfe->ops->isr_read(vfe, &value0, &value1); in vfe_isr()
940 value0, value1); in vfe_isr()
942 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) in vfe_isr()
952 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) in vfe_isr()
955 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) in vfe_isr()
963 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { in vfe_isr()
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| D | camss-ispif.c | 163 u32 value0, value1, value2, value3, value4, value5; in ispif_isr_8x96() local
165 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); in ispif_isr_8x96()
172 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); in ispif_isr_8x96()
181 if ((value0 >> 27) & 0x1) in ispif_isr_8x96()
184 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW)) in ispif_isr_8x96()
187 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW)) in ispif_isr_8x96()
227 u32 value0, value1, value2; in ispif_isr_8x16() local
229 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); in ispif_isr_8x16()
233 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); in ispif_isr_8x16()
239 if ((value0 >> 27) & 0x1) in ispif_isr_8x16()
[all …]
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| D | camss-vfe-4-7.c | 1027 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) in vfe_isr_read() argument
1029 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); in vfe_isr_read()
1032 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); in vfe_isr_read()
1056 u32 value0, value1; in vfe_isr() local
1059 vfe->ops->isr_read(vfe, &value0, &value1); in vfe_isr()
1062 value0, value1); in vfe_isr()
1064 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) in vfe_isr()
1074 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) in vfe_isr()
1077 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) in vfe_isr()
1085 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { in vfe_isr()
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| D | camss-vfe.h | 131 void (*isr_read)(struct vfe_device *vfe, u32 *value0, u32 *value1);
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| /drivers/ata/ |
| D | pata_pdc2027x.c | 80 u8 value0, value1, value2; member
90 u8 value0, value1; member
98 u8 value0, value1, value2; member
309 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | in pdc2027x_set_piomode()
357 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | in pdc2027x_set_dmamode()
375 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | in pdc2027x_set_dmamode()
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| /drivers/media/i2c/ |
| D | ov7740.c | 433 unsigned int value0, value1; in ov7740_get_gain() local
439 ret = regmap_read(regmap, REG_GAIN, &value0); in ov7740_get_gain()
446 ov7740->gain->val = (value1 << 8) | (value0 & 0xff); in ov7740_get_gain()
454 unsigned int value0, value1; in ov7740_get_exp() local
460 ret = regmap_read(regmap, REG_AEC, &value0); in ov7740_get_exp()
467 ov7740->exposure->val = (value1 << 8) | (value0 & 0xff); in ov7740_get_exp()
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| /drivers/iio/adc/ |
| D | meson_saradc.c | 1029 int ret, nominal0, nominal1, value0, value1; in meson_sar_adc_calib() local
1039 MEAN_AVERAGING, EIGHT_SAMPLES, &value0); in meson_sar_adc_calib()
1051 if (value1 <= value0) { in meson_sar_adc_calib()
1057 value1 - value0); in meson_sar_adc_calib()
1058 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, in meson_sar_adc_calib()
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| /drivers/gpu/drm/msm/edp/ |
| D | edp_ctrl.c | 572 u32 value0; in edp_voltage_pre_emphasise_set() local
577 value0 = vm_pre_emphasis[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; in edp_voltage_pre_emphasise_set()
581 if (value0 != 0xFF && value1 != 0xFF) { in edp_voltage_pre_emphasise_set()
582 msm_edp_phy_vm_pe_cfg(ctrl->phy, value0, value1); in edp_voltage_pre_emphasise_set()
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| /drivers/pinctrl/intel/ |
| D | pinctrl-intel.c | 759 u32 value0, value2; in intel_config_set_debounce() local
769 value0 = readl(padcfg0); in intel_config_set_debounce()
773 value0 &= ~PADCFG0_PREGFRXSEL; in intel_config_set_debounce()
786 value0 |= PADCFG0_PREGFRXSEL; in intel_config_set_debounce()
791 writel(value0, padcfg0); in intel_config_set_debounce()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_link_encoder.c | 1210 uint32_t value0 = 0; in dcn10_link_encoder_update_mst_stream_allocation_table() local
1312 value0 = REG_READ(DP_MSE_SAT_UPDATE); in dcn10_link_encoder_update_mst_stream_allocation_table()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.c | 1506 uint32_t value0 = 0; in dce110_link_encoder_update_mst_stream_allocation_table() local
1607 value0 = REG_READ(DP_MSE_SAT_UPDATE); in dce110_link_encoder_update_mst_stream_allocation_table()
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