SSPP_VIG2 (reference) in projects: drivers

Searched refs:SSPP_VIG2 (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
D	mdp5_cfg.c	`28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7, 112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7, 196 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19, 433 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,`
D	mdp5_ctl.c	`292 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask() 315 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask() 443 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()`
D	mdp5.xml.h	`71 SSPP_VIG2 = 3, enumerator 541 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); in __offset_PIPE()`
D	mdp5_kms.c	`727 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator`
/drivers/gpu/drm/msm/disp/dpu1/
D	dpu_hw_top.c	`140 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; in dpu_hw_get_danger_status() 237 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; in dpu_hw_get_safe_status()`
D	dpu_hw_ctl.c	`147 case SSPP_VIG2: in dpu_hw_ctl_get_bitmask_sspp() 403 case SSPP_VIG2: in dpu_hw_ctl_setup_blendstage()`
D	dpu_hw_mdss.h	`111 SSPP_VIG2, enumerator`
D	dpu_hw_interrupts.c	`386 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2}, 387 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,`
D	dpu_hw_catalog.c	`346 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,`