1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_MDSS_H 6 #define _DPU_HW_MDSS_H 7 8 #include <linux/kernel.h> 9 #include <linux/err.h> 10 11 #include "msm_drv.h" 12 13 #define DPU_DBG_NAME "dpu" 14 15 #define DPU_NONE 0 16 17 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 18 #define DPU_CSC_MATRIX_COEFF_SIZE 9 19 #endif 20 21 #ifndef DPU_CSC_CLAMP_SIZE 22 #define DPU_CSC_CLAMP_SIZE 6 23 #endif 24 25 #ifndef DPU_CSC_BIAS_SIZE 26 #define DPU_CSC_BIAS_SIZE 3 27 #endif 28 29 #ifndef DPU_MAX_PLANES 30 #define DPU_MAX_PLANES 4 31 #endif 32 33 #define PIPES_PER_STAGE 2 34 #ifndef DPU_MAX_DE_CURVES 35 #define DPU_MAX_DE_CURVES 3 36 #endif 37 38 enum dpu_format_flags { 39 DPU_FORMAT_FLAG_YUV_BIT, 40 DPU_FORMAT_FLAG_DX_BIT, 41 DPU_FORMAT_FLAG_COMPRESSED_BIT, 42 DPU_FORMAT_FLAG_BIT_MAX, 43 }; 44 45 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 46 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 47 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 48 #define DPU_FORMAT_IS_YUV(X) \ 49 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) 50 #define DPU_FORMAT_IS_DX(X) \ 51 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) 52 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) 53 #define DPU_FORMAT_IS_TILE(X) \ 54 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 55 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 56 #define DPU_FORMAT_IS_UBWC(X) \ 57 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 58 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 59 60 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 61 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 62 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 63 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 64 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 65 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 66 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 67 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 68 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 69 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 70 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 71 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 72 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 73 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 74 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 75 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 76 77 #define DPU_VSYNC0_SOURCE_GPIO 0 78 #define DPU_VSYNC1_SOURCE_GPIO 1 79 #define DPU_VSYNC2_SOURCE_GPIO 2 80 #define DPU_VSYNC_SOURCE_INTF_0 3 81 #define DPU_VSYNC_SOURCE_INTF_1 4 82 #define DPU_VSYNC_SOURCE_INTF_2 5 83 #define DPU_VSYNC_SOURCE_INTF_3 6 84 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 85 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 86 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 87 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 88 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 89 90 enum dpu_hw_blk_type { 91 DPU_HW_BLK_TOP = 0, 92 DPU_HW_BLK_SSPP, 93 DPU_HW_BLK_LM, 94 DPU_HW_BLK_CTL, 95 DPU_HW_BLK_PINGPONG, 96 DPU_HW_BLK_INTF, 97 DPU_HW_BLK_WB, 98 DPU_HW_BLK_DSPP, 99 DPU_HW_BLK_MAX, 100 }; 101 102 enum dpu_mdp { 103 MDP_TOP = 0x1, 104 MDP_MAX, 105 }; 106 107 enum dpu_sspp { 108 SSPP_NONE, 109 SSPP_VIG0, 110 SSPP_VIG1, 111 SSPP_VIG2, 112 SSPP_VIG3, 113 SSPP_RGB0, 114 SSPP_RGB1, 115 SSPP_RGB2, 116 SSPP_RGB3, 117 SSPP_DMA0, 118 SSPP_DMA1, 119 SSPP_DMA2, 120 SSPP_DMA3, 121 SSPP_CURSOR0, 122 SSPP_CURSOR1, 123 SSPP_MAX 124 }; 125 126 enum dpu_sspp_type { 127 SSPP_TYPE_VIG, 128 SSPP_TYPE_RGB, 129 SSPP_TYPE_DMA, 130 SSPP_TYPE_CURSOR, 131 SSPP_TYPE_MAX 132 }; 133 134 enum dpu_lm { 135 LM_0 = 1, 136 LM_1, 137 LM_2, 138 LM_3, 139 LM_4, 140 LM_5, 141 LM_6, 142 LM_MAX 143 }; 144 145 enum dpu_stage { 146 DPU_STAGE_BASE = 0, 147 DPU_STAGE_0, 148 DPU_STAGE_1, 149 DPU_STAGE_2, 150 DPU_STAGE_3, 151 DPU_STAGE_4, 152 DPU_STAGE_5, 153 DPU_STAGE_6, 154 DPU_STAGE_7, 155 DPU_STAGE_8, 156 DPU_STAGE_9, 157 DPU_STAGE_10, 158 DPU_STAGE_MAX 159 }; 160 enum dpu_dspp { 161 DSPP_0 = 1, 162 DSPP_1, 163 DSPP_2, 164 DSPP_3, 165 DSPP_MAX 166 }; 167 168 enum dpu_ctl { 169 CTL_0 = 1, 170 CTL_1, 171 CTL_2, 172 CTL_3, 173 CTL_4, 174 CTL_5, 175 CTL_MAX 176 }; 177 178 enum dpu_pingpong { 179 PINGPONG_0 = 1, 180 PINGPONG_1, 181 PINGPONG_2, 182 PINGPONG_3, 183 PINGPONG_4, 184 PINGPONG_5, 185 PINGPONG_S0, 186 PINGPONG_MAX 187 }; 188 189 enum dpu_intf { 190 INTF_0 = 1, 191 INTF_1, 192 INTF_2, 193 INTF_3, 194 INTF_4, 195 INTF_5, 196 INTF_6, 197 INTF_MAX 198 }; 199 200 enum dpu_intf_type { 201 INTF_NONE = 0x0, 202 INTF_DSI = 0x1, 203 INTF_HDMI = 0x3, 204 INTF_LCDC = 0x5, 205 INTF_EDP = 0x9, 206 INTF_DP = 0xa, 207 INTF_TYPE_MAX, 208 209 /* virtual interfaces */ 210 INTF_WB = 0x100, 211 }; 212 213 enum dpu_intf_mode { 214 INTF_MODE_NONE = 0, 215 INTF_MODE_CMD, 216 INTF_MODE_VIDEO, 217 INTF_MODE_WB_BLOCK, 218 INTF_MODE_WB_LINE, 219 INTF_MODE_MAX 220 }; 221 222 enum dpu_wb { 223 WB_0 = 1, 224 WB_1, 225 WB_2, 226 WB_3, 227 WB_MAX 228 }; 229 230 enum dpu_cwb { 231 CWB_0 = 0x1, 232 CWB_1, 233 CWB_2, 234 CWB_3, 235 CWB_MAX 236 }; 237 238 enum dpu_wd_timer { 239 WD_TIMER_0 = 0x1, 240 WD_TIMER_1, 241 WD_TIMER_2, 242 WD_TIMER_3, 243 WD_TIMER_4, 244 WD_TIMER_5, 245 WD_TIMER_MAX 246 }; 247 248 enum dpu_vbif { 249 VBIF_0, 250 VBIF_1, 251 VBIF_MAX, 252 VBIF_RT = VBIF_0, 253 VBIF_NRT = VBIF_1 254 }; 255 256 /** 257 * DPU HW,Component order color map 258 */ 259 enum { 260 C0_G_Y = 0, 261 C1_B_Cb = 1, 262 C2_R_Cr = 2, 263 C3_ALPHA = 3 264 }; 265 266 /** 267 * enum dpu_plane_type - defines how the color component pixel packing 268 * @DPU_PLANE_INTERLEAVED : Color components in single plane 269 * @DPU_PLANE_PLANAR : Color component in separate planes 270 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane 271 */ 272 enum dpu_plane_type { 273 DPU_PLANE_INTERLEAVED, 274 DPU_PLANE_PLANAR, 275 DPU_PLANE_PSEUDO_PLANAR, 276 }; 277 278 /** 279 * enum dpu_chroma_samp_type - chroma sub-samplng type 280 * @DPU_CHROMA_RGB : No chroma subsampling 281 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled 282 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled 283 * @DPU_CHROMA_420 : 420 subsampling 284 */ 285 enum dpu_chroma_samp_type { 286 DPU_CHROMA_RGB, 287 DPU_CHROMA_H2V1, 288 DPU_CHROMA_H1V2, 289 DPU_CHROMA_420 290 }; 291 292 /** 293 * dpu_fetch_type - Defines How DPU HW fetches data 294 * @DPU_FETCH_LINEAR : fetch is line by line 295 * @DPU_FETCH_TILE : fetches data in Z order from a tile 296 * @DPU_FETCH_UBWC : fetch and decompress data 297 */ 298 enum dpu_fetch_type { 299 DPU_FETCH_LINEAR, 300 DPU_FETCH_TILE, 301 DPU_FETCH_UBWC 302 }; 303 304 /** 305 * Value of enum chosen to fit the number of bits 306 * expected by the HW programming. 307 */ 308 enum { 309 COLOR_ALPHA_1BIT = 0, 310 COLOR_ALPHA_4BIT = 1, 311 COLOR_4BIT = 0, 312 COLOR_5BIT = 1, /* No 5-bit Alpha */ 313 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ 314 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ 315 }; 316 317 /** 318 * enum dpu_3d_blend_mode 319 * Desribes how the 3d data is blended 320 * @BLEND_3D_NONE : 3d blending not enabled 321 * @BLEND_3D_FRAME_INT : Frame interleaving 322 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 323 * @BLEND_3D_V_ROW_INT : vertical row interleaving 324 * @BLEND_3D_COL_INT : column interleaving 325 * @BLEND_3D_MAX : 326 */ 327 enum dpu_3d_blend_mode { 328 BLEND_3D_NONE = 0, 329 BLEND_3D_FRAME_INT, 330 BLEND_3D_H_ROW_INT, 331 BLEND_3D_V_ROW_INT, 332 BLEND_3D_COL_INT, 333 BLEND_3D_MAX 334 }; 335 336 /** struct dpu_format - defines the format configuration which 337 * allows DPU HW to correctly fetch and decode the format 338 * @base: base msm_format struture containing fourcc code 339 * @fetch_planes: how the color components are packed in pixel format 340 * @element: element color ordering 341 * @bits: element bit widths 342 * @chroma_sample: chroma sub-samplng type 343 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB 344 * @unpack_tight: 0 for loose, 1 for tight 345 * @unpack_count: 0 = 1 component, 1 = 2 component 346 * @bpp: bytes per pixel 347 * @alpha_enable: whether the format has an alpha channel 348 * @num_planes: number of planes (including meta data planes) 349 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 350 * @flag: usage bit flags 351 * @tile_width: format tile width 352 * @tile_height: format tile height 353 */ 354 struct dpu_format { 355 struct msm_format base; 356 enum dpu_plane_type fetch_planes; 357 u8 element[DPU_MAX_PLANES]; 358 u8 bits[DPU_MAX_PLANES]; 359 enum dpu_chroma_samp_type chroma_sample; 360 u8 unpack_align_msb; 361 u8 unpack_tight; 362 u8 unpack_count; 363 u8 bpp; 364 u8 alpha_enable; 365 u8 num_planes; 366 enum dpu_fetch_type fetch_mode; 367 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); 368 u16 tile_width; 369 u16 tile_height; 370 }; 371 #define to_dpu_format(x) container_of(x, struct dpu_format, base) 372 373 /** 374 * struct dpu_hw_fmt_layout - format information of the source pixel data 375 * @format: pixel format parameters 376 * @num_planes: number of planes (including meta data planes) 377 * @width: image width 378 * @height: image height 379 * @total_size: total size in bytes 380 * @plane_addr: address of each plane 381 * @plane_size: length of each plane 382 * @plane_pitch: pitch of each plane 383 */ 384 struct dpu_hw_fmt_layout { 385 const struct dpu_format *format; 386 uint32_t num_planes; 387 uint32_t width; 388 uint32_t height; 389 uint32_t total_size; 390 uint32_t plane_addr[DPU_MAX_PLANES]; 391 uint32_t plane_size[DPU_MAX_PLANES]; 392 uint32_t plane_pitch[DPU_MAX_PLANES]; 393 }; 394 395 struct dpu_csc_cfg { 396 /* matrix coefficients in S15.16 format */ 397 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 398 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 399 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 400 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 401 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 402 }; 403 404 /** 405 * struct dpu_mdss_color - mdss color description 406 * color 0 : green 407 * color 1 : blue 408 * color 2 : red 409 * color 3 : alpha 410 */ 411 struct dpu_mdss_color { 412 u32 color_0; 413 u32 color_1; 414 u32 color_2; 415 u32 color_3; 416 }; 417 418 /* 419 * Define bit masks for h/w logging. 420 */ 421 #define DPU_DBG_MASK_NONE (1 << 0) 422 #define DPU_DBG_MASK_INTF (1 << 1) 423 #define DPU_DBG_MASK_LM (1 << 2) 424 #define DPU_DBG_MASK_CTL (1 << 3) 425 #define DPU_DBG_MASK_PINGPONG (1 << 4) 426 #define DPU_DBG_MASK_SSPP (1 << 5) 427 #define DPU_DBG_MASK_WB (1 << 6) 428 #define DPU_DBG_MASK_TOP (1 << 7) 429 #define DPU_DBG_MASK_VBIF (1 << 8) 430 #define DPU_DBG_MASK_ROT (1 << 9) 431 #define DPU_DBG_MASK_DSPP (1 << 10) 432 433 #endif /* _DPU_HW_MDSS_H */ 434