| /drivers/misc/habanalabs/gaudi/ |
| D | gaudi_security.c | 489 u32 pb_addr, mask; in gaudi_init_mme_protection_bits() local
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
516 mask |= 1U << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
517 mask |= 1U << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
518 mask |= 1U << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
519 mask |= 1U << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
520 mask |= 1U << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
521 mask |= 1U << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
522 mask |= 1U << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
523 mask |= 1U << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
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| /drivers/misc/habanalabs/goya/ |
| D | goya_security.c | 30 u32 pb_addr, mask; in goya_init_mme_protection_bits() local
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
74 mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2); in goya_init_mme_protection_bits()
75 mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2); in goya_init_mme_protection_bits()
76 mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2); in goya_init_mme_protection_bits()
77 mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 31 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) argument
34 #define SetBF(mask,value) ((value) << (0?mask)) argument
35 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
54 #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
[all …]
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| /drivers/mfd/ |
| D | sec-irq.c | 23 .mask = S2MPS11_IRQ_PWRONF_MASK,
27 .mask = S2MPS11_IRQ_PWRONR_MASK,
31 .mask = S2MPS11_IRQ_JIGONBF_MASK,
35 .mask = S2MPS11_IRQ_JIGONBR_MASK,
39 .mask = S2MPS11_IRQ_ACOKBF_MASK,
43 .mask = S2MPS11_IRQ_ACOKBR_MASK,
47 .mask = S2MPS11_IRQ_PWRON1S_MASK,
51 .mask = S2MPS11_IRQ_MRB_MASK,
55 .mask = S2MPS11_IRQ_RTC60S_MASK,
59 .mask = S2MPS11_IRQ_RTCA1_MASK,
[all …]
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| D | wm8350-irq.c | 37 int mask; member
45 .mask = WM8350_OC_LS_EINT,
51 .mask = WM8350_UV_DC1_EINT,
56 .mask = WM8350_UV_DC2_EINT,
61 .mask = WM8350_UV_DC3_EINT,
66 .mask = WM8350_UV_DC4_EINT,
71 .mask = WM8350_UV_DC5_EINT,
76 .mask = WM8350_UV_DC6_EINT,
81 .mask = WM8350_UV_LDO1_EINT,
86 .mask = WM8350_UV_LDO2_EINT,
[all …]
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| D | wm831x-irq.c | 28 int mask; member
35 .mask = WM831X_TEMP_THW_EINT,
40 .mask = WM831X_GP1_EINT,
45 .mask = WM831X_GP2_EINT,
50 .mask = WM831X_GP3_EINT,
55 .mask = WM831X_GP4_EINT,
60 .mask = WM831X_GP5_EINT,
65 .mask = WM831X_GP6_EINT,
70 .mask = WM831X_GP7_EINT,
75 .mask = WM831X_GP8_EINT,
[all …]
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| D | da9052-irq.c | 38 .mask = DA9052_IRQ_MASK_POS_1,
42 .mask = DA9052_IRQ_MASK_POS_2,
46 .mask = DA9052_IRQ_MASK_POS_3,
50 .mask = DA9052_IRQ_MASK_POS_4,
54 .mask = DA9052_IRQ_MASK_POS_5,
58 .mask = DA9052_IRQ_MASK_POS_6,
62 .mask = DA9052_IRQ_MASK_POS_7,
66 .mask = DA9052_IRQ_MASK_POS_8,
70 .mask = DA9052_IRQ_MASK_POS_1,
74 .mask = DA9052_IRQ_MASK_POS_2,
[all …]
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| D | wm5110-tables.c | 285 .mask = ARIZONA_MICD_CLAMP_FALL_EINT1
288 .mask = ARIZONA_MICD_CLAMP_RISE_EINT1
290 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
291 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
292 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
293 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
310 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
311 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
312 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
313 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[all …]
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| D | palmas.c | 47 .mask = TPS65917_RESERVED,
50 .mask = TPS65917_INT1_STATUS_PWRON,
53 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
56 .mask = TPS65917_RESERVED,
59 .mask = TPS65917_INT1_STATUS_PWRDOWN,
62 .mask = TPS65917_INT1_STATUS_HOTDIE,
65 .mask = TPS65917_INT1_STATUS_VSYS_MON,
68 .mask = TPS65917_RESERVED,
72 .mask = TPS65917_RESERVED,
76 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
[all …]
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask);
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos() argument
49 f->mask.tos = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag() argument
61 mask_val = ntohl(mask) & 0x0000FFFF; in cxgb4_fill_ipv4_frag()
65 f->mask.frag = 1; in cxgb4_fill_ipv4_frag()
68 f->mask.frag = 1; in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto() argument
80 f->mask.proto = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip() argument
[all …]
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| /drivers/iio/imu/st_lsm6dsx/ |
| D | st_lsm6dsx_core.c | 96 .mask = BIT(0),
100 .mask = BIT(7),
104 .mask = BIT(6),
130 .mask = GENMASK(7, 5),
143 .mask = GENMASK(7, 5),
158 .mask = GENMASK(4, 3),
169 .mask = GENMASK(4, 3),
181 .mask = BIT(3),
185 .mask = BIT(3),
189 .mask = BIT(5),
[all …]
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| /drivers/media/platform/rcar-vin/ |
| D | rcar-core.c | 72 unsigned int mask = 0; in rvin_group_get_mask() local
74 for (route = vin->info->routes; route->mask; route++) { in rvin_group_get_mask()
81 mask |= route->mask; in rvin_group_get_mask()
85 return mask; in rvin_group_get_mask()
118 unsigned int mask = ~0; in rvin_group_link_notify() local
169 mask &= rvin_group_get_mask(group->vin[i], csi_id, channel); in rvin_group_link_notify()
203 mask_new = mask & rvin_group_get_mask(vin, csi_id, channel); in rvin_group_link_notify()
204 vin_dbg(vin, "Try link change mask: 0x%x new: 0x%x\n", mask, mask_new); in rvin_group_link_notify()
700 for (route = vin->info->routes; route->mask; route++) { in rvin_group_notify_complete()
947 { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
[all …]
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| /drivers/video/fbdev/ |
| D | c2p_core.h | 23 unsigned int shift, u32 mask) in _transp() argument
25 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
62 u32 mask = get_mask(n); in transp8() local
67 _transp(d, 0, 1, n, mask); in transp8()
69 _transp(d, 2, 3, n, mask); in transp8()
71 _transp(d, 4, 5, n, mask); in transp8()
73 _transp(d, 6, 7, n, mask); in transp8()
78 _transp(d, 0, 2, n, mask); in transp8()
79 _transp(d, 1, 3, n, mask); in transp8()
81 _transp(d, 4, 6, n, mask); in transp8()
[all …]
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| /drivers/gpio/ |
| D | gpio-vr41xx.c | 226 u16 mask; in vr41xx_set_irq_trigger() local
229 mask = 1 << pin; in vr41xx_set_irq_trigger()
231 giu_set(GIUINTTYPL, mask); in vr41xx_set_irq_trigger()
233 giu_set(GIUINTHTSELL, mask); in vr41xx_set_irq_trigger()
235 giu_clear(GIUINTHTSELL, mask); in vr41xx_set_irq_trigger()
239 giu_set(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
240 giu_clear(GIUREDGEINHL, mask); in vr41xx_set_irq_trigger()
243 giu_clear(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
244 giu_set(GIUREDGEINHL, mask); in vr41xx_set_irq_trigger()
247 giu_set(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
[all …]
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| /drivers/platform/x86/ |
| D | mlx-platform.c | 229 .mask = MLXPLAT_CPLD_I2C_CAP_MASK,
244 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
360 .mask = BIT(0),
366 .mask = BIT(1),
376 .mask = BIT(0),
382 .mask = BIT(1),
391 .mask = BIT(0),
398 .mask = BIT(1),
408 .mask = BIT(0),
415 .mask = BIT(1),
[all …]
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| /drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| D | hw_translate_dce80.c | 48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
166 *en = index_from_vector(mask); in offset_to_id()
[all …]
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| /drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
| D | hw_translate_dce60.c | 48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
166 *en = index_from_vector(mask); in offset_to_id()
[all …]
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_matcher.c | 121 dr_mask_is_flex_parser_tnl_vxlan_gpe_set(struct mlx5dr_match_param *mask, in dr_mask_is_flex_parser_tnl_vxlan_gpe_set() argument
124 return dr_mask_is_misc3_vxlan_gpe_set(&mask->misc3) && in dr_mask_is_flex_parser_tnl_vxlan_gpe_set()
144 dr_mask_is_flex_parser_tnl_geneve_set(struct mlx5dr_match_param *mask, in dr_mask_is_flex_parser_tnl_geneve_set() argument
147 return dr_mask_is_misc_geneve_set(&mask->misc) && in dr_mask_is_flex_parser_tnl_geneve_set()
205 struct mlx5dr_match_param mask = {}; in dr_matcher_set_ste_builders() local
216 mask.outer = matcher->mask.outer; in dr_matcher_set_ste_builders()
219 mask.misc = matcher->mask.misc; in dr_matcher_set_ste_builders()
222 mask.inner = matcher->mask.inner; in dr_matcher_set_ste_builders()
225 mask.misc2 = matcher->mask.misc2; in dr_matcher_set_ste_builders()
228 mask.misc3 = matcher->mask.misc3; in dr_matcher_set_ste_builders()
[all …]
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| D | dr_ste.c | 53 #define DR_STE_SET_MPLS_MASK(lookup_type, mask, in_out, bit_mask) do { \ argument
54 DR_STE_SET_MASK_V(lookup_type, mask, mpls0_label, mask, \
56 DR_STE_SET_MASK_V(lookup_type, mask, mpls0_s_bos, mask, \
58 DR_STE_SET_MASK_V(lookup_type, mask, mpls0_exp, mask, \
60 DR_STE_SET_MASK_V(lookup_type, mask, mpls0_ttl, mask, \
64 #define DR_STE_SET_MPLS_TAG(lookup_type, mask, in_out, tag) do { \ argument
65 DR_STE_SET_TAG(lookup_type, tag, mpls0_label, mask, \
67 DR_STE_SET_TAG(lookup_type, tag, mpls0_s_bos, mask, \
69 DR_STE_SET_TAG(lookup_type, tag, mpls0_exp, mask, \
71 DR_STE_SET_TAG(lookup_type, tag, mpls0_ttl, mask, \
[all …]
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| /drivers/memory/tegra/ |
| D | tegra210.c | 26 .mask = 0xff,
40 .mask = 0xff,
54 .mask = 0xff,
68 .mask = 0xff,
82 .mask = 0xff,
96 .mask = 0xff,
110 .mask = 0xff,
124 .mask = 0xff,
138 .mask = 0xff,
152 .mask = 0xff,
[all …]
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| D | tegra30.c | 50 .mask = 0xff,
64 .mask = 0xff,
78 .mask = 0xff,
92 .mask = 0xff,
106 .mask = 0xff,
120 .mask = 0xff,
134 .mask = 0xff,
148 .mask = 0xff,
162 .mask = 0xff,
176 .mask = 0xff,
[all …]
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| D | tegra114.c | 29 .mask = 0xff,
43 .mask = 0xff,
57 .mask = 0xff,
71 .mask = 0xff,
85 .mask = 0xff,
99 .mask = 0xff,
113 .mask = 0xff,
127 .mask = 0xff,
141 .mask = 0xff,
155 .mask = 0xff,
[all …]
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| D | tegra124.c | 29 .mask = 0xff,
43 .mask = 0xff,
57 .mask = 0xff,
71 .mask = 0xff,
85 .mask = 0xff,
99 .mask = 0xff,
113 .mask = 0xff,
127 .mask = 0xff,
141 .mask = 0xff,
155 .mask = 0xff,
[all …]
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| /drivers/media/pci/ivtv/ |
| D | ivtv-gpio.c | 149 u16 mask, data; in subdev_s_clock_freq() local
151 mask = itv->card->gpio_audio_freq.mask; in subdev_s_clock_freq()
164 if (mask) in subdev_s_clock_freq()
165 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_clock_freq()
172 u16 mask; in subdev_g_tuner() local
174 mask = itv->card->gpio_audio_detect.mask; in subdev_g_tuner()
175 if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask)) in subdev_g_tuner()
186 u16 mask, data; in subdev_s_tuner() local
188 mask = itv->card->gpio_audio_mode.mask; in subdev_s_tuner()
205 if (mask) in subdev_s_tuner()
[all …]
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| /drivers/iio/accel/ |
| D | st_accel_core.c | 109 .mask = 0xf0,
123 .mask = 0xf0,
128 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
132 .mask = 0x30,
158 .mask = 0x80,
163 .mask = 0x10,
169 .mask = 0x07,
191 .mask = 0x18,
201 .mask = 0xe0,
207 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
[all …]
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