1* Qualcomm SDHCI controller (sdhci-msm) 2 3This file documents differences between the core properties in mmc.txt 4and the properties used by the sdhci-msm driver. 5 6Required properties: 7- compatible: Should contain a SoC-specific string and a IP version string: 8 version strings: 9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0 10 "qcom,sdhci-msm-v5" for sdcc version 5.0 11 For SDCC version 5.0.0, MCI registers are removed from SDCC 12 interface and some registers are moved to HC. New compatible 13 string is added to support this change - "qcom,sdhci-msm-v5". 14 full compatible strings with SoC and version: 15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4" 16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4" 17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" 18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" 19 "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4" 20 "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" 21 "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" 22 "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" 23 "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 24 NOTE that some old device tree files may be floating around that only 25 have the string "qcom,sdhci-msm-v4" without the SoC compatible string 26 but doing that should be considered a deprecated practice. 27 28- reg: Base address and length of the register in the following order: 29 - Host controller register map (required) 30 - SD Core register map (required for controllers earlier than msm-v5) 31 - CQE register map (Optional, CQE support is present on SDHC instance meant 32 for eMMC and version v4.2 and above) 33 - Inline Crypto Engine register map (optional) 34- reg-names: When CQE register map is supplied, below reg-names are required 35 - "hc" for Host controller register map 36 - "core" for SD core register map 37 - "cqhci" for CQE register map 38 - "ice" for Inline Crypto Engine register map (optional) 39- interrupts: Should contain an interrupt-specifiers for the interrupts: 40 - Host controller interrupt (required) 41- pinctrl-names: Should contain only one value - "default". 42- pinctrl-0: Should specify pin control groups used for this controller. 43- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names. 44- clock-names: Should contain the following: 45 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required) 46 "core" - SDC MMC clock (MCLK) (required) 47 "bus" - SDCC bus voter clock (optional) 48 "xo" - TCXO clock (optional) 49 "cal" - reference clock for RCLK delay calibration (optional) 50 "sleep" - sleep clock for RCLK delay calibration (optional) 51 "ice" - clock for Inline Crypto Engine (optional) 52 53- qcom,ddr-config: Certain chipsets and platforms require particular settings 54 for the DDR_CONFIG register. Use this field to specify the register 55 value as per the Hardware Programming Guide. 56 57- qcom,dll-config: Chipset and Platform specific value. Use this field to 58 specify the DLL_CONFIG register value as per Hardware Programming Guide. 59 60Optional Properties: 61* Following bus parameters are required for interconnect bandwidth scaling: 62- interconnects: Pairs of phandles and interconnect provider specifier 63 to denote the edge source and destination ports of 64 the interconnect path. 65 66- interconnect-names: For sdhc, we have two main paths. 67 1. Data path : sdhc to ddr 68 2. Config path : cpu to sdhc 69 For Data interconnect path the name supposed to be 70 is "sdhc-ddr" and for config interconnect path it is 71 "cpu-sdhc". 72 Please refer to Documentation/devicetree/bindings/ 73 interconnect/ for more details. 74 75Example: 76 77 sdhc_1: sdhci@f9824900 { 78 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 79 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 80 interrupts = <0 123 0>; 81 bus-width = <8>; 82 non-removable; 83 84 vmmc-supply = <&pm8941_l20>; 85 vqmmc-supply = <&pm8941_s3>; 86 87 pinctrl-names = "default"; 88 pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; 89 90 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; 91 clock-names = "core", "iface"; 92 interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>, 93 <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>; 94 interconnect-names = "sdhc-ddr","cpu-sdhc"; 95 96 qcom,dll-config = <0x000f642c>; 97 qcom,ddr-config = <0x80040868>; 98 }; 99 100 sdhc_2: sdhci@f98a4900 { 101 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 102 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 103 interrupts = <0 125 0>; 104 bus-width = <4>; 105 cd-gpios = <&msmgpio 62 0x1>; 106 107 vmmc-supply = <&pm8941_l21>; 108 vqmmc-supply = <&pm8941_l13>; 109 110 pinctrl-names = "default"; 111 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>; 112 113 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; 114 clock-names = "core", "iface"; 115 116 qcom,dll-config = <0x0007642c>; 117 qcom,ddr-config = <0x80040868>; 118 }; 119