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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
4 */
5#include "dra72-evm-common.dtsi"
6#include "dra72x-mmc-iodelay.dtsi"
7/ {
8	model = "TI DRA722";
9
10	memory@0 {
11		device_type = "memory";
12		reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
13	};
14
15	reserved-memory {
16		#address-cells = <2>;
17		#size-cells = <2>;
18		ranges;
19
20		ipu2_memory_region: ipu2-memory@95800000 {
21			compatible = "shared-dma-pool";
22			reg = <0x0 0x95800000 0x0 0x3800000>;
23			reusable;
24			status = "okay";
25		};
26
27		dsp1_memory_region: dsp1-memory@99000000 {
28			compatible = "shared-dma-pool";
29			reg = <0x0 0x99000000 0x0 0x4000000>;
30			reusable;
31			status = "okay";
32		};
33
34		ipu1_memory_region: ipu1-memory@9d000000 {
35			compatible = "shared-dma-pool";
36			reg = <0x0 0x9d000000 0x0 0x2000000>;
37			reusable;
38			status = "okay";
39		};
40	};
41
42	evm_1v8_sw: fixedregulator-evm_1v8 {
43		compatible = "regulator-fixed";
44		regulator-name = "evm_1v8";
45		regulator-min-microvolt = <1800000>;
46		regulator-max-microvolt = <1800000>;
47		vin-supply = <&smps4_reg>;
48		regulator-always-on;
49		regulator-boot-on;
50	};
51};
52
53&i2c1 {
54	tps65917: tps65917@58 {
55		reg = <0x58>;
56
57		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
58	};
59};
60
61#include "dra72-evm-tps65917.dtsi"
62
63&hdmi {
64	vdda-supply = <&ldo3_reg>;
65};
66
67&pcf_gpio_21 {
68	interrupt-parent = <&gpio6>;
69	interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
70};
71
72&mac_sw {
73	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
74	status = "okay";
75};
76
77&cpsw_port1 {
78	phy-handle = <&ethphy0>;
79	phy-mode = "rgmii";
80	ti,dual-emac-pvid = <1>;
81};
82
83&cpsw_port2 {
84	status = "disabled";
85};
86
87&davinci_mdio_sw {
88	ethphy0: ethernet-phy@3 {
89		reg = <3>;
90	};
91};
92
93&mmc1 {
94	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
95	pinctrl-0 = <&mmc1_pins_default>;
96	pinctrl-1 = <&mmc1_pins_hs>;
97	pinctrl-2 = <&mmc1_pins_sdr12>;
98	pinctrl-3 = <&mmc1_pins_sdr25>;
99	pinctrl-4 = <&mmc1_pins_sdr50>;
100	pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
101	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
102	vqmmc-supply = <&ldo1_reg>;
103};
104
105&mmc2 {
106	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
107	pinctrl-0 = <&mmc2_pins_default>;
108	pinctrl-1 = <&mmc2_pins_hs>;
109	pinctrl-2 = <&mmc2_pins_ddr_rev10>;
110	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
111	vmmc-supply = <&evm_1v8_sw>;
112};
113
114&ipu2 {
115	status = "okay";
116	memory-region = <&ipu2_memory_region>;
117};
118
119&ipu1 {
120	status = "okay";
121	memory-region = <&ipu1_memory_region>;
122};
123
124&dsp1 {
125	status = "okay";
126	memory-region = <&dsp1_memory_region>;
127};
128