1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2013 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/sound/fsl-imx-audmux.h> 10 11/ { 12 /* these are used by bootloader for disabling nodes */ 13 aliases { 14 led0 = &led0; 15 led1 = &led1; 16 led2 = &led2; 17 nand = &gpmi; 18 ssi0 = &ssi1; 19 usb0 = &usbh1; 20 usb1 = &usbotg; 21 }; 22 23 chosen { 24 bootargs = "console=ttymxc1,115200"; 25 }; 26 27 backlight { 28 compatible = "pwm-backlight"; 29 pwms = <&pwm4 0 5000000>; 30 brightness-levels = <0 4 8 16 32 64 128 255>; 31 default-brightness-level = <7>; 32 }; 33 34 gpio-keys { 35 compatible = "gpio-keys"; 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 user-pb { 40 label = "user_pb"; 41 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 42 linux,code = <BTN_0>; 43 }; 44 45 user-pb1x { 46 label = "user_pb1x"; 47 linux,code = <BTN_1>; 48 interrupt-parent = <&gsc>; 49 interrupts = <0>; 50 }; 51 52 key-erased { 53 label = "key-erased"; 54 linux,code = <BTN_2>; 55 interrupt-parent = <&gsc>; 56 interrupts = <1>; 57 }; 58 59 eeprom-wp { 60 label = "eeprom_wp"; 61 linux,code = <BTN_3>; 62 interrupt-parent = <&gsc>; 63 interrupts = <2>; 64 }; 65 66 tamper { 67 label = "tamper"; 68 linux,code = <BTN_4>; 69 interrupt-parent = <&gsc>; 70 interrupts = <5>; 71 }; 72 73 switch-hold { 74 label = "switch_hold"; 75 linux,code = <BTN_5>; 76 interrupt-parent = <&gsc>; 77 interrupts = <7>; 78 }; 79 }; 80 81 leds { 82 compatible = "gpio-leds"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_gpio_leds>; 85 86 led0: user1 { 87 label = "user1"; 88 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 89 default-state = "on"; 90 linux,default-trigger = "heartbeat"; 91 }; 92 93 led1: user2 { 94 label = "user2"; 95 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 96 default-state = "off"; 97 }; 98 99 led2: user3 { 100 label = "user3"; 101 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 102 default-state = "off"; 103 }; 104 }; 105 106 memory@10000000 { 107 device_type = "memory"; 108 reg = <0x10000000 0x40000000>; 109 }; 110 111 pps { 112 compatible = "pps-gpio"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_pps>; 115 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 116 status = "okay"; 117 }; 118 119 regulators { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 reg_1p0v: regulator@0 { 125 compatible = "regulator-fixed"; 126 reg = <0>; 127 regulator-name = "1P0V"; 128 regulator-min-microvolt = <1000000>; 129 regulator-max-microvolt = <1000000>; 130 regulator-always-on; 131 }; 132 133 reg_3p3v: regulator@1 { 134 compatible = "regulator-fixed"; 135 reg = <1>; 136 regulator-name = "3P3V"; 137 regulator-min-microvolt = <3300000>; 138 regulator-max-microvolt = <3300000>; 139 regulator-always-on; 140 }; 141 142 reg_usb_h1_vbus: regulator@2 { 143 compatible = "regulator-fixed"; 144 reg = <2>; 145 regulator-name = "usb_h1_vbus"; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 regulator-always-on; 149 }; 150 151 reg_usb_otg_vbus: regulator@3 { 152 compatible = "regulator-fixed"; 153 reg = <3>; 154 regulator-name = "usb_otg_vbus"; 155 regulator-min-microvolt = <5000000>; 156 regulator-max-microvolt = <5000000>; 157 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 158 enable-active-high; 159 }; 160 }; 161 162 sound-analog { 163 compatible = "fsl,imx6q-ventana-sgtl5000", 164 "fsl,imx-audio-sgtl5000"; 165 model = "sgtl5000-audio"; 166 ssi-controller = <&ssi1>; 167 audio-codec = <&sgtl5000>; 168 audio-routing = 169 "MIC_IN", "Mic Jack", 170 "Mic Jack", "Mic Bias", 171 "Headphone Jack", "HP_OUT"; 172 mux-int-port = <1>; 173 mux-ext-port = <4>; 174 }; 175}; 176 177&audmux { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ 180 status = "okay"; 181 182 ssi2 { 183 fsl,audmux-port = <1>; 184 fsl,port-config = < 185 (IMX_AUDMUX_V2_PTCR_TFSDIR | 186 IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ 187 IMX_AUDMUX_V2_PTCR_TCLKDIR | 188 IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ 189 IMX_AUDMUX_V2_PTCR_SYN) 190 IMX_AUDMUX_V2_PDCR_RXDSEL(4) 191 >; 192 }; 193 194 aud5 { 195 fsl,audmux-port = <4>; 196 fsl,port-config = < 197 IMX_AUDMUX_V2_PTCR_SYN 198 IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; 199 }; 200}; 201 202&can1 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_flexcan1>; 205 status = "okay"; 206}; 207 208&clks { 209 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 210 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 211 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 212 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 213}; 214 215&ecspi2 { 216 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_ecspi2>; 219 status = "okay"; 220}; 221 222&fec { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_enet>; 225 phy-mode = "rgmii-id"; 226 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 227 status = "okay"; 228}; 229 230&gpmi { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_gpmi_nand>; 233 status = "okay"; 234}; 235 236&hdmi { 237 ddc-i2c-bus = <&i2c3>; 238 status = "okay"; 239}; 240 241&i2c1 { 242 clock-frequency = <100000>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_i2c1>; 245 status = "okay"; 246 247 gsc: gsc@20 { 248 compatible = "gw,gsc"; 249 reg = <0x20>; 250 interrupt-parent = <&gpio1>; 251 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 252 interrupt-controller; 253 #interrupt-cells = <1>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 257 adc { 258 compatible = "gw,gsc-adc"; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 262 channel@0 { 263 gw,mode = <0>; 264 reg = <0x00>; 265 label = "temp"; 266 }; 267 268 channel@2 { 269 gw,mode = <1>; 270 reg = <0x02>; 271 label = "vdd_vin"; 272 }; 273 274 channel@5 { 275 gw,mode = <1>; 276 reg = <0x05>; 277 label = "vdd_3p3"; 278 }; 279 280 channel@8 { 281 gw,mode = <1>; 282 reg = <0x08>; 283 label = "vdd_bat"; 284 }; 285 286 channel@b { 287 gw,mode = <1>; 288 reg = <0x0b>; 289 label = "vdd_5p0"; 290 }; 291 292 channel@e { 293 gw,mode = <1>; 294 reg = <0xe>; 295 label = "vdd_arm"; 296 }; 297 298 channel@11 { 299 gw,mode = <1>; 300 reg = <0x11>; 301 label = "vdd_soc"; 302 }; 303 304 channel@14 { 305 gw,mode = <1>; 306 reg = <0x14>; 307 label = "vdd_3p0"; 308 }; 309 310 channel@17 { 311 gw,mode = <1>; 312 reg = <0x17>; 313 label = "vdd_1p5"; 314 }; 315 316 channel@1d { 317 gw,mode = <1>; 318 reg = <0x1d>; 319 label = "vdd_1p8"; 320 }; 321 322 channel@20 { 323 gw,mode = <1>; 324 reg = <0x20>; 325 label = "vdd_1p0"; 326 }; 327 328 channel@23 { 329 gw,mode = <1>; 330 reg = <0x23>; 331 label = "vdd_2p5"; 332 }; 333 334 channel@26 { 335 gw,mode = <1>; 336 reg = <0x26>; 337 label = "vdd_gps"; 338 }; 339 }; 340 341 fan-controller@2c { 342 compatible = "gw,gsc-fan"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 reg = <0x2c>; 346 }; 347 }; 348 349 gsc_gpio: gpio@23 { 350 compatible = "nxp,pca9555"; 351 reg = <0x23>; 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-parent = <&gsc>; 355 interrupts = <4>; 356 }; 357 358 eeprom1: eeprom@50 { 359 compatible = "atmel,24c02"; 360 reg = <0x50>; 361 pagesize = <16>; 362 }; 363 364 eeprom2: eeprom@51 { 365 compatible = "atmel,24c02"; 366 reg = <0x51>; 367 pagesize = <16>; 368 }; 369 370 eeprom3: eeprom@52 { 371 compatible = "atmel,24c02"; 372 reg = <0x52>; 373 pagesize = <16>; 374 }; 375 376 eeprom4: eeprom@53 { 377 compatible = "atmel,24c02"; 378 reg = <0x53>; 379 pagesize = <16>; 380 }; 381 382 rtc: ds1672@68 { 383 compatible = "dallas,ds1672"; 384 reg = <0x68>; 385 }; 386}; 387 388&i2c2 { 389 clock-frequency = <100000>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_i2c2>; 392 status = "okay"; 393 394 pmic: pfuze100@8 { 395 compatible = "fsl,pfuze100"; 396 reg = <0x08>; 397 398 regulators { 399 sw1a_reg: sw1ab { 400 regulator-min-microvolt = <300000>; 401 regulator-max-microvolt = <1875000>; 402 regulator-boot-on; 403 regulator-always-on; 404 regulator-ramp-delay = <6250>; 405 }; 406 407 sw1c_reg: sw1c { 408 regulator-min-microvolt = <300000>; 409 regulator-max-microvolt = <1875000>; 410 regulator-boot-on; 411 regulator-always-on; 412 regulator-ramp-delay = <6250>; 413 }; 414 415 sw2_reg: sw2 { 416 regulator-min-microvolt = <800000>; 417 regulator-max-microvolt = <3950000>; 418 regulator-boot-on; 419 regulator-always-on; 420 }; 421 422 sw3a_reg: sw3a { 423 regulator-min-microvolt = <400000>; 424 regulator-max-microvolt = <1975000>; 425 regulator-boot-on; 426 regulator-always-on; 427 }; 428 429 sw3b_reg: sw3b { 430 regulator-min-microvolt = <400000>; 431 regulator-max-microvolt = <1975000>; 432 regulator-boot-on; 433 regulator-always-on; 434 }; 435 436 sw4_reg: sw4 { 437 regulator-min-microvolt = <800000>; 438 regulator-max-microvolt = <3300000>; 439 }; 440 441 swbst_reg: swbst { 442 regulator-min-microvolt = <5000000>; 443 regulator-max-microvolt = <5150000>; 444 regulator-boot-on; 445 regulator-always-on; 446 }; 447 448 snvs_reg: vsnvs { 449 regulator-min-microvolt = <1000000>; 450 regulator-max-microvolt = <3000000>; 451 regulator-boot-on; 452 regulator-always-on; 453 }; 454 455 vref_reg: vrefddr { 456 regulator-boot-on; 457 regulator-always-on; 458 }; 459 460 vgen1_reg: vgen1 { 461 regulator-min-microvolt = <800000>; 462 regulator-max-microvolt = <1550000>; 463 }; 464 465 vgen2_reg: vgen2 { 466 regulator-min-microvolt = <800000>; 467 regulator-max-microvolt = <1550000>; 468 }; 469 470 vgen3_reg: vgen3 { 471 regulator-min-microvolt = <1800000>; 472 regulator-max-microvolt = <3300000>; 473 }; 474 475 vgen4_reg: vgen4 { 476 regulator-min-microvolt = <1800000>; 477 regulator-max-microvolt = <3300000>; 478 regulator-always-on; 479 }; 480 481 vgen5_reg: vgen5 { 482 regulator-min-microvolt = <1800000>; 483 regulator-max-microvolt = <3300000>; 484 regulator-always-on; 485 }; 486 487 vgen6_reg: vgen6 { 488 regulator-min-microvolt = <1800000>; 489 regulator-max-microvolt = <3300000>; 490 regulator-always-on; 491 }; 492 }; 493 }; 494}; 495 496&i2c3 { 497 clock-frequency = <100000>; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_i2c3>; 500 status = "okay"; 501 502 sgtl5000: audio-codec@a { 503 compatible = "fsl,sgtl5000"; 504 reg = <0x0a>; 505 clocks = <&clks IMX6QDL_CLK_CKO>; 506 VDDA-supply = <&sw4_reg>; 507 VDDIO-supply = <®_3p3v>; 508 }; 509 510 touchscreen: egalax_ts@4 { 511 compatible = "eeti,egalax_ts"; 512 reg = <0x04>; 513 interrupt-parent = <&gpio7>; 514 interrupts = <12 2>; 515 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; 516 }; 517 518 accel@1e { 519 compatible = "nxp,fxos8700"; 520 reg = <0x1e>; 521 }; 522}; 523 524&ldb { 525 status = "okay"; 526 527 lvds-channel@0 { 528 fsl,data-mapping = "spwg"; 529 fsl,data-width = <18>; 530 status = "okay"; 531 532 display-timings { 533 native-mode = <&timing0>; 534 timing0: hsd100pxn1 { 535 clock-frequency = <65000000>; 536 hactive = <1024>; 537 vactive = <768>; 538 hback-porch = <220>; 539 hfront-porch = <40>; 540 vback-porch = <21>; 541 vfront-porch = <7>; 542 hsync-len = <60>; 543 vsync-len = <10>; 544 }; 545 }; 546 }; 547}; 548 549&pcie { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_pcie>; 552 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 553 status = "okay"; 554}; 555 556&pwm1 { 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ 559 status = "disabled"; 560}; 561 562&pwm2 { 563 pinctrl-names = "default"; 564 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 565 status = "disabled"; 566}; 567 568&pwm3 { 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 571 status = "disabled"; 572}; 573 574&pwm4 { 575 #pwm-cells = <2>; 576 pinctrl-names = "default", "state_dio"; 577 pinctrl-0 = <&pinctrl_pwm4_backlight>; 578 pinctrl-1 = <&pinctrl_pwm4_dio>; 579 status = "okay"; 580}; 581 582&ssi1 { 583 status = "okay"; 584}; 585 586&ssi2 { 587 status = "okay"; 588}; 589 590&uart1 { 591 pinctrl-names = "default"; 592 pinctrl-0 = <&pinctrl_uart1>; 593 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 594 status = "okay"; 595}; 596 597&uart2 { 598 pinctrl-names = "default"; 599 pinctrl-0 = <&pinctrl_uart2>; 600 status = "okay"; 601}; 602 603&uart5 { 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_uart5>; 606 status = "okay"; 607}; 608 609&usbotg { 610 vbus-supply = <®_usb_otg_vbus>; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&pinctrl_usbotg>; 613 disable-over-current; 614 status = "okay"; 615}; 616 617&usbh1 { 618 vbus-supply = <®_usb_h1_vbus>; 619 status = "okay"; 620}; 621 622&usdhc3 { 623 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 624 pinctrl-0 = <&pinctrl_usdhc3>; 625 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 626 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 627 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 628 vmmc-supply = <®_3p3v>; 629 no-1-8-v; /* firmware will remove if board revision supports */ 630 status = "okay"; 631}; 632 633&wdog1 { 634 status = "disabled"; 635}; 636 637&wdog2 { 638 pinctrl-names = "default"; 639 pinctrl-0 = <&pinctrl_wdog>; 640 fsl,ext-reset-output; 641 status = "okay"; 642}; 643 644&iomuxc { 645 pinctrl_audmux: audmuxgrp { 646 fsl,pins = < 647 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 648 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 649 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 650 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 651 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 652 MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 653 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 654 MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 655 >; 656 }; 657 658 pinctrl_enet: enetgrp { 659 fsl,pins = < 660 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 661 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 662 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 663 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 664 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 665 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 666 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 667 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 668 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 669 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 670 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 671 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 672 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 673 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 674 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 675 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 676 >; 677 }; 678 679 pinctrl_ecspi2: escpi2grp { 680 fsl,pins = < 681 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 682 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 683 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 684 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 685 >; 686 }; 687 688 pinctrl_flexcan1: flexcan1grp { 689 fsl,pins = < 690 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 691 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 692 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 693 >; 694 }; 695 696 pinctrl_gpio_leds: gpioledsgrp { 697 fsl,pins = < 698 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 699 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 700 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 701 >; 702 }; 703 704 pinctrl_gpmi_nand: gpminandgrp { 705 fsl,pins = < 706 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 707 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 708 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 709 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 710 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 711 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 712 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 713 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 714 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 715 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 716 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 717 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 718 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 719 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 720 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 721 >; 722 }; 723 724 pinctrl_i2c1: i2c1grp { 725 fsl,pins = < 726 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 727 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 728 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 729 >; 730 }; 731 732 pinctrl_i2c2: i2c2grp { 733 fsl,pins = < 734 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 735 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 736 >; 737 }; 738 739 pinctrl_i2c3: i2c3grp { 740 fsl,pins = < 741 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 742 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 743 >; 744 }; 745 746 pinctrl_pcie: pciegrp { 747 fsl,pins = < 748 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 749 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 750 >; 751 }; 752 753 pinctrl_pps: ppsgrp { 754 fsl,pins = < 755 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 756 >; 757 }; 758 759 pinctrl_pwm1: pwm1grp { 760 fsl,pins = < 761 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 762 >; 763 }; 764 765 pinctrl_pwm2: pwm2grp { 766 fsl,pins = < 767 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 768 >; 769 }; 770 771 pinctrl_pwm3: pwm3grp { 772 fsl,pins = < 773 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 774 >; 775 }; 776 777 pinctrl_pwm4_backlight: pwm4grpbacklight { 778 fsl,pins = < 779 /* LVDS_PWM J6.5 */ 780 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 781 >; 782 }; 783 784 pinctrl_pwm4_dio: pwm4grpdio { 785 fsl,pins = < 786 /* DIO3 J16.4 */ 787 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 788 >; 789 }; 790 791 pinctrl_uart1: uart1grp { 792 fsl,pins = < 793 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 794 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 795 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 796 >; 797 }; 798 799 pinctrl_uart2: uart2grp { 800 fsl,pins = < 801 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 802 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 803 >; 804 }; 805 806 pinctrl_uart5: uart5grp { 807 fsl,pins = < 808 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 809 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 810 >; 811 }; 812 813 pinctrl_usbotg: usbotggrp { 814 fsl,pins = < 815 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 816 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 817 >; 818 }; 819 820 pinctrl_usdhc3: usdhc3grp { 821 fsl,pins = < 822 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 823 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 824 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 825 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 826 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 827 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 828 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 829 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 830 >; 831 }; 832 833 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 834 fsl,pins = < 835 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 836 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 837 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 838 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 839 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 840 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 841 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 842 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 843 >; 844 }; 845 846 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 847 fsl,pins = < 848 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 849 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 850 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 851 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 852 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 853 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 854 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 855 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 856 >; 857 }; 858 859 pinctrl_wdog: wdoggrp { 860 fsl,pins = < 861 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 862 >; 863 }; 864}; 865