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1// SPDX-License-Identifier: (GPL-2.0)
2/*
3 * Device tree for the Tolino Shine 3 ebook reader
4 *
5 * Name on mainboard is: 37NB-E60K00+4A4
6 * Serials start with: E60K02 (a number also seen in
7 * vendor kernel sources)
8 *
9 * This mainboard seems to be equipped with different SoCs.
10 * In the Toline Shine 3 ebook reader it is a i.MX6SL
11 *
12 * Copyright 2019 Andreas Kemnade
13 * based on works
14 * Copyright 2016 Freescale Semiconductor, Inc.
15 */
16
17/dts-v1/;
18
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/gpio/gpio.h>
21#include "imx6sl.dtsi"
22#include "e60k02.dtsi"
23
24/ {
25	model = "Tolino Shine 3";
26	compatible = "kobo,tolino-shine3", "fsl,imx6sl";
27};
28
29&gpio_keys {
30	pinctrl-names = "default";
31	pinctrl-0 = <&pinctrl_gpio_keys>;
32};
33
34&i2c1 {
35	pinctrl-names = "default","sleep";
36	pinctrl-0 = <&pinctrl_i2c1>;
37	pinctrl-1 = <&pinctrl_i2c1_sleep>;
38};
39
40&i2c2 {
41	pinctrl-names = "default","sleep";
42	pinctrl-0 = <&pinctrl_i2c2>;
43	pinctrl-1 = <&pinctrl_i2c2_sleep>;
44};
45
46&i2c3 {
47	pinctrl-names = "default";
48	pinctrl-0 = <&pinctrl_i2c3>;
49};
50
51&iomuxc {
52	pinctrl-names = "default";
53	pinctrl-0 = <&pinctrl_hog>;
54
55	pinctrl_gpio_keys: gpio-keysgrp {
56		fsl,pins = <
57			MX6SL_PAD_SD1_DAT1__GPIO5_IO08	0x17059	/* PWR_SW */
58			MX6SL_PAD_SD1_DAT4__GPIO5_IO12	0x17059	/* HALL_EN */
59		>;
60	};
61
62	pinctrl_hog: hoggrp {
63		fsl,pins = <
64			MX6SL_PAD_LCD_DAT0__GPIO2_IO20	0x79
65			MX6SL_PAD_LCD_DAT1__GPIO2_IO21	0x79
66			MX6SL_PAD_LCD_DAT2__GPIO2_IO22	0x79
67			MX6SL_PAD_LCD_DAT3__GPIO2_IO23	0x79
68			MX6SL_PAD_LCD_DAT4__GPIO2_IO24	0x79
69			MX6SL_PAD_LCD_DAT5__GPIO2_IO25	0x79
70			MX6SL_PAD_LCD_DAT6__GPIO2_IO26	0x79
71			MX6SL_PAD_LCD_DAT7__GPIO2_IO27	0x79
72			MX6SL_PAD_LCD_DAT8__GPIO2_IO28	0x79
73			MX6SL_PAD_LCD_DAT9__GPIO2_IO29	0x79
74			MX6SL_PAD_LCD_DAT10__GPIO2_IO30	0x79
75			MX6SL_PAD_LCD_DAT11__GPIO2_IO31	0x79
76			MX6SL_PAD_LCD_DAT12__GPIO3_IO00	0x79
77			MX6SL_PAD_LCD_DAT13__GPIO3_IO01	0x79
78			MX6SL_PAD_LCD_DAT14__GPIO3_IO02	0x79
79			MX6SL_PAD_LCD_DAT15__GPIO3_IO03	0x79
80			MX6SL_PAD_LCD_DAT16__GPIO3_IO04	0x79
81			MX6SL_PAD_LCD_DAT17__GPIO3_IO05	0x79
82			MX6SL_PAD_LCD_DAT18__GPIO3_IO06	0x79
83			MX6SL_PAD_LCD_DAT19__GPIO3_IO07	0x79
84			MX6SL_PAD_LCD_DAT20__GPIO3_IO08	0x79
85			MX6SL_PAD_LCD_DAT21__GPIO3_IO09	0x79
86			MX6SL_PAD_LCD_DAT22__GPIO3_IO10	0x79
87			MX6SL_PAD_LCD_DAT23__GPIO3_IO11	0x79
88			MX6SL_PAD_LCD_CLK__GPIO2_IO15		0x79
89			MX6SL_PAD_LCD_ENABLE__GPIO2_IO16	0x79
90			MX6SL_PAD_LCD_HSYNC__GPIO2_IO17	0x79
91			MX6SL_PAD_LCD_VSYNC__GPIO2_IO18	0x79
92			MX6SL_PAD_LCD_RESET__GPIO2_IO19	0x79
93			MX6SL_PAD_KEY_COL3__GPIO3_IO30		0x79
94			MX6SL_PAD_KEY_ROW7__GPIO4_IO07		0x79
95			MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13	0x79
96			MX6SL_PAD_KEY_COL5__GPIO4_IO02		0x79
97			MX6SL_PAD_KEY_ROW6__GPIO4_IO05		0x79
98		>;
99	};
100
101	pinctrl_i2c1: i2c1grp {
102		fsl,pins = <
103			MX6SL_PAD_I2C1_SCL__I2C1_SCL	 0x4001f8b1
104			MX6SL_PAD_I2C1_SDA__I2C1_SDA	 0x4001f8b1
105		>;
106	};
107
108	pinctrl_i2c1_sleep: i2c1grp-sleep {
109		fsl,pins = <
110			MX6SL_PAD_I2C1_SCL__I2C1_SCL	 0x400108b1
111			MX6SL_PAD_I2C1_SDA__I2C1_SDA	 0x400108b1
112		>;
113	};
114
115	pinctrl_i2c2: i2c2grp {
116		fsl,pins = <
117			MX6SL_PAD_I2C2_SCL__I2C2_SCL	 0x4001f8b1
118			MX6SL_PAD_I2C2_SDA__I2C2_SDA	 0x4001f8b1
119		>;
120	};
121
122	pinctrl_i2c2_sleep: i2c2grp-sleep {
123		fsl,pins = <
124			MX6SL_PAD_I2C2_SCL__I2C2_SCL	 0x400108b1
125			MX6SL_PAD_I2C2_SDA__I2C2_SDA	 0x400108b1
126		>;
127	};
128
129	pinctrl_i2c3: i2c3grp {
130		fsl,pins = <
131			MX6SL_PAD_REF_CLK_24M__I2C3_SCL  0x4001f8b1
132			MX6SL_PAD_REF_CLK_32K__I2C3_SDA  0x4001f8b1
133		>;
134	};
135
136	pinctrl_led: ledgrp {
137		fsl,pins = <
138			MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
139		>;
140	};
141
142	pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
143		fsl,pins = <
144			MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10		0x10059 /* HWEN */
145		>;
146	};
147
148	pinctrl_ricoh_gpio: ricoh_gpiogrp {
149		fsl,pins = <
150			MX6SL_PAD_SD1_CLK__GPIO5_IO15                  0x1b8b1 /* ricoh619 chg */
151			MX6SL_PAD_SD1_DAT0__GPIO5_IO11        0x1b8b1 /* ricoh619 irq */
152			MX6SL_PAD_KEY_COL2__GPIO3_IO28                         0x1b8b1 /* ricoh619 bat_low_int */
153		>;
154	};
155
156	pinctrl_uart1: uart1grp {
157		fsl,pins = <
158			MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
159			MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1
160		>;
161	};
162
163	pinctrl_usbotg1: usbotg1grp {
164		fsl,pins = <
165			MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
166		>;
167	};
168
169	pinctrl_usdhc2: usdhc2grp {
170		fsl,pins = <
171			MX6SL_PAD_SD2_CMD__SD2_CMD		0x17059
172			MX6SL_PAD_SD2_CLK__SD2_CLK		0x13059
173			MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x17059
174			MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x17059
175			MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x17059
176			MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x17059
177		>;
178	};
179
180	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
181		fsl,pins = <
182			MX6SL_PAD_SD2_CMD__SD2_CMD		0x170b9
183			MX6SL_PAD_SD2_CLK__SD2_CLK		0x130b9
184			MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
185			MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
186			MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
187			MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
188		>;
189	};
190
191	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
192		fsl,pins = <
193			MX6SL_PAD_SD2_CMD__SD2_CMD		0x170f9
194			MX6SL_PAD_SD2_CLK__SD2_CLK		0x130f9
195			MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
196			MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
197			MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
198			MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
199		>;
200	};
201
202	pinctrl_usdhc2_sleep: usdhc2grp-sleep {
203		fsl,pins = <
204			MX6SL_PAD_SD2_CMD__GPIO5_IO04		0x100f9
205			MX6SL_PAD_SD2_CLK__GPIO5_IO05		0x100f9
206			MX6SL_PAD_SD2_DAT0__GPIO5_IO01		0x100f9
207			MX6SL_PAD_SD2_DAT1__GPIO4_IO30		0x100f9
208			MX6SL_PAD_SD2_DAT2__GPIO5_IO03		0x100f9
209			MX6SL_PAD_SD2_DAT3__GPIO4_IO28		0x100f9
210		>;
211	};
212
213	pinctrl_usdhc3: usdhc3grp {
214		fsl,pins = <
215			MX6SL_PAD_SD3_CMD__SD3_CMD	0x11059
216			MX6SL_PAD_SD3_CLK__SD3_CLK	0x11059
217			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x11059
218			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x11059
219			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x11059
220			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x11059
221		>;
222	};
223
224	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
225		fsl,pins = <
226			MX6SL_PAD_SD3_CMD__SD3_CMD	0x170b9
227			MX6SL_PAD_SD3_CLK__SD3_CLK	0x170b9
228			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x170b9
229			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x170b9
230			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x170b9
231			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x170b9
232		>;
233	};
234
235	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
236		fsl,pins = <
237			MX6SL_PAD_SD3_CMD__SD3_CMD	0x170f9
238			MX6SL_PAD_SD3_CLK__SD3_CLK	0x170f9
239			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x170f9
240			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x170f9
241			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x170f9
242			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x170f9
243		>;
244	};
245
246	pinctrl_usdhc3_sleep: usdhc3grp-sleep {
247		fsl,pins = <
248			MX6SL_PAD_SD3_CMD__GPIO5_IO21	0x100c1
249			MX6SL_PAD_SD3_CLK__GPIO5_IO18	0x100c1
250			MX6SL_PAD_SD3_DAT0__GPIO5_IO19	0x100c1
251			MX6SL_PAD_SD3_DAT1__GPIO5_IO20	0x100c1
252			MX6SL_PAD_SD3_DAT2__GPIO5_IO16	0x100c1
253			MX6SL_PAD_SD3_DAT3__GPIO5_IO17	0x100c1
254		>;
255	};
256
257	pinctrl_wifi_power: wifi-powergrp {
258		fsl,pins = <
259			MX6SL_PAD_SD2_DAT6__GPIO4_IO29	0x10059	/* WIFI_3V3_ON */
260		>;
261	};
262
263	pinctrl_wifi_reset: wifi-resetgrp {
264		fsl,pins = <
265			MX6SL_PAD_SD2_DAT7__GPIO5_IO00	0x10059	/* WIFI_RST */
266		>;
267	};
268};
269
270&leds {
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_led>;
273};
274
275&lm3630a {
276	pinctrl-names = "default";
277	pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
278};
279
280&reg_wifi {
281	pinctrl-names = "default";
282	pinctrl-0 = <&pinctrl_wifi_power>;
283};
284
285&reg_vdd1p1 {
286	vin-supply = <&dcdc2_reg>;
287};
288
289&reg_vdd2p5 {
290	vin-supply = <&dcdc2_reg>;
291};
292
293&ricoh619 {
294	pinctrl-names = "default";
295	pinctrl-0 = <&pinctrl_ricoh_gpio>;
296};
297
298&uart1 {
299	pinctrl-names = "default";
300	pinctrl-0 = <&pinctrl_uart1>;
301};
302
303&usdhc2 {
304	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
305	pinctrl-0 = <&pinctrl_usdhc2>;
306	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
307	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
308	pinctrl-3 = <&pinctrl_usdhc2_sleep>;
309};
310
311&usdhc3 {
312	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
313	pinctrl-0 = <&pinctrl_usdhc3>;
314	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
315	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
316	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
317};
318
319&wifi_pwrseq {
320	pinctrl-names = "default";
321	pinctrl-0 = <&pinctrl_wifi_reset>;
322};
323