1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Based on "omap4.dtsi" 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/omap.h> 12#include <dt-bindings/clock/omap5.h> 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 compatible = "ti,omap5"; 19 interrupt-parent = <&wakeupgen>; 20 chosen { }; 21 22 aliases { 23 i2c0 = &i2c1; 24 i2c1 = &i2c2; 25 i2c2 = &i2c3; 26 i2c3 = &i2c4; 27 i2c4 = &i2c5; 28 mmc0 = &mmc1; 29 mmc1 = &mmc2; 30 mmc2 = &mmc3; 31 mmc3 = &mmc4; 32 mmc4 = &mmc5; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 serial4 = &uart5; 38 serial5 = &uart6; 39 rproc0 = &dsp; 40 rproc1 = &ipu; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a15"; 50 reg = <0x0>; 51 52 operating-points = < 53 /* kHz uV */ 54 1000000 1060000 55 1500000 1250000 56 >; 57 58 clocks = <&dpll_mpu_ck>; 59 clock-names = "cpu"; 60 61 clock-latency = <300000>; /* From omap-cpufreq driver */ 62 63 /* cooling options */ 64 #cooling-cells = <2>; /* min followed by max */ 65 }; 66 cpu@1 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a15"; 69 reg = <0x1>; 70 71 operating-points = < 72 /* kHz uV */ 73 1000000 1060000 74 1500000 1250000 75 >; 76 77 clocks = <&dpll_mpu_ck>; 78 clock-names = "cpu"; 79 80 clock-latency = <300000>; /* From omap-cpufreq driver */ 81 82 /* cooling options */ 83 #cooling-cells = <2>; /* min followed by max */ 84 }; 85 }; 86 87 thermal-zones { 88 #include "omap4-cpu-thermal.dtsi" 89 #include "omap5-gpu-thermal.dtsi" 90 #include "omap5-core-thermal.dtsi" 91 }; 92 93 timer { 94 compatible = "arm,armv7-timer"; 95 /* PPI secure/nonsecure IRQ */ 96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; 100 interrupt-parent = <&gic>; 101 }; 102 103 pmu { 104 compatible = "arm,cortex-a15-pmu"; 105 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 107 }; 108 109 gic: interrupt-controller@48211000 { 110 compatible = "arm,cortex-a15-gic"; 111 interrupt-controller; 112 #interrupt-cells = <3>; 113 reg = <0 0x48211000 0 0x1000>, 114 <0 0x48212000 0 0x2000>, 115 <0 0x48214000 0 0x2000>, 116 <0 0x48216000 0 0x2000>; 117 interrupt-parent = <&gic>; 118 }; 119 120 wakeupgen: interrupt-controller@48281000 { 121 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 122 interrupt-controller; 123 #interrupt-cells = <3>; 124 reg = <0 0x48281000 0 0x1000>; 125 interrupt-parent = <&gic>; 126 }; 127 128 /* 129 * The soc node represents the soc top level view. It is used for IPs 130 * that are not memory mapped in the MPU view or for the MPU itself. 131 */ 132 soc { 133 compatible = "ti,omap-infra"; 134 mpu { 135 compatible = "ti,omap4-mpu"; 136 ti,hwmods = "mpu"; 137 sram = <&ocmcram>; 138 }; 139 }; 140 141 /* 142 * XXX: Use a flat representation of the OMAP3 interconnect. 143 * The real OMAP interconnect network is quite complex. 144 * Since it will not bring real advantage to represent that in DT for 145 * the moment, just use a fake OCP bus entry to represent the whole bus 146 * hierarchy. 147 */ 148 ocp { 149 compatible = "ti,omap5-l3-noc", "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges = <0 0 0 0xc0000000>; 153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 154 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 155 reg = <0 0x44000000 0 0x2000>, 156 <0 0x44800000 0 0x3000>, 157 <0 0x45000000 0 0x4000>; 158 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 160 161 l4_wkup: interconnect@4ae00000 { 162 }; 163 164 l4_cfg: interconnect@4a000000 { 165 }; 166 167 l4_per: interconnect@48000000 { 168 }; 169 170 l4_abe: interconnect@40100000 { 171 }; 172 173 ocmcram: sram@40300000 { 174 compatible = "mmio-sram"; 175 reg = <0x40300000 0x20000>; /* 128k */ 176 }; 177 178 gpmc: gpmc@50000000 { 179 compatible = "ti,omap4430-gpmc"; 180 reg = <0x50000000 0x1000>; 181 #address-cells = <2>; 182 #size-cells = <1>; 183 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 184 dmas = <&sdma 4>; 185 dma-names = "rxtx"; 186 gpmc,num-cs = <8>; 187 gpmc,num-waitpins = <4>; 188 ti,hwmods = "gpmc"; 189 clocks = <&l3_iclk_div>; 190 clock-names = "fck"; 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 gpio-controller; 194 #gpio-cells = <2>; 195 }; 196 197 target-module@55082000 { 198 compatible = "ti,sysc-omap2", "ti,sysc"; 199 reg = <0x55082000 0x4>, 200 <0x55082010 0x4>, 201 <0x55082014 0x4>; 202 reg-names = "rev", "sysc", "syss"; 203 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 204 <SYSC_IDLE_NO>, 205 <SYSC_IDLE_SMART>; 206 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 207 SYSC_OMAP2_SOFTRESET | 208 SYSC_OMAP2_AUTOIDLE)>; 209 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; 210 clock-names = "fck"; 211 resets = <&prm_core 2>; 212 reset-names = "rstctrl"; 213 ranges = <0x0 0x55082000 0x100>; 214 #size-cells = <1>; 215 #address-cells = <1>; 216 217 mmu_ipu: mmu@0 { 218 compatible = "ti,omap4-iommu"; 219 reg = <0x0 0x100>; 220 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 221 #iommu-cells = <0>; 222 ti,iommu-bus-err-back; 223 }; 224 }; 225 226 dsp: dsp { 227 compatible = "ti,omap5-dsp"; 228 ti,bootreg = <&scm_conf 0x304 0>; 229 iommus = <&mmu_dsp>; 230 resets = <&prm_dsp 0>; 231 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; 232 firmware-name = "omap5-dsp-fw.xe64T"; 233 mboxes = <&mailbox &mbox_dsp>; 234 status = "disabled"; 235 }; 236 237 ipu: ipu@55020000 { 238 compatible = "ti,omap5-ipu"; 239 reg = <0x55020000 0x10000>; 240 reg-names = "l2ram"; 241 iommus = <&mmu_ipu>; 242 resets = <&prm_core 0>, <&prm_core 1>; 243 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; 244 firmware-name = "omap5-ipu-fw.xem4"; 245 mboxes = <&mailbox &mbox_ipu>; 246 status = "disabled"; 247 }; 248 249 dmm@4e000000 { 250 compatible = "ti,omap5-dmm"; 251 reg = <0x4e000000 0x800>; 252 interrupts = <0 113 0x4>; 253 ti,hwmods = "dmm"; 254 }; 255 256 emif1: emif@4c000000 { 257 compatible = "ti,emif-4d5"; 258 ti,hwmods = "emif1"; 259 ti,no-idle-on-init; 260 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 261 reg = <0x4c000000 0x400>; 262 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 263 hw-caps-read-idle-ctrl; 264 hw-caps-ll-interface; 265 hw-caps-temp-alert; 266 }; 267 268 emif2: emif@4d000000 { 269 compatible = "ti,emif-4d5"; 270 ti,hwmods = "emif2"; 271 ti,no-idle-on-init; 272 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 273 reg = <0x4d000000 0x400>; 274 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 275 hw-caps-read-idle-ctrl; 276 hw-caps-ll-interface; 277 hw-caps-temp-alert; 278 }; 279 280 aes1_target: target-module@4b501000 { 281 compatible = "ti,sysc-omap2", "ti,sysc"; 282 reg = <0x4b501080 0x4>, 283 <0x4b501084 0x4>, 284 <0x4b501088 0x4>; 285 reg-names = "rev", "sysc", "syss"; 286 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 287 SYSC_OMAP2_AUTOIDLE)>; 288 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 289 <SYSC_IDLE_NO>, 290 <SYSC_IDLE_SMART>, 291 <SYSC_IDLE_SMART_WKUP>; 292 ti,syss-mask = <1>; 293 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 294 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; 295 clock-names = "fck"; 296 #address-cells = <1>; 297 #size-cells = <1>; 298 ranges = <0x0 0x4b501000 0x1000>; 299 300 aes1: aes@0 { 301 compatible = "ti,omap4-aes"; 302 reg = <0 0xa0>; 303 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 304 dmas = <&sdma 111>, <&sdma 110>; 305 dma-names = "tx", "rx"; 306 }; 307 }; 308 309 aes2_target: target-module@4b701000 { 310 compatible = "ti,sysc-omap2", "ti,sysc"; 311 reg = <0x4b701080 0x4>, 312 <0x4b701084 0x4>, 313 <0x4b701088 0x4>; 314 reg-names = "rev", "sysc", "syss"; 315 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 316 SYSC_OMAP2_AUTOIDLE)>; 317 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 318 <SYSC_IDLE_NO>, 319 <SYSC_IDLE_SMART>, 320 <SYSC_IDLE_SMART_WKUP>; 321 ti,syss-mask = <1>; 322 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 323 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; 324 clock-names = "fck"; 325 #address-cells = <1>; 326 #size-cells = <1>; 327 ranges = <0x0 0x4b701000 0x1000>; 328 329 aes2: aes@0 { 330 compatible = "ti,omap4-aes"; 331 reg = <0 0xa0>; 332 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 333 dmas = <&sdma 114>, <&sdma 113>; 334 dma-names = "tx", "rx"; 335 }; 336 }; 337 338 sham_target: target-module@4b100000 { 339 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 340 reg = <0x4b100100 0x4>, 341 <0x4b100110 0x4>, 342 <0x4b100114 0x4>; 343 reg-names = "rev", "sysc", "syss"; 344 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 345 SYSC_OMAP2_AUTOIDLE)>; 346 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 347 <SYSC_IDLE_NO>, 348 <SYSC_IDLE_SMART>; 349 ti,syss-mask = <1>; 350 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 351 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; 352 clock-names = "fck"; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 ranges = <0x0 0x4b100000 0x1000>; 356 357 sham: sham@0 { 358 compatible = "ti,omap4-sham"; 359 reg = <0 0x300>; 360 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 361 dmas = <&sdma 119>; 362 dma-names = "rx"; 363 }; 364 }; 365 366 bandgap: bandgap@4a0021e0 { 367 reg = <0x4a0021e0 0xc 368 0x4a00232c 0xc 369 0x4a002380 0x2c 370 0x4a0023C0 0x3c>; 371 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 372 compatible = "ti,omap5430-bandgap"; 373 374 #thermal-sensor-cells = <1>; 375 }; 376 377 /* OCP2SCP3 */ 378 sata: sata@4a141100 { 379 compatible = "snps,dwc-ahci"; 380 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 381 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 382 phys = <&sata_phy>; 383 phy-names = "sata-phy"; 384 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; 385 ti,hwmods = "sata"; 386 ports-implemented = <0x1>; 387 }; 388 389 target-module@56000000 { 390 compatible = "ti,sysc-omap4", "ti,sysc"; 391 reg = <0x5600fe00 0x4>, 392 <0x5600fe10 0x4>; 393 reg-names = "rev", "sysc"; 394 ti,sysc-midle = <SYSC_IDLE_FORCE>, 395 <SYSC_IDLE_NO>, 396 <SYSC_IDLE_SMART>; 397 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 398 <SYSC_IDLE_NO>, 399 <SYSC_IDLE_SMART>; 400 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; 401 clock-names = "fck"; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 ranges = <0 0x56000000 0x2000000>; 405 406 /* 407 * Closed source PowerVR driver, no child device 408 * binding or driver in mainline 409 */ 410 }; 411 412 target-module@58000000 { 413 compatible = "ti,sysc-omap2", "ti,sysc"; 414 reg = <0x58000000 4>, 415 <0x58000014 4>; 416 reg-names = "rev", "syss"; 417 ti,syss-mask = <1>; 418 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, 419 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, 420 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, 421 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; 422 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges = <0 0x58000000 0x1000000>; 426 427 dss: dss@0 { 428 compatible = "ti,omap5-dss"; 429 reg = <0 0x80>; 430 status = "disabled"; 431 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; 432 clock-names = "fck"; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 ranges = <0 0 0x1000000>; 436 437 target-module@1000 { 438 compatible = "ti,sysc-omap2", "ti,sysc"; 439 reg = <0x1000 0x4>, 440 <0x1010 0x4>, 441 <0x1014 0x4>; 442 reg-names = "rev", "sysc", "syss"; 443 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 444 <SYSC_IDLE_NO>, 445 <SYSC_IDLE_SMART>; 446 ti,sysc-midle = <SYSC_IDLE_FORCE>, 447 <SYSC_IDLE_NO>, 448 <SYSC_IDLE_SMART>; 449 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 450 SYSC_OMAP2_ENAWAKEUP | 451 SYSC_OMAP2_SOFTRESET | 452 SYSC_OMAP2_AUTOIDLE)>; 453 ti,syss-mask = <1>; 454 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; 455 clock-names = "fck"; 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges = <0 0x1000 0x1000>; 459 460 dispc@0 { 461 compatible = "ti,omap5-dispc"; 462 reg = <0 0x1000>; 463 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; 465 clock-names = "fck"; 466 }; 467 }; 468 469 target-module@2000 { 470 compatible = "ti,sysc-omap2", "ti,sysc"; 471 reg = <0x2000 0x4>, 472 <0x2010 0x4>, 473 <0x2014 0x4>; 474 reg-names = "rev", "sysc", "syss"; 475 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 476 <SYSC_IDLE_NO>, 477 <SYSC_IDLE_SMART>; 478 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 479 SYSC_OMAP2_AUTOIDLE)>; 480 ti,syss-mask = <1>; 481 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; 482 clock-names = "fck"; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 ranges = <0 0x2000 0x1000>; 486 487 rfbi: encoder@0 { 488 compatible = "ti,omap5-rfbi"; 489 reg = <0 0x100>; 490 status = "disabled"; 491 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; 492 clock-names = "fck", "ick"; 493 }; 494 }; 495 496 target-module@4000 { 497 compatible = "ti,sysc-omap2", "ti,sysc"; 498 reg = <0x4000 0x4>, 499 <0x4010 0x4>, 500 <0x4014 0x4>; 501 reg-names = "rev", "sysc", "syss"; 502 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 503 <SYSC_IDLE_NO>, 504 <SYSC_IDLE_SMART>; 505 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 506 SYSC_OMAP2_ENAWAKEUP | 507 SYSC_OMAP2_SOFTRESET | 508 SYSC_OMAP2_AUTOIDLE)>; 509 ti,syss-mask = <1>; 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges = <0 0x4000 0x1000>; 513 514 dsi1: encoder@0 { 515 compatible = "ti,omap5-dsi"; 516 reg = <0 0x200>, 517 <0x200 0x40>, 518 <0x300 0x40>; 519 reg-names = "proto", "phy", "pll"; 520 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 521 status = "disabled"; 522 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, 523 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; 524 clock-names = "fck", "sys_clk"; 525 }; 526 }; 527 528 target-module@9000 { 529 compatible = "ti,sysc-omap2", "ti,sysc"; 530 reg = <0x9000 0x4>, 531 <0x9010 0x4>, 532 <0x9014 0x4>; 533 reg-names = "rev", "sysc", "syss"; 534 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 535 <SYSC_IDLE_NO>, 536 <SYSC_IDLE_SMART>; 537 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 538 SYSC_OMAP2_ENAWAKEUP | 539 SYSC_OMAP2_SOFTRESET | 540 SYSC_OMAP2_AUTOIDLE)>; 541 ti,syss-mask = <1>; 542 #address-cells = <1>; 543 #size-cells = <1>; 544 ranges = <0 0x9000 0x1000>; 545 546 dsi2: encoder@0 { 547 compatible = "ti,omap5-dsi"; 548 reg = <0 0x200>, 549 <0x200 0x40>, 550 <0x300 0x40>; 551 reg-names = "proto", "phy", "pll"; 552 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 553 status = "disabled"; 554 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, 555 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; 556 clock-names = "fck", "sys_clk"; 557 }; 558 }; 559 560 target-module@40000 { 561 compatible = "ti,sysc-omap4", "ti,sysc"; 562 reg = <0x40000 0x4>, 563 <0x40010 0x4>; 564 reg-names = "rev", "sysc"; 565 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 566 <SYSC_IDLE_NO>, 567 <SYSC_IDLE_SMART>, 568 <SYSC_IDLE_SMART_WKUP>; 569 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; 570 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, 571 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; 572 clock-names = "fck", "dss_clk"; 573 #address-cells = <1>; 574 #size-cells = <1>; 575 ranges = <0 0x40000 0x40000>; 576 577 hdmi: encoder@0 { 578 compatible = "ti,omap5-hdmi"; 579 reg = <0 0x200>, 580 <0x200 0x80>, 581 <0x300 0x80>, 582 <0x20000 0x19000>; 583 reg-names = "wp", "pll", "phy", "core"; 584 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 585 status = "disabled"; 586 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, 587 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; 588 clock-names = "fck", "sys_clk"; 589 dmas = <&sdma 76>; 590 dma-names = "audio_tx"; 591 }; 592 }; 593 }; 594 }; 595 596 abb_mpu: regulator-abb-mpu { 597 compatible = "ti,abb-v2"; 598 regulator-name = "abb_mpu"; 599 #address-cells = <0>; 600 #size-cells = <0>; 601 clocks = <&sys_clkin>; 602 ti,settling-time = <50>; 603 ti,clock-cycles = <16>; 604 605 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, 606 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; 607 reg-names = "base-address", "int-address", 608 "efuse-address", "ldo-address"; 609 ti,tranxdone-status-mask = <0x80>; 610 /* LDOVBBMPU_MUX_CTRL */ 611 ti,ldovbb-override-mask = <0x400>; 612 /* LDOVBBMPU_VSET_OUT */ 613 ti,ldovbb-vset-mask = <0x1F>; 614 615 /* 616 * NOTE: only FBB mode used but actual vset will 617 * determine final biasing 618 */ 619 ti,abb_info = < 620 /*uV ABB efuse rbb_m fbb_m vset_m*/ 621 1060000 0 0x0 0 0x02000000 0x01F00000 622 1250000 0 0x4 0 0x02000000 0x01F00000 623 >; 624 }; 625 626 abb_mm: regulator-abb-mm { 627 compatible = "ti,abb-v2"; 628 regulator-name = "abb_mm"; 629 #address-cells = <0>; 630 #size-cells = <0>; 631 clocks = <&sys_clkin>; 632 ti,settling-time = <50>; 633 ti,clock-cycles = <16>; 634 635 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, 636 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; 637 reg-names = "base-address", "int-address", 638 "efuse-address", "ldo-address"; 639 ti,tranxdone-status-mask = <0x80000000>; 640 /* LDOVBBMM_MUX_CTRL */ 641 ti,ldovbb-override-mask = <0x400>; 642 /* LDOVBBMM_VSET_OUT */ 643 ti,ldovbb-vset-mask = <0x1F>; 644 645 /* 646 * NOTE: only FBB mode used but actual vset will 647 * determine final biasing 648 */ 649 ti,abb_info = < 650 /*uV ABB efuse rbb_m fbb_m vset_m*/ 651 1025000 0 0x0 0 0x02000000 0x01F00000 652 1120000 0 0x4 0 0x02000000 0x01F00000 653 >; 654 }; 655 }; 656}; 657 658&cpu_thermal { 659 polling-delay = <500>; /* milliseconds */ 660 coefficients = <65 (-1791)>; 661}; 662 663#include "omap5-l4.dtsi" 664#include "omap54xx-clocks.dtsi" 665 666&gpu_thermal { 667 coefficients = <117 (-2992)>; 668}; 669 670&core_thermal { 671 coefficients = <0 2000>; 672}; 673 674#include "omap5-l4-abe.dtsi" 675#include "omap54xx-clocks.dtsi" 676 677&prm { 678 prm_dsp: prm@400 { 679 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; 680 reg = <0x400 0x100>; 681 #reset-cells = <1>; 682 }; 683 684 prm_abe: prm@500 { 685 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; 686 reg = <0x500 0x100>; 687 #power-domain-cells = <0>; 688 }; 689 690 prm_core: prm@700 { 691 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; 692 reg = <0x700 0x100>; 693 #reset-cells = <1>; 694 }; 695 696 prm_iva: prm@1200 { 697 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; 698 reg = <0x1200 0x100>; 699 #reset-cells = <1>; 700 }; 701 702 prm_device: prm@1c00 { 703 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; 704 reg = <0x1c00 0x100>; 705 #reset-cells = <1>; 706 }; 707}; 708 709/* Preferred always-on timer for clockevent */ 710&timer1_target { 711 ti,no-reset-on-init; 712 ti,no-idle; 713 timer@0 { 714 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; 715 assigned-clock-parents = <&sys_32k_ck>; 716 }; 717}; 718