1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * OMAP SRAM detection and management
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17
18 #include <asm/fncpy.h>
19 #include <asm/tlb.h>
20 #include <asm/cacheflush.h>
21
22 #include <asm/mach/map.h>
23
24 #include "soc.h"
25 #include "iomap.h"
26 #include "prm2xxx_3xxx.h"
27 #include "sdrc.h"
28 #include "sram.h"
29
30 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
31 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
32
33 #define SRAM_BOOTLOADER_SZ 0x00
34
35 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
36 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
37 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
38
39 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
40 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
41 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
42 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
43 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
44
45 #define GP_DEVICE 0x300
46
47 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
48
49 static unsigned long omap_sram_start;
50 static unsigned long omap_sram_skip;
51 static unsigned long omap_sram_size;
52
53 /*
54 * Depending on the target RAMFS firewall setup, the public usable amount of
55 * SRAM varies. The default accessible size for all device types is 2k. A GP
56 * device allows ARM11 but not other initiators for full size. This
57 * functionality seems ok until some nice security API happens.
58 */
is_sram_locked(void)59 static int is_sram_locked(void)
60 {
61 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
62 /* RAMFW: R/W access to all initiators for all qualifier sets */
63 if (cpu_is_omap242x()) {
64 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
65 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
66 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
67 }
68 if (cpu_is_omap34xx()) {
69 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
70 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
71 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
72 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
73 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
74 }
75 return 0;
76 } else
77 return 1; /* assume locked with no PPA or security driver */
78 }
79
80 /*
81 * The amount of SRAM depends on the core type.
82 * Note that we cannot try to test for SRAM here because writes
83 * to secure SRAM will hang the system. Also the SRAM is not
84 * yet mapped at this point.
85 */
omap_detect_sram(void)86 static void __init omap_detect_sram(void)
87 {
88 omap_sram_skip = SRAM_BOOTLOADER_SZ;
89 if (is_sram_locked()) {
90 if (cpu_is_omap34xx()) {
91 omap_sram_start = OMAP3_SRAM_PUB_PA;
92 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
93 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
94 omap_sram_size = 0x7000; /* 28K */
95 omap_sram_skip += SZ_16K;
96 } else {
97 omap_sram_size = 0x8000; /* 32K */
98 }
99 } else {
100 omap_sram_start = OMAP2_SRAM_PUB_PA;
101 omap_sram_size = 0x800; /* 2K */
102 }
103 } else {
104 if (cpu_is_omap34xx()) {
105 omap_sram_start = OMAP3_SRAM_PA;
106 omap_sram_size = 0x10000; /* 64K */
107 } else {
108 omap_sram_start = OMAP2_SRAM_PA;
109 if (cpu_is_omap242x())
110 omap_sram_size = 0xa0000; /* 640K */
111 else if (cpu_is_omap243x())
112 omap_sram_size = 0x10000; /* 64K */
113 }
114 }
115 }
116
117 /*
118 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
119 */
omap2_map_sram(void)120 static void __init omap2_map_sram(void)
121 {
122 int cached = 1;
123
124 if (cpu_is_omap34xx()) {
125 /*
126 * SRAM must be marked as non-cached on OMAP3 since the
127 * CORE DPLL M2 divider change code (in SRAM) runs with the
128 * SDRAM controller disabled, and if it is marked cached,
129 * the ARM may attempt to write cache lines back to SDRAM
130 * which will cause the system to hang.
131 */
132 cached = 0;
133 }
134
135 omap_map_sram(omap_sram_start, omap_sram_size,
136 omap_sram_skip, cached);
137 }
138
139 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
140 u32 base_cs, u32 force_unlock);
141
omap2_sram_ddr_init(u32 * slow_dll_ctrl,u32 fast_dll_ctrl,u32 base_cs,u32 force_unlock)142 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
143 u32 base_cs, u32 force_unlock)
144 {
145 BUG_ON(!_omap2_sram_ddr_init);
146 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
147 base_cs, force_unlock);
148 }
149
150 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
151 u32 mem_type);
152
omap2_sram_reprogram_sdrc(u32 perf_level,u32 dll_val,u32 mem_type)153 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
154 {
155 BUG_ON(!_omap2_sram_reprogram_sdrc);
156 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
157 }
158
159 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
160
omap2_set_prcm(u32 dpll_ctrl_val,u32 sdrc_rfr_val,int bypass)161 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
162 {
163 BUG_ON(!_omap2_set_prcm);
164 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
165 }
166
167 #ifdef CONFIG_SOC_OMAP2420
omap242x_sram_init(void)168 static int __init omap242x_sram_init(void)
169 {
170 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
171 omap242x_sram_ddr_init_sz);
172
173 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
174 omap242x_sram_reprogram_sdrc_sz);
175
176 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
177 omap242x_sram_set_prcm_sz);
178
179 return 0;
180 }
181 #else
omap242x_sram_init(void)182 static inline int omap242x_sram_init(void)
183 {
184 return 0;
185 }
186 #endif
187
188 #ifdef CONFIG_SOC_OMAP2430
omap243x_sram_init(void)189 static int __init omap243x_sram_init(void)
190 {
191 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
192 omap243x_sram_ddr_init_sz);
193
194 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
195 omap243x_sram_reprogram_sdrc_sz);
196
197 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
198 omap243x_sram_set_prcm_sz);
199
200 return 0;
201 }
202 #else
omap243x_sram_init(void)203 static inline int omap243x_sram_init(void)
204 {
205 return 0;
206 }
207 #endif
208
209 #ifdef CONFIG_ARCH_OMAP3
210
omap3_sram_restore_context(void)211 void omap3_sram_restore_context(void)
212 {
213 omap_sram_reset();
214
215 omap_push_sram_idle();
216 }
217
omap34xx_sram_init(void)218 static inline int omap34xx_sram_init(void)
219 {
220 omap3_sram_restore_context();
221 return 0;
222 }
223 #else
omap34xx_sram_init(void)224 static inline int omap34xx_sram_init(void)
225 {
226 return 0;
227 }
228 #endif /* CONFIG_ARCH_OMAP3 */
229
omap_sram_init(void)230 int __init omap_sram_init(void)
231 {
232 omap_detect_sram();
233 omap2_map_sram();
234
235 if (cpu_is_omap242x())
236 omap242x_sram_init();
237 else if (cpu_is_omap2430())
238 omap243x_sram_init();
239 else if (cpu_is_omap34xx())
240 omap34xx_sram_init();
241
242 return 0;
243 }
244