1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/mm/nommu.c
4 *
5 * ARM uCLinux supporting functions.
6 */
7 #include <linux/module.h>
8 #include <linux/mm.h>
9 #include <linux/pagemap.h>
10 #include <linux/io.h>
11 #include <linux/memblock.h>
12 #include <linux/kernel.h>
13
14 #include <asm/cacheflush.h>
15 #include <asm/cp15.h>
16 #include <asm/sections.h>
17 #include <asm/page.h>
18 #include <asm/setup.h>
19 #include <asm/traps.h>
20 #include <asm/mach/arch.h>
21 #include <asm/cputype.h>
22 #include <asm/mpu.h>
23 #include <asm/procinfo.h>
24
25 #include "mm.h"
26
27 unsigned long vectors_base;
28
29 /*
30 * empty_zero_page is a special page that is used for
31 * zero-initialized data and COW.
32 */
33 struct page *empty_zero_page;
34 EXPORT_SYMBOL(empty_zero_page);
35
36 #ifdef CONFIG_ARM_MPU
37 struct mpu_rgn_info mpu_rgn_info;
38 #endif
39
40 #ifdef CONFIG_CPU_CP15
41 #ifdef CONFIG_CPU_HIGH_VECTOR
setup_vectors_base(void)42 unsigned long setup_vectors_base(void)
43 {
44 unsigned long reg = get_cr();
45
46 set_cr(reg | CR_V);
47 return 0xffff0000;
48 }
49 #else /* CONFIG_CPU_HIGH_VECTOR */
50 /* Write exception base address to VBAR */
set_vbar(unsigned long val)51 static inline void set_vbar(unsigned long val)
52 {
53 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc");
54 }
55
56 /*
57 * Security extensions, bits[7:4], permitted values,
58 * 0b0000 - not implemented, 0b0001/0b0010 - implemented
59 */
security_extensions_enabled(void)60 static inline bool security_extensions_enabled(void)
61 {
62 /* Check CPUID Identification Scheme before ID_PFR1 read */
63 if ((read_cpuid_id() & 0x000f0000) == 0x000f0000)
64 return cpuid_feature_extract(CPUID_EXT_PFR1, 4) ||
65 cpuid_feature_extract(CPUID_EXT_PFR1, 20);
66 return 0;
67 }
68
setup_vectors_base(void)69 unsigned long setup_vectors_base(void)
70 {
71 unsigned long base = 0, reg = get_cr();
72
73 set_cr(reg & ~CR_V);
74 if (security_extensions_enabled()) {
75 if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM))
76 base = CONFIG_DRAM_BASE;
77 set_vbar(base);
78 } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) {
79 if (CONFIG_DRAM_BASE != 0)
80 pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n");
81 }
82
83 return base;
84 }
85 #endif /* CONFIG_CPU_HIGH_VECTOR */
86 #endif /* CONFIG_CPU_CP15 */
87
arm_mm_memblock_reserve(void)88 void __init arm_mm_memblock_reserve(void)
89 {
90 #ifndef CONFIG_CPU_V7M
91 vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0;
92 /*
93 * Register the exception vector page.
94 * some architectures which the DRAM is the exception vector to trap,
95 * alloc_page breaks with error, although it is not NULL, but "0."
96 */
97 memblock_reserve(vectors_base, 2 * PAGE_SIZE);
98 #else /* ifndef CONFIG_CPU_V7M */
99 /*
100 * There is no dedicated vector page on V7-M. So nothing needs to be
101 * reserved here.
102 */
103 #endif
104 /*
105 * In any case, always ensure address 0 is never used as many things
106 * get very confused if 0 is returned as a legitimate address.
107 */
108 memblock_reserve(0, 1);
109 }
110
adjust_lowmem_bounds_mpu(void)111 static void __init adjust_lowmem_bounds_mpu(void)
112 {
113 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
114
115 switch (pmsa) {
116 case MMFR0_PMSAv7:
117 pmsav7_adjust_lowmem_bounds();
118 break;
119 case MMFR0_PMSAv8:
120 pmsav8_adjust_lowmem_bounds();
121 break;
122 default:
123 break;
124 }
125 }
126
mpu_setup(void)127 static void __init mpu_setup(void)
128 {
129 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
130
131 switch (pmsa) {
132 case MMFR0_PMSAv7:
133 pmsav7_setup();
134 break;
135 case MMFR0_PMSAv8:
136 pmsav8_setup();
137 break;
138 default:
139 break;
140 }
141 }
142
adjust_lowmem_bounds(void)143 void __init adjust_lowmem_bounds(void)
144 {
145 phys_addr_t end;
146 adjust_lowmem_bounds_mpu();
147 end = memblock_end_of_DRAM();
148 high_memory = __va(end - 1) + 1;
149 memblock_set_current_limit(end);
150 }
151
152 /*
153 * paging_init() sets up the page tables, initialises the zone memory
154 * maps, and sets up the zero page, bad page and bad page tables.
155 */
paging_init(const struct machine_desc * mdesc)156 void __init paging_init(const struct machine_desc *mdesc)
157 {
158 void *zero_page;
159
160 early_trap_init((void *)vectors_base);
161 mpu_setup();
162
163 /* allocate the zero page. */
164 zero_page = (void *)memblock_alloc(PAGE_SIZE, PAGE_SIZE);
165 if (!zero_page)
166 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
167 __func__, PAGE_SIZE, PAGE_SIZE);
168
169 bootmem_init();
170
171 empty_zero_page = virt_to_page(zero_page);
172 flush_dcache_page(empty_zero_page);
173 }
174
175 /*
176 * We don't need to do anything here for nommu machines.
177 */
setup_mm_for_reboot(void)178 void setup_mm_for_reboot(void)
179 {
180 }
181
flush_dcache_page(struct page * page)182 void flush_dcache_page(struct page *page)
183 {
184 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
185 }
186 EXPORT_SYMBOL(flush_dcache_page);
187
flush_kernel_dcache_page(struct page * page)188 void flush_kernel_dcache_page(struct page *page)
189 {
190 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
191 }
192 EXPORT_SYMBOL(flush_kernel_dcache_page);
193
copy_to_user_page(struct vm_area_struct * vma,struct page * page,unsigned long uaddr,void * dst,const void * src,unsigned long len)194 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
195 unsigned long uaddr, void *dst, const void *src,
196 unsigned long len)
197 {
198 memcpy(dst, src, len);
199 if (vma->vm_flags & VM_EXEC)
200 __cpuc_coherent_user_range(uaddr, uaddr + len);
201 }
202
__arm_ioremap_pfn(unsigned long pfn,unsigned long offset,size_t size,unsigned int mtype)203 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
204 size_t size, unsigned int mtype)
205 {
206 if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
207 return NULL;
208 return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
209 }
210 EXPORT_SYMBOL(__arm_ioremap_pfn);
211
__arm_ioremap_caller(phys_addr_t phys_addr,size_t size,unsigned int mtype,void * caller)212 void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
213 unsigned int mtype, void *caller)
214 {
215 return (void __iomem *)phys_addr;
216 }
217
218 void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
219
ioremap(resource_size_t res_cookie,size_t size)220 void __iomem *ioremap(resource_size_t res_cookie, size_t size)
221 {
222 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
223 __builtin_return_address(0));
224 }
225 EXPORT_SYMBOL(ioremap);
226
ioremap_cache(resource_size_t res_cookie,size_t size)227 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
228 {
229 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
230 __builtin_return_address(0));
231 }
232 EXPORT_SYMBOL(ioremap_cache);
233
ioremap_wc(resource_size_t res_cookie,size_t size)234 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
235 {
236 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
237 __builtin_return_address(0));
238 }
239 EXPORT_SYMBOL(ioremap_wc);
240
241 #ifdef CONFIG_PCI
242
243 #include <asm/mach/map.h>
244
pci_remap_cfgspace(resource_size_t res_cookie,size_t size)245 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)
246 {
247 return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,
248 __builtin_return_address(0));
249 }
250 EXPORT_SYMBOL_GPL(pci_remap_cfgspace);
251 #endif
252
arch_memremap_wb(phys_addr_t phys_addr,size_t size)253 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)
254 {
255 return (void *)phys_addr;
256 }
257
__iounmap(volatile void __iomem * addr)258 void __iounmap(volatile void __iomem *addr)
259 {
260 }
261 EXPORT_SYMBOL(__iounmap);
262
263 void (*arch_iounmap)(volatile void __iomem *);
264
iounmap(volatile void __iomem * addr)265 void iounmap(volatile void __iomem *addr)
266 {
267 }
268 EXPORT_SYMBOL(iounmap);
269