1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for CZ.NIC Turris Mox Board 4 * 2019 by Marek Behun <marek.behun@nic.cz> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/bus/moxtet.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include "armada-372x.dtsi" 13 14/ { 15 model = "CZ.NIC Turris Mox Board"; 16 compatible = "cznic,turris-mox", "marvell,armada3720", 17 "marvell,armada3710"; 18 19 aliases { 20 spi0 = &spi0; 21 ethernet0 = ð0; 22 ethernet1 = ð1; 23 mmc0 = &sdhci0; 24 mmc1 = &sdhci1; 25 }; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 memory@0 { 32 device_type = "memory"; 33 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 34 }; 35 36 leds { 37 compatible = "gpio-leds"; 38 red { 39 label = "mox:red:activity"; 40 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 41 linux,default-trigger = "default-on"; 42 }; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 48 reset { 49 label = "reset"; 50 linux,code = <KEY_RESTART>; 51 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 52 debounce-interval = <60>; 53 }; 54 }; 55 56 exp_usb3_vbus: usb3-vbus { 57 compatible = "regulator-fixed"; 58 regulator-name = "usb3-vbus"; 59 regulator-min-microvolt = <5000000>; 60 regulator-max-microvolt = <5000000>; 61 enable-active-high; 62 regulator-always-on; 63 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 64 }; 65 66 vsdc_reg: vsdc-reg { 67 compatible = "regulator-gpio"; 68 regulator-name = "vsdc"; 69 regulator-min-microvolt = <1800000>; 70 regulator-max-microvolt = <3300000>; 71 regulator-boot-on; 72 73 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 74 gpios-states = <0>; 75 states = <1800000 0x1 76 3300000 0x0>; 77 enable-active-high; 78 }; 79 80 vsdio_reg: vsdio-reg { 81 compatible = "regulator-gpio"; 82 regulator-name = "vsdio"; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-boot-on; 86 87 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 88 gpios-states = <0>; 89 states = <1800000 0x1 90 3300000 0x0>; 91 enable-active-high; 92 }; 93 94 sdhci1_pwrseq: sdhci1-pwrseq { 95 compatible = "mmc-pwrseq-simple"; 96 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 97 status = "okay"; 98 }; 99 100 sfp: sfp { 101 compatible = "sff,sfp"; 102 i2c-bus = <&i2c0>; 103 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 104 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 105 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 106 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 107 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 108 109 /* enabled by U-Boot if SFP module is present */ 110 status = "disabled"; 111 }; 112 113 firmware { 114 armada-3700-rwtm { 115 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; 116 }; 117 }; 118}; 119 120&i2c0 { 121 pinctrl-names = "default"; 122 pinctrl-0 = <&i2c1_pins>; 123 clock-frequency = <100000>; 124 /delete-property/ mrvl,i2c-fast-mode; 125 status = "okay"; 126 127 /* MCP7940MT-I/MNY RTC */ 128 rtc@6f { 129 compatible = "microchip,mcp7940x"; 130 reg = <0x6f>; 131 interrupt-parent = <&gpiosb>; 132 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */ 133 }; 134}; 135 136&pcie0 { 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 139 status = "okay"; 140 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 141 /* 142 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property 143 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and 144 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it 145 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so 146 * no remapping) and that this address is the lowest from all specified ranges. If these 147 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address 148 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window 149 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. 150 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in 151 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): 152 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 153 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf 154 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 155 * Bug related to requirement of same child and parent addresses for first range is fixed 156 * in U-Boot version 2022.04 by following commit: 157 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 158 */ 159 #address-cells = <3>; 160 #size-cells = <2>; 161 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ 162 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ 163 164 /* enabled by U-Boot if PCIe module is present */ 165 status = "disabled"; 166}; 167 168&uart0 { 169 status = "okay"; 170}; 171 172ð0 { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&rgmii_pins>; 175 phy-mode = "rgmii-id"; 176 phy-handle = <&phy1>; 177 status = "okay"; 178}; 179 180ð1 { 181 phy-mode = "2500base-x"; 182 managed = "in-band-status"; 183 phys = <&comphy0 1>; 184}; 185 186&sdhci0 { 187 wp-inverted; 188 bus-width = <4>; 189 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 190 vqmmc-supply = <&vsdc_reg>; 191 marvell,pad-type = "sd"; 192 status = "okay"; 193}; 194 195&sdhci1 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&sdio_pins>; 198 non-removable; 199 bus-width = <4>; 200 marvell,pad-type = "sd"; 201 vqmmc-supply = <&vsdio_reg>; 202 mmc-pwrseq = <&sdhci1_pwrseq>; 203 /* forbid SDR104 for FCC purposes */ 204 sdhci-caps-mask = <0x2 0x0>; 205 status = "okay"; 206}; 207 208&spi0 { 209 status = "okay"; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 212 assigned-clocks = <&nb_periph_clk 7>; 213 assigned-clock-parents = <&tbg 1>; 214 assigned-clock-rates = <20000000>; 215 216 spi-flash@0 { 217 #address-cells = <1>; 218 #size-cells = <1>; 219 compatible = "jedec,spi-nor"; 220 reg = <0>; 221 spi-max-frequency = <20000000>; 222 223 partitions { 224 compatible = "fixed-partitions"; 225 #address-cells = <1>; 226 #size-cells = <1>; 227 228 partition@0 { 229 label = "secure-firmware"; 230 reg = <0x0 0x20000>; 231 }; 232 233 partition@20000 { 234 label = "a53-firmware"; 235 reg = <0x20000 0x160000>; 236 }; 237 238 partition@180000 { 239 label = "u-boot-env"; 240 reg = <0x180000 0x10000>; 241 }; 242 243 partition@190000 { 244 label = "Rescue system"; 245 reg = <0x190000 0x660000>; 246 }; 247 248 partition@7f0000 { 249 label = "dtb"; 250 reg = <0x7f0000 0x10000>; 251 }; 252 }; 253 }; 254 255 moxtet: moxtet@1 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "cznic,moxtet"; 259 reg = <1>; 260 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 261 spi-max-frequency = <10000000>; 262 spi-cpol; 263 spi-cpha; 264 interrupt-controller; 265 #interrupt-cells = <1>; 266 interrupt-parent = <&gpiosb>; 267 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 268 status = "okay"; 269 270 moxtet_sfp: gpio@0 { 271 compatible = "cznic,moxtet-gpio"; 272 gpio-controller; 273 #gpio-cells = <2>; 274 reg = <0>; 275 status = "disabled"; 276 }; 277 }; 278}; 279 280&usb2 { 281 status = "okay"; 282}; 283 284&comphy2 { 285 connector { 286 compatible = "usb-a-connector"; 287 phy-supply = <&exp_usb3_vbus>; 288 }; 289}; 290 291&usb3 { 292 status = "okay"; 293 phys = <&comphy2 0>; 294}; 295 296&mdio { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&smi_pins>; 299 status = "okay"; 300 301 phy1: ethernet-phy@1 { 302 reg = <1>; 303 }; 304 305 /* switch nodes are enabled by U-Boot if modules are present */ 306 switch0@10 { 307 compatible = "marvell,mv88e6190"; 308 reg = <0x10 0>; 309 dsa,member = <0 0>; 310 interrupt-parent = <&moxtet>; 311 interrupts = <MOXTET_IRQ_PERIDOT(0)>; 312 status = "disabled"; 313 314 mdio { 315 #address-cells = <1>; 316 #size-cells = <0>; 317 318 switch0phy1: switch0phy1@1 { 319 reg = <0x1>; 320 }; 321 322 switch0phy2: switch0phy2@2 { 323 reg = <0x2>; 324 }; 325 326 switch0phy3: switch0phy3@3 { 327 reg = <0x3>; 328 }; 329 330 switch0phy4: switch0phy4@4 { 331 reg = <0x4>; 332 }; 333 334 switch0phy5: switch0phy5@5 { 335 reg = <0x5>; 336 }; 337 338 switch0phy6: switch0phy6@6 { 339 reg = <0x6>; 340 }; 341 342 switch0phy7: switch0phy7@7 { 343 reg = <0x7>; 344 }; 345 346 switch0phy8: switch0phy8@8 { 347 reg = <0x8>; 348 }; 349 }; 350 351 ports { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 355 port@1 { 356 reg = <0x1>; 357 label = "lan1"; 358 phy-handle = <&switch0phy1>; 359 }; 360 361 port@2 { 362 reg = <0x2>; 363 label = "lan2"; 364 phy-handle = <&switch0phy2>; 365 }; 366 367 port@3 { 368 reg = <0x3>; 369 label = "lan3"; 370 phy-handle = <&switch0phy3>; 371 }; 372 373 port@4 { 374 reg = <0x4>; 375 label = "lan4"; 376 phy-handle = <&switch0phy4>; 377 }; 378 379 port@5 { 380 reg = <0x5>; 381 label = "lan5"; 382 phy-handle = <&switch0phy5>; 383 }; 384 385 port@6 { 386 reg = <0x6>; 387 label = "lan6"; 388 phy-handle = <&switch0phy6>; 389 }; 390 391 port@7 { 392 reg = <0x7>; 393 label = "lan7"; 394 phy-handle = <&switch0phy7>; 395 }; 396 397 port@8 { 398 reg = <0x8>; 399 label = "lan8"; 400 phy-handle = <&switch0phy8>; 401 }; 402 403 port@9 { 404 reg = <0x9>; 405 label = "cpu"; 406 ethernet = <ð1>; 407 phy-mode = "2500base-x"; 408 managed = "in-band-status"; 409 }; 410 411 switch0port10: port@a { 412 reg = <0xa>; 413 label = "dsa"; 414 phy-mode = "2500base-x"; 415 managed = "in-band-status"; 416 link = <&switch1port9 &switch2port9>; 417 status = "disabled"; 418 }; 419 420 port-sfp@a { 421 reg = <0xa>; 422 label = "sfp"; 423 sfp = <&sfp>; 424 phy-mode = "sgmii"; 425 managed = "in-band-status"; 426 status = "disabled"; 427 }; 428 }; 429 }; 430 431 switch0@2 { 432 compatible = "marvell,mv88e6085"; 433 reg = <0x2 0>; 434 dsa,member = <0 0>; 435 interrupt-parent = <&moxtet>; 436 interrupts = <MOXTET_IRQ_TOPAZ>; 437 status = "disabled"; 438 439 mdio { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 443 switch0phy1_topaz: switch0phy1@11 { 444 reg = <0x11>; 445 }; 446 447 switch0phy2_topaz: switch0phy2@12 { 448 reg = <0x12>; 449 }; 450 451 switch0phy3_topaz: switch0phy3@13 { 452 reg = <0x13>; 453 }; 454 455 switch0phy4_topaz: switch0phy4@14 { 456 reg = <0x14>; 457 }; 458 }; 459 460 ports { 461 #address-cells = <1>; 462 #size-cells = <0>; 463 464 port@1 { 465 reg = <0x1>; 466 label = "lan1"; 467 phy-handle = <&switch0phy1_topaz>; 468 }; 469 470 port@2 { 471 reg = <0x2>; 472 label = "lan2"; 473 phy-handle = <&switch0phy2_topaz>; 474 }; 475 476 port@3 { 477 reg = <0x3>; 478 label = "lan3"; 479 phy-handle = <&switch0phy3_topaz>; 480 }; 481 482 port@4 { 483 reg = <0x4>; 484 label = "lan4"; 485 phy-handle = <&switch0phy4_topaz>; 486 }; 487 488 port@5 { 489 reg = <0x5>; 490 label = "cpu"; 491 phy-mode = "2500base-x"; 492 managed = "in-band-status"; 493 ethernet = <ð1>; 494 }; 495 }; 496 }; 497 498 switch1@11 { 499 compatible = "marvell,mv88e6190"; 500 reg = <0x11 0>; 501 dsa,member = <0 1>; 502 interrupt-parent = <&moxtet>; 503 interrupts = <MOXTET_IRQ_PERIDOT(1)>; 504 status = "disabled"; 505 506 mdio { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 510 switch1phy1: switch1phy1@1 { 511 reg = <0x1>; 512 }; 513 514 switch1phy2: switch1phy2@2 { 515 reg = <0x2>; 516 }; 517 518 switch1phy3: switch1phy3@3 { 519 reg = <0x3>; 520 }; 521 522 switch1phy4: switch1phy4@4 { 523 reg = <0x4>; 524 }; 525 526 switch1phy5: switch1phy5@5 { 527 reg = <0x5>; 528 }; 529 530 switch1phy6: switch1phy6@6 { 531 reg = <0x6>; 532 }; 533 534 switch1phy7: switch1phy7@7 { 535 reg = <0x7>; 536 }; 537 538 switch1phy8: switch1phy8@8 { 539 reg = <0x8>; 540 }; 541 }; 542 543 ports { 544 #address-cells = <1>; 545 #size-cells = <0>; 546 547 port@1 { 548 reg = <0x1>; 549 label = "lan9"; 550 phy-handle = <&switch1phy1>; 551 }; 552 553 port@2 { 554 reg = <0x2>; 555 label = "lan10"; 556 phy-handle = <&switch1phy2>; 557 }; 558 559 port@3 { 560 reg = <0x3>; 561 label = "lan11"; 562 phy-handle = <&switch1phy3>; 563 }; 564 565 port@4 { 566 reg = <0x4>; 567 label = "lan12"; 568 phy-handle = <&switch1phy4>; 569 }; 570 571 port@5 { 572 reg = <0x5>; 573 label = "lan13"; 574 phy-handle = <&switch1phy5>; 575 }; 576 577 port@6 { 578 reg = <0x6>; 579 label = "lan14"; 580 phy-handle = <&switch1phy6>; 581 }; 582 583 port@7 { 584 reg = <0x7>; 585 label = "lan15"; 586 phy-handle = <&switch1phy7>; 587 }; 588 589 port@8 { 590 reg = <0x8>; 591 label = "lan16"; 592 phy-handle = <&switch1phy8>; 593 }; 594 595 switch1port9: port@9 { 596 reg = <0x9>; 597 label = "dsa"; 598 phy-mode = "2500base-x"; 599 managed = "in-band-status"; 600 link = <&switch0port10>; 601 }; 602 603 switch1port10: port@a { 604 reg = <0xa>; 605 label = "dsa"; 606 phy-mode = "2500base-x"; 607 managed = "in-band-status"; 608 link = <&switch2port9>; 609 status = "disabled"; 610 }; 611 612 port-sfp@a { 613 reg = <0xa>; 614 label = "sfp"; 615 sfp = <&sfp>; 616 phy-mode = "sgmii"; 617 managed = "in-band-status"; 618 status = "disabled"; 619 }; 620 }; 621 }; 622 623 switch1@2 { 624 compatible = "marvell,mv88e6085"; 625 reg = <0x2 0>; 626 dsa,member = <0 1>; 627 interrupt-parent = <&moxtet>; 628 interrupts = <MOXTET_IRQ_TOPAZ>; 629 status = "disabled"; 630 631 mdio { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 635 switch1phy1_topaz: switch1phy1@11 { 636 reg = <0x11>; 637 }; 638 639 switch1phy2_topaz: switch1phy2@12 { 640 reg = <0x12>; 641 }; 642 643 switch1phy3_topaz: switch1phy3@13 { 644 reg = <0x13>; 645 }; 646 647 switch1phy4_topaz: switch1phy4@14 { 648 reg = <0x14>; 649 }; 650 }; 651 652 ports { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 656 port@1 { 657 reg = <0x1>; 658 label = "lan9"; 659 phy-handle = <&switch1phy1_topaz>; 660 }; 661 662 port@2 { 663 reg = <0x2>; 664 label = "lan10"; 665 phy-handle = <&switch1phy2_topaz>; 666 }; 667 668 port@3 { 669 reg = <0x3>; 670 label = "lan11"; 671 phy-handle = <&switch1phy3_topaz>; 672 }; 673 674 port@4 { 675 reg = <0x4>; 676 label = "lan12"; 677 phy-handle = <&switch1phy4_topaz>; 678 }; 679 680 port@5 { 681 reg = <0x5>; 682 label = "dsa"; 683 phy-mode = "2500base-x"; 684 managed = "in-band-status"; 685 link = <&switch0port10>; 686 }; 687 }; 688 }; 689 690 switch2@12 { 691 compatible = "marvell,mv88e6190"; 692 reg = <0x12 0>; 693 dsa,member = <0 2>; 694 interrupt-parent = <&moxtet>; 695 interrupts = <MOXTET_IRQ_PERIDOT(2)>; 696 status = "disabled"; 697 698 mdio { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 702 switch2phy1: switch2phy1@1 { 703 reg = <0x1>; 704 }; 705 706 switch2phy2: switch2phy2@2 { 707 reg = <0x2>; 708 }; 709 710 switch2phy3: switch2phy3@3 { 711 reg = <0x3>; 712 }; 713 714 switch2phy4: switch2phy4@4 { 715 reg = <0x4>; 716 }; 717 718 switch2phy5: switch2phy5@5 { 719 reg = <0x5>; 720 }; 721 722 switch2phy6: switch2phy6@6 { 723 reg = <0x6>; 724 }; 725 726 switch2phy7: switch2phy7@7 { 727 reg = <0x7>; 728 }; 729 730 switch2phy8: switch2phy8@8 { 731 reg = <0x8>; 732 }; 733 }; 734 735 ports { 736 #address-cells = <1>; 737 #size-cells = <0>; 738 739 port@1 { 740 reg = <0x1>; 741 label = "lan17"; 742 phy-handle = <&switch2phy1>; 743 }; 744 745 port@2 { 746 reg = <0x2>; 747 label = "lan18"; 748 phy-handle = <&switch2phy2>; 749 }; 750 751 port@3 { 752 reg = <0x3>; 753 label = "lan19"; 754 phy-handle = <&switch2phy3>; 755 }; 756 757 port@4 { 758 reg = <0x4>; 759 label = "lan20"; 760 phy-handle = <&switch2phy4>; 761 }; 762 763 port@5 { 764 reg = <0x5>; 765 label = "lan21"; 766 phy-handle = <&switch2phy5>; 767 }; 768 769 port@6 { 770 reg = <0x6>; 771 label = "lan22"; 772 phy-handle = <&switch2phy6>; 773 }; 774 775 port@7 { 776 reg = <0x7>; 777 label = "lan23"; 778 phy-handle = <&switch2phy7>; 779 }; 780 781 port@8 { 782 reg = <0x8>; 783 label = "lan24"; 784 phy-handle = <&switch2phy8>; 785 }; 786 787 switch2port9: port@9 { 788 reg = <0x9>; 789 label = "dsa"; 790 phy-mode = "2500base-x"; 791 managed = "in-band-status"; 792 link = <&switch1port10 &switch0port10>; 793 }; 794 795 port-sfp@a { 796 reg = <0xa>; 797 label = "sfp"; 798 sfp = <&sfp>; 799 phy-mode = "sgmii"; 800 managed = "in-band-status"; 801 status = "disabled"; 802 }; 803 }; 804 }; 805 806 switch2@2 { 807 compatible = "marvell,mv88e6085"; 808 reg = <0x2 0>; 809 dsa,member = <0 2>; 810 interrupt-parent = <&moxtet>; 811 interrupts = <MOXTET_IRQ_TOPAZ>; 812 status = "disabled"; 813 814 mdio { 815 #address-cells = <1>; 816 #size-cells = <0>; 817 818 switch2phy1_topaz: switch2phy1@11 { 819 reg = <0x11>; 820 }; 821 822 switch2phy2_topaz: switch2phy2@12 { 823 reg = <0x12>; 824 }; 825 826 switch2phy3_topaz: switch2phy3@13 { 827 reg = <0x13>; 828 }; 829 830 switch2phy4_topaz: switch2phy4@14 { 831 reg = <0x14>; 832 }; 833 }; 834 835 ports { 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 port@1 { 840 reg = <0x1>; 841 label = "lan17"; 842 phy-handle = <&switch2phy1_topaz>; 843 }; 844 845 port@2 { 846 reg = <0x2>; 847 label = "lan18"; 848 phy-handle = <&switch2phy2_topaz>; 849 }; 850 851 port@3 { 852 reg = <0x3>; 853 label = "lan19"; 854 phy-handle = <&switch2phy3_topaz>; 855 }; 856 857 port@4 { 858 reg = <0x4>; 859 label = "lan20"; 860 phy-handle = <&switch2phy4_topaz>; 861 }; 862 863 port@5 { 864 reg = <0x5>; 865 label = "dsa"; 866 phy-mode = "2500base-x"; 867 managed = "in-band-status"; 868 link = <&switch1port10 &switch0port10>; 869 }; 870 }; 871 }; 872}; 873