1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include <dt-bindings/phy/phy.h> 13#include "mt8183-pinfunc.h" 14 15/ { 16 compatible = "mediatek,mt8183"; 17 interrupt-parent = <&sysirq>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 i2c6 = &i2c6; 29 i2c7 = &i2c7; 30 i2c8 = &i2c8; 31 i2c9 = &i2c9; 32 i2c10 = &i2c10; 33 i2c11 = &i2c11; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu-map { 41 cluster0 { 42 core0 { 43 cpu = <&cpu0>; 44 }; 45 core1 { 46 cpu = <&cpu1>; 47 }; 48 core2 { 49 cpu = <&cpu2>; 50 }; 51 core3 { 52 cpu = <&cpu3>; 53 }; 54 }; 55 56 cluster1 { 57 core0 { 58 cpu = <&cpu4>; 59 }; 60 core1 { 61 cpu = <&cpu5>; 62 }; 63 core2 { 64 cpu = <&cpu6>; 65 }; 66 core3 { 67 cpu = <&cpu7>; 68 }; 69 }; 70 }; 71 72 cpu0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x000>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <741>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 79 dynamic-power-coefficient = <84>; 80 #cooling-cells = <2>; 81 }; 82 83 cpu1: cpu@1 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53"; 86 reg = <0x001>; 87 enable-method = "psci"; 88 capacity-dmips-mhz = <741>; 89 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 90 dynamic-power-coefficient = <84>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x002>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <741>; 100 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 101 dynamic-power-coefficient = <84>; 102 #cooling-cells = <2>; 103 }; 104 105 cpu3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x003>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <741>; 111 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 112 dynamic-power-coefficient = <84>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu4: cpu@100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a73"; 119 reg = <0x100>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 123 dynamic-power-coefficient = <211>; 124 #cooling-cells = <2>; 125 }; 126 127 cpu5: cpu@101 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a73"; 130 reg = <0x101>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <1024>; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 134 dynamic-power-coefficient = <211>; 135 #cooling-cells = <2>; 136 }; 137 138 cpu6: cpu@102 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a73"; 141 reg = <0x102>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 145 dynamic-power-coefficient = <211>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu7: cpu@103 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a73"; 152 reg = <0x103>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 156 dynamic-power-coefficient = <211>; 157 #cooling-cells = <2>; 158 }; 159 160 idle-states { 161 entry-method = "psci"; 162 163 CPU_SLEEP: cpu-sleep { 164 compatible = "arm,idle-state"; 165 local-timer-stop; 166 arm,psci-suspend-param = <0x00010001>; 167 entry-latency-us = <200>; 168 exit-latency-us = <200>; 169 min-residency-us = <800>; 170 }; 171 172 CLUSTER_SLEEP0: cluster-sleep-0 { 173 compatible = "arm,idle-state"; 174 local-timer-stop; 175 arm,psci-suspend-param = <0x01010001>; 176 entry-latency-us = <250>; 177 exit-latency-us = <400>; 178 min-residency-us = <1000>; 179 }; 180 CLUSTER_SLEEP1: cluster-sleep-1 { 181 compatible = "arm,idle-state"; 182 local-timer-stop; 183 arm,psci-suspend-param = <0x01010001>; 184 entry-latency-us = <250>; 185 exit-latency-us = <400>; 186 min-residency-us = <1300>; 187 }; 188 }; 189 }; 190 191 pmu-a53 { 192 compatible = "arm,cortex-a53-pmu"; 193 interrupt-parent = <&gic>; 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 195 }; 196 197 pmu-a73 { 198 compatible = "arm,cortex-a73-pmu"; 199 interrupt-parent = <&gic>; 200 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 201 }; 202 203 psci { 204 compatible = "arm,psci-1.0"; 205 method = "smc"; 206 }; 207 208 clk13m: fixed-factor-clock-13m { 209 compatible = "fixed-factor-clock"; 210 #clock-cells = <0>; 211 clocks = <&clk26m>; 212 clock-div = <2>; 213 clock-mult = <1>; 214 clock-output-names = "clk13m"; 215 }; 216 217 clk26m: oscillator { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <26000000>; 221 clock-output-names = "clk26m"; 222 }; 223 224 timer { 225 compatible = "arm,armv8-timer"; 226 interrupt-parent = <&gic>; 227 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 228 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 229 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 230 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 231 }; 232 233 soc { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 compatible = "simple-bus"; 237 ranges; 238 239 soc_data: soc_data@8000000 { 240 compatible = "mediatek,mt8183-efuse", 241 "mediatek,efuse"; 242 reg = <0 0x08000000 0 0x0010>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 status = "disabled"; 246 }; 247 248 gic: interrupt-controller@c000000 { 249 compatible = "arm,gic-v3"; 250 #interrupt-cells = <4>; 251 interrupt-parent = <&gic>; 252 interrupt-controller; 253 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 254 <0 0x0c100000 0 0x200000>, /* GICR */ 255 <0 0x0c400000 0 0x2000>, /* GICC */ 256 <0 0x0c410000 0 0x1000>, /* GICH */ 257 <0 0x0c420000 0 0x2000>; /* GICV */ 258 259 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 260 ppi-partitions { 261 ppi_cluster0: interrupt-partition-0 { 262 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 263 }; 264 ppi_cluster1: interrupt-partition-1 { 265 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 266 }; 267 }; 268 }; 269 270 mcucfg: syscon@c530000 { 271 compatible = "mediatek,mt8183-mcucfg", "syscon"; 272 reg = <0 0x0c530000 0 0x1000>; 273 #clock-cells = <1>; 274 }; 275 276 sysirq: interrupt-controller@c530a80 { 277 compatible = "mediatek,mt8183-sysirq", 278 "mediatek,mt6577-sysirq"; 279 interrupt-controller; 280 #interrupt-cells = <3>; 281 interrupt-parent = <&gic>; 282 reg = <0 0x0c530a80 0 0x50>; 283 }; 284 285 topckgen: syscon@10000000 { 286 compatible = "mediatek,mt8183-topckgen", "syscon"; 287 reg = <0 0x10000000 0 0x1000>; 288 #clock-cells = <1>; 289 }; 290 291 infracfg: syscon@10001000 { 292 compatible = "mediatek,mt8183-infracfg", "syscon"; 293 reg = <0 0x10001000 0 0x1000>; 294 #clock-cells = <1>; 295 #reset-cells = <1>; 296 }; 297 298 pericfg: syscon@10003000 { 299 compatible = "mediatek,mt8183-pericfg", "syscon"; 300 reg = <0 0x10003000 0 0x1000>; 301 #clock-cells = <1>; 302 }; 303 304 pio: pinctrl@10005000 { 305 compatible = "mediatek,mt8183-pinctrl"; 306 reg = <0 0x10005000 0 0x1000>, 307 <0 0x11f20000 0 0x1000>, 308 <0 0x11e80000 0 0x1000>, 309 <0 0x11e70000 0 0x1000>, 310 <0 0x11e90000 0 0x1000>, 311 <0 0x11d30000 0 0x1000>, 312 <0 0x11d20000 0 0x1000>, 313 <0 0x11c50000 0 0x1000>, 314 <0 0x11f30000 0 0x1000>, 315 <0 0x1000b000 0 0x1000>; 316 reg-names = "iocfg0", "iocfg1", "iocfg2", 317 "iocfg3", "iocfg4", "iocfg5", 318 "iocfg6", "iocfg7", "iocfg8", 319 "eint"; 320 gpio-controller; 321 #gpio-cells = <2>; 322 gpio-ranges = <&pio 0 0 192>; 323 interrupt-controller; 324 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 325 #interrupt-cells = <2>; 326 }; 327 328 watchdog: watchdog@10007000 { 329 compatible = "mediatek,mt8183-wdt"; 330 reg = <0 0x10007000 0 0x100>; 331 #reset-cells = <1>; 332 }; 333 334 apmixedsys: syscon@1000c000 { 335 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 336 reg = <0 0x1000c000 0 0x1000>; 337 #clock-cells = <1>; 338 }; 339 340 pwrap: pwrap@1000d000 { 341 compatible = "mediatek,mt8183-pwrap"; 342 reg = <0 0x1000d000 0 0x1000>; 343 reg-names = "pwrap"; 344 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 346 <&infracfg CLK_INFRA_PMIC_AP>; 347 clock-names = "spi", "wrap"; 348 }; 349 350 scp: scp@10500000 { 351 compatible = "mediatek,mt8183-scp"; 352 reg = <0 0x10500000 0 0x80000>, 353 <0 0x105c0000 0 0x19080>; 354 reg-names = "sram", "cfg"; 355 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&infracfg CLK_INFRA_SCPSYS>; 357 clock-names = "main"; 358 memory-region = <&scp_mem_reserved>; 359 status = "disabled"; 360 }; 361 362 systimer: timer@10017000 { 363 compatible = "mediatek,mt8183-timer", 364 "mediatek,mt6765-timer"; 365 reg = <0 0x10017000 0 0x1000>; 366 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&clk13m>; 368 }; 369 370 gce: mailbox@10238000 { 371 compatible = "mediatek,mt8183-gce"; 372 reg = <0 0x10238000 0 0x4000>; 373 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 374 #mbox-cells = <2>; 375 clocks = <&infracfg CLK_INFRA_GCE>; 376 clock-names = "gce"; 377 }; 378 379 auxadc: auxadc@11001000 { 380 compatible = "mediatek,mt8183-auxadc", 381 "mediatek,mt8173-auxadc"; 382 reg = <0 0x11001000 0 0x1000>; 383 clocks = <&infracfg CLK_INFRA_AUXADC>; 384 clock-names = "main"; 385 #io-channel-cells = <1>; 386 status = "disabled"; 387 }; 388 389 uart0: serial@11002000 { 390 compatible = "mediatek,mt8183-uart", 391 "mediatek,mt6577-uart"; 392 reg = <0 0x11002000 0 0x1000>; 393 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 394 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 395 clock-names = "baud", "bus"; 396 status = "disabled"; 397 }; 398 399 uart1: serial@11003000 { 400 compatible = "mediatek,mt8183-uart", 401 "mediatek,mt6577-uart"; 402 reg = <0 0x11003000 0 0x1000>; 403 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 404 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 405 clock-names = "baud", "bus"; 406 status = "disabled"; 407 }; 408 409 uart2: serial@11004000 { 410 compatible = "mediatek,mt8183-uart", 411 "mediatek,mt6577-uart"; 412 reg = <0 0x11004000 0 0x1000>; 413 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 414 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 415 clock-names = "baud", "bus"; 416 status = "disabled"; 417 }; 418 419 i2c6: i2c@11005000 { 420 compatible = "mediatek,mt8183-i2c"; 421 reg = <0 0x11005000 0 0x1000>, 422 <0 0x11000600 0 0x80>; 423 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 424 clocks = <&infracfg CLK_INFRA_I2C6>, 425 <&infracfg CLK_INFRA_AP_DMA>; 426 clock-names = "main", "dma"; 427 clock-div = <1>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 status = "disabled"; 431 }; 432 433 i2c0: i2c@11007000 { 434 compatible = "mediatek,mt8183-i2c"; 435 reg = <0 0x11007000 0 0x1000>, 436 <0 0x11000080 0 0x80>; 437 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 438 clocks = <&infracfg CLK_INFRA_I2C0>, 439 <&infracfg CLK_INFRA_AP_DMA>; 440 clock-names = "main", "dma"; 441 clock-div = <1>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 i2c4: i2c@11008000 { 448 compatible = "mediatek,mt8183-i2c"; 449 reg = <0 0x11008000 0 0x1000>, 450 <0 0x11000100 0 0x80>; 451 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 452 clocks = <&infracfg CLK_INFRA_I2C1>, 453 <&infracfg CLK_INFRA_AP_DMA>, 454 <&infracfg CLK_INFRA_I2C1_ARBITER>; 455 clock-names = "main", "dma","arb"; 456 clock-div = <1>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 status = "disabled"; 460 }; 461 462 i2c2: i2c@11009000 { 463 compatible = "mediatek,mt8183-i2c"; 464 reg = <0 0x11009000 0 0x1000>, 465 <0 0x11000280 0 0x80>; 466 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 467 clocks = <&infracfg CLK_INFRA_I2C2>, 468 <&infracfg CLK_INFRA_AP_DMA>, 469 <&infracfg CLK_INFRA_I2C2_ARBITER>; 470 clock-names = "main", "dma", "arb"; 471 clock-div = <1>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 477 spi0: spi@1100a000 { 478 compatible = "mediatek,mt8183-spi"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 reg = <0 0x1100a000 0 0x1000>; 482 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 483 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 484 <&topckgen CLK_TOP_MUX_SPI>, 485 <&infracfg CLK_INFRA_SPI0>; 486 clock-names = "parent-clk", "sel-clk", "spi-clk"; 487 status = "disabled"; 488 }; 489 490 i2c3: i2c@1100f000 { 491 compatible = "mediatek,mt8183-i2c"; 492 reg = <0 0x1100f000 0 0x1000>, 493 <0 0x11000400 0 0x80>; 494 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 495 clocks = <&infracfg CLK_INFRA_I2C3>, 496 <&infracfg CLK_INFRA_AP_DMA>; 497 clock-names = "main", "dma"; 498 clock-div = <1>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 status = "disabled"; 502 }; 503 504 spi1: spi@11010000 { 505 compatible = "mediatek,mt8183-spi"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <0 0x11010000 0 0x1000>; 509 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 510 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 511 <&topckgen CLK_TOP_MUX_SPI>, 512 <&infracfg CLK_INFRA_SPI1>; 513 clock-names = "parent-clk", "sel-clk", "spi-clk"; 514 status = "disabled"; 515 }; 516 517 i2c1: i2c@11011000 { 518 compatible = "mediatek,mt8183-i2c"; 519 reg = <0 0x11011000 0 0x1000>, 520 <0 0x11000480 0 0x80>; 521 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 522 clocks = <&infracfg CLK_INFRA_I2C4>, 523 <&infracfg CLK_INFRA_AP_DMA>; 524 clock-names = "main", "dma"; 525 clock-div = <1>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 status = "disabled"; 529 }; 530 531 spi2: spi@11012000 { 532 compatible = "mediatek,mt8183-spi"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 reg = <0 0x11012000 0 0x1000>; 536 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 537 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 538 <&topckgen CLK_TOP_MUX_SPI>, 539 <&infracfg CLK_INFRA_SPI2>; 540 clock-names = "parent-clk", "sel-clk", "spi-clk"; 541 status = "disabled"; 542 }; 543 544 spi3: spi@11013000 { 545 compatible = "mediatek,mt8183-spi"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 reg = <0 0x11013000 0 0x1000>; 549 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 550 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 551 <&topckgen CLK_TOP_MUX_SPI>, 552 <&infracfg CLK_INFRA_SPI3>; 553 clock-names = "parent-clk", "sel-clk", "spi-clk"; 554 status = "disabled"; 555 }; 556 557 i2c9: i2c@11014000 { 558 compatible = "mediatek,mt8183-i2c"; 559 reg = <0 0x11014000 0 0x1000>, 560 <0 0x11000180 0 0x80>; 561 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 562 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 563 <&infracfg CLK_INFRA_AP_DMA>, 564 <&infracfg CLK_INFRA_I2C1_ARBITER>; 565 clock-names = "main", "dma", "arb"; 566 clock-div = <1>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 i2c10: i2c@11015000 { 573 compatible = "mediatek,mt8183-i2c"; 574 reg = <0 0x11015000 0 0x1000>, 575 <0 0x11000300 0 0x80>; 576 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 577 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 578 <&infracfg CLK_INFRA_AP_DMA>, 579 <&infracfg CLK_INFRA_I2C2_ARBITER>; 580 clock-names = "main", "dma", "arb"; 581 clock-div = <1>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 i2c5: i2c@11016000 { 588 compatible = "mediatek,mt8183-i2c"; 589 reg = <0 0x11016000 0 0x1000>, 590 <0 0x11000500 0 0x80>; 591 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 592 clocks = <&infracfg CLK_INFRA_I2C5>, 593 <&infracfg CLK_INFRA_AP_DMA>, 594 <&infracfg CLK_INFRA_I2C5_ARBITER>; 595 clock-names = "main", "dma", "arb"; 596 clock-div = <1>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 i2c11: i2c@11017000 { 603 compatible = "mediatek,mt8183-i2c"; 604 reg = <0 0x11017000 0 0x1000>, 605 <0 0x11000580 0 0x80>; 606 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 607 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 608 <&infracfg CLK_INFRA_AP_DMA>, 609 <&infracfg CLK_INFRA_I2C5_ARBITER>; 610 clock-names = "main", "dma", "arb"; 611 clock-div = <1>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 spi4: spi@11018000 { 618 compatible = "mediatek,mt8183-spi"; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 reg = <0 0x11018000 0 0x1000>; 622 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 623 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 624 <&topckgen CLK_TOP_MUX_SPI>, 625 <&infracfg CLK_INFRA_SPI4>; 626 clock-names = "parent-clk", "sel-clk", "spi-clk"; 627 status = "disabled"; 628 }; 629 630 spi5: spi@11019000 { 631 compatible = "mediatek,mt8183-spi"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 reg = <0 0x11019000 0 0x1000>; 635 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 636 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 637 <&topckgen CLK_TOP_MUX_SPI>, 638 <&infracfg CLK_INFRA_SPI5>; 639 clock-names = "parent-clk", "sel-clk", "spi-clk"; 640 status = "disabled"; 641 }; 642 643 i2c7: i2c@1101a000 { 644 compatible = "mediatek,mt8183-i2c"; 645 reg = <0 0x1101a000 0 0x1000>, 646 <0 0x11000680 0 0x80>; 647 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 648 clocks = <&infracfg CLK_INFRA_I2C7>, 649 <&infracfg CLK_INFRA_AP_DMA>; 650 clock-names = "main", "dma"; 651 clock-div = <1>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 status = "disabled"; 655 }; 656 657 i2c8: i2c@1101b000 { 658 compatible = "mediatek,mt8183-i2c"; 659 reg = <0 0x1101b000 0 0x1000>, 660 <0 0x11000700 0 0x80>; 661 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 662 clocks = <&infracfg CLK_INFRA_I2C8>, 663 <&infracfg CLK_INFRA_AP_DMA>; 664 clock-names = "main", "dma"; 665 clock-div = <1>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 status = "disabled"; 669 }; 670 671 ssusb: usb@11201000 { 672 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 673 reg = <0 0x11201000 0 0x2e00>, 674 <0 0x11203e00 0 0x0100>; 675 reg-names = "mac", "ippc"; 676 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 677 phys = <&u2port0 PHY_TYPE_USB2>, 678 <&u3port0 PHY_TYPE_USB3>; 679 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 680 <&infracfg CLK_INFRA_USB>; 681 clock-names = "sys_ck", "ref_ck"; 682 mediatek,syscon-wakeup = <&pericfg 0x400 0>; 683 #address-cells = <2>; 684 #size-cells = <2>; 685 ranges; 686 status = "disabled"; 687 688 usb_host: xhci@11200000 { 689 compatible = "mediatek,mt8183-xhci", 690 "mediatek,mtk-xhci"; 691 reg = <0 0x11200000 0 0x1000>; 692 reg-names = "mac"; 693 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 694 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 695 <&infracfg CLK_INFRA_USB>; 696 clock-names = "sys_ck", "ref_ck"; 697 status = "disabled"; 698 }; 699 }; 700 701 audiosys: syscon@11220000 { 702 compatible = "mediatek,mt8183-audiosys", "syscon"; 703 reg = <0 0x11220000 0 0x1000>; 704 #clock-cells = <1>; 705 }; 706 707 mmc0: mmc@11230000 { 708 compatible = "mediatek,mt8183-mmc"; 709 reg = <0 0x11230000 0 0x1000>, 710 <0 0x11f50000 0 0x1000>; 711 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 712 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 713 <&infracfg CLK_INFRA_MSDC0>, 714 <&infracfg CLK_INFRA_MSDC0_SCK>; 715 clock-names = "source", "hclk", "source_cg"; 716 status = "disabled"; 717 }; 718 719 mmc1: mmc@11240000 { 720 compatible = "mediatek,mt8183-mmc"; 721 reg = <0 0x11240000 0 0x1000>, 722 <0 0x11e10000 0 0x1000>; 723 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 724 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 725 <&infracfg CLK_INFRA_MSDC1>, 726 <&infracfg CLK_INFRA_MSDC1_SCK>; 727 clock-names = "source", "hclk", "source_cg"; 728 status = "disabled"; 729 }; 730 731 efuse: efuse@11f10000 { 732 compatible = "mediatek,mt8183-efuse", 733 "mediatek,efuse"; 734 reg = <0 0x11f10000 0 0x1000>; 735 }; 736 737 u3phy: usb-phy@11f40000 { 738 compatible = "mediatek,mt8183-tphy", 739 "mediatek,generic-tphy-v2"; 740 #address-cells = <1>; 741 #phy-cells = <1>; 742 #size-cells = <1>; 743 ranges = <0 0 0x11f40000 0x1000>; 744 status = "okay"; 745 746 u2port0: usb-phy@0 { 747 reg = <0x0 0x700>; 748 clocks = <&clk26m>; 749 clock-names = "ref"; 750 #phy-cells = <1>; 751 mediatek,discth = <15>; 752 status = "okay"; 753 }; 754 755 u3port0: usb-phy@0700 { 756 reg = <0x0700 0x900>; 757 clocks = <&clk26m>; 758 clock-names = "ref"; 759 #phy-cells = <1>; 760 status = "okay"; 761 }; 762 }; 763 764 mfgcfg: syscon@13000000 { 765 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 766 reg = <0 0x13000000 0 0x1000>; 767 #clock-cells = <1>; 768 }; 769 770 mmsys: syscon@14000000 { 771 compatible = "mediatek,mt8183-mmsys", "syscon"; 772 reg = <0 0x14000000 0 0x1000>; 773 #clock-cells = <1>; 774 }; 775 776 imgsys: syscon@15020000 { 777 compatible = "mediatek,mt8183-imgsys", "syscon"; 778 reg = <0 0x15020000 0 0x1000>; 779 #clock-cells = <1>; 780 }; 781 782 vdecsys: syscon@16000000 { 783 compatible = "mediatek,mt8183-vdecsys", "syscon"; 784 reg = <0 0x16000000 0 0x1000>; 785 #clock-cells = <1>; 786 }; 787 788 vencsys: syscon@17000000 { 789 compatible = "mediatek,mt8183-vencsys", "syscon"; 790 reg = <0 0x17000000 0 0x1000>; 791 #clock-cells = <1>; 792 }; 793 794 ipu_conn: syscon@19000000 { 795 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 796 reg = <0 0x19000000 0 0x1000>; 797 #clock-cells = <1>; 798 }; 799 800 ipu_adl: syscon@19010000 { 801 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 802 reg = <0 0x19010000 0 0x1000>; 803 #clock-cells = <1>; 804 }; 805 806 ipu_core0: syscon@19180000 { 807 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 808 reg = <0 0x19180000 0 0x1000>; 809 #clock-cells = <1>; 810 }; 811 812 ipu_core1: syscon@19280000 { 813 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 814 reg = <0 0x19280000 0 0x1000>; 815 #clock-cells = <1>; 816 }; 817 818 camsys: syscon@1a000000 { 819 compatible = "mediatek,mt8183-camsys", "syscon"; 820 reg = <0 0x1a000000 0 0x1000>; 821 #clock-cells = <1>; 822 }; 823 }; 824}; 825