1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <0x2>; 87 }; 88 }; 89 90 cpu_opp_table: cpu_opp_table { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-864000000 { 95 opp-hz = /bits/ 64 <864000000>; 96 opp-microvolt = <725000>; 97 clock-latency-ns = <200000>; 98 }; 99 opp-1056000000 { 100 opp-hz = /bits/ 64 <1056000000>; 101 opp-microvolt = <787500>; 102 clock-latency-ns = <200000>; 103 }; 104 opp-1320000000 { 105 opp-hz = /bits/ 64 <1320000000>; 106 opp-microvolt = <862500>; 107 clock-latency-ns = <200000>; 108 }; 109 opp-1440000000 { 110 opp-hz = /bits/ 64 <1440000000>; 111 opp-microvolt = <925000>; 112 clock-latency-ns = <200000>; 113 }; 114 opp-1608000000 { 115 opp-hz = /bits/ 64 <1608000000>; 116 opp-microvolt = <987500>; 117 clock-latency-ns = <200000>; 118 }; 119 opp-1800000000 { 120 opp-hz = /bits/ 64 <1800000000>; 121 opp-microvolt = <1062500>; 122 clock-latency-ns = <200000>; 123 }; 124 }; 125 126 firmware { 127 scm { 128 compatible = "qcom,scm"; 129 }; 130 }; 131 132 pmuv8: pmu { 133 compatible = "arm,cortex-a53-pmu"; 134 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 135 IRQ_TYPE_LEVEL_HIGH)>; 136 }; 137 138 psci: psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 }; 142 143 reserved-memory { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 rpm_msg_ram: memory@60000 { 149 reg = <0x0 0x60000 0x0 0x6000>; 150 no-map; 151 }; 152 153 tz: memory@4a600000 { 154 reg = <0x0 0x4a600000 0x0 0x00400000>; 155 no-map; 156 }; 157 158 smem_region: memory@4aa00000 { 159 reg = <0x0 0x4aa00000 0x0 0x00100000>; 160 no-map; 161 }; 162 163 q6_region: memory@4ab00000 { 164 reg = <0x0 0x4ab00000 0x0 0x05500000>; 165 no-map; 166 }; 167 }; 168 169 smem { 170 compatible = "qcom,smem"; 171 memory-region = <&smem_region>; 172 hwlocks = <&tcsr_mutex 3>; 173 }; 174 175 soc: soc { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges = <0 0 0 0 0x0 0xffffffff>; 179 dma-ranges; 180 compatible = "simple-bus"; 181 182 prng: qrng@e1000 { 183 compatible = "qcom,prng-ee"; 184 reg = <0x0 0xe3000 0x0 0x1000>; 185 clocks = <&gcc GCC_PRNG_AHB_CLK>; 186 clock-names = "core"; 187 }; 188 189 cryptobam: dma@704000 { 190 compatible = "qcom,bam-v1.7.0"; 191 reg = <0x0 0x00704000 0x0 0x20000>; 192 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 194 clock-names = "bam_clk"; 195 #dma-cells = <1>; 196 qcom,ee = <1>; 197 qcom,controlled-remotely; 198 qcom,config-pipe-trust-reg = <0>; 199 }; 200 201 crypto: crypto@73a000 { 202 compatible = "qcom,crypto-v5.1"; 203 reg = <0x0 0x0073a000 0x0 0x6000>; 204 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 205 <&gcc GCC_CRYPTO_AXI_CLK>, 206 <&gcc GCC_CRYPTO_CLK>; 207 clock-names = "iface", "bus", "core"; 208 dmas = <&cryptobam 2>, <&cryptobam 3>; 209 dma-names = "rx", "tx"; 210 }; 211 212 tlmm: pinctrl@1000000 { 213 compatible = "qcom,ipq6018-pinctrl"; 214 reg = <0x0 0x01000000 0x0 0x300000>; 215 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 216 gpio-controller; 217 #gpio-cells = <2>; 218 gpio-ranges = <&tlmm 0 0 80>; 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 222 serial_3_pins: serial3-pinmux { 223 pins = "gpio44", "gpio45"; 224 function = "blsp2_uart"; 225 drive-strength = <8>; 226 bias-pull-down; 227 }; 228 }; 229 230 gcc: gcc@1800000 { 231 compatible = "qcom,gcc-ipq6018"; 232 reg = <0x0 0x01800000 0x0 0x80000>; 233 clocks = <&xo>, <&sleep_clk>; 234 clock-names = "xo", "sleep_clk"; 235 #clock-cells = <1>; 236 #reset-cells = <1>; 237 }; 238 239 tcsr_mutex: hwlock@1905000 { 240 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 241 reg = <0x0 0x01905000 0x0 0x20000>; 242 #hwlock-cells = <1>; 243 }; 244 245 tcsr_q6: syscon@1945000 { 246 compatible = "syscon"; 247 reg = <0x0 0x01945000 0x0 0xe000>; 248 }; 249 250 blsp_dma: dma@7884000 { 251 compatible = "qcom,bam-v1.7.0"; 252 reg = <0x0 0x07884000 0x0 0x2b000>; 253 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 255 clock-names = "bam_clk"; 256 #dma-cells = <1>; 257 qcom,ee = <0>; 258 }; 259 260 blsp1_uart3: serial@78b1000 { 261 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 262 reg = <0x0 0x078b1000 0x0 0x200>; 263 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 265 <&gcc GCC_BLSP1_AHB_CLK>; 266 clock-names = "core", "iface"; 267 status = "disabled"; 268 }; 269 270 spi_0: spi@78b5000 { 271 compatible = "qcom,spi-qup-v2.2.1"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0x0 0x078b5000 0x0 0x600>; 275 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 276 spi-max-frequency = <50000000>; 277 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 278 <&gcc GCC_BLSP1_AHB_CLK>; 279 clock-names = "core", "iface"; 280 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 281 dma-names = "tx", "rx"; 282 status = "disabled"; 283 }; 284 285 spi_1: spi@78b6000 { 286 compatible = "qcom,spi-qup-v2.2.1"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 reg = <0x0 0x078b6000 0x0 0x600>; 290 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 291 spi-max-frequency = <50000000>; 292 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 293 <&gcc GCC_BLSP1_AHB_CLK>; 294 clock-names = "core", "iface"; 295 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 296 dma-names = "tx", "rx"; 297 status = "disabled"; 298 }; 299 300 i2c_0: i2c@78b6000 { 301 compatible = "qcom,i2c-qup-v2.2.1"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <0x0 0x078b6000 0x0 0x600>; 305 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 307 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 308 clock-names = "iface", "core"; 309 clock-frequency = <400000>; 310 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 311 dma-names = "rx", "tx"; 312 status = "disabled"; 313 }; 314 315 i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 316 compatible = "qcom,i2c-qup-v2.2.1"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <0x0 0x078b7000 0x0 0x600>; 320 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 322 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 323 clock-names = "iface", "core"; 324 clock-frequency = <400000>; 325 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 330 intc: interrupt-controller@b000000 { 331 compatible = "qcom,msm-qgic2"; 332 interrupt-controller; 333 #interrupt-cells = <0x3>; 334 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 335 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 336 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 337 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 338 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 339 }; 340 341 watchdog@b017000 { 342 compatible = "qcom,kpss-wdt"; 343 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 344 reg = <0x0 0x0b017000 0x0 0x40>; 345 clocks = <&sleep_clk>; 346 timeout-sec = <10>; 347 }; 348 349 apcs_glb: mailbox@b111000 { 350 compatible = "qcom,ipq6018-apcs-apps-global"; 351 reg = <0x0 0x0b111000 0x0 0x1000>; 352 #clock-cells = <1>; 353 clocks = <&a53pll>, <&xo>; 354 clock-names = "pll", "xo"; 355 #mbox-cells = <1>; 356 }; 357 358 a53pll: clock@b116000 { 359 compatible = "qcom,ipq6018-a53pll"; 360 reg = <0x0 0x0b116000 0x0 0x40>; 361 #clock-cells = <0>; 362 clocks = <&xo>; 363 clock-names = "xo"; 364 }; 365 366 timer { 367 compatible = "arm,armv8-timer"; 368 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 369 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 370 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 371 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 372 }; 373 374 timer@b120000 { 375 #address-cells = <2>; 376 #size-cells = <2>; 377 ranges; 378 compatible = "arm,armv7-timer-mem"; 379 reg = <0x0 0x0b120000 0x0 0x1000>; 380 clock-frequency = <19200000>; 381 382 frame@b120000 { 383 frame-number = <0>; 384 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 386 reg = <0x0 0x0b121000 0x0 0x1000>, 387 <0x0 0x0b122000 0x0 0x1000>; 388 }; 389 390 frame@b123000 { 391 frame-number = <1>; 392 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 393 reg = <0x0 0xb123000 0x0 0x1000>; 394 status = "disabled"; 395 }; 396 397 frame@b124000 { 398 frame-number = <2>; 399 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 400 reg = <0x0 0x0b124000 0x0 0x1000>; 401 status = "disabled"; 402 }; 403 404 frame@b125000 { 405 frame-number = <3>; 406 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 407 reg = <0x0 0x0b125000 0x0 0x1000>; 408 status = "disabled"; 409 }; 410 411 frame@b126000 { 412 frame-number = <4>; 413 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 414 reg = <0x0 0x0b126000 0x0 0x1000>; 415 status = "disabled"; 416 }; 417 418 frame@b127000 { 419 frame-number = <5>; 420 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 421 reg = <0x0 0x0b127000 0x0 0x1000>; 422 status = "disabled"; 423 }; 424 425 frame@b128000 { 426 frame-number = <6>; 427 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 428 reg = <0x0 0x0b128000 0x0 0x1000>; 429 status = "disabled"; 430 }; 431 }; 432 433 q6v5_wcss: remoteproc@cd00000 { 434 compatible = "qcom,ipq8074-wcss-pil"; 435 reg = <0x0 0x0cd00000 0x0 0x4040>, 436 <0x0 0x004ab000 0x0 0x20>; 437 reg-names = "qdsp6", 438 "rmb"; 439 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 440 <&wcss_smp2p_in 0 0>, 441 <&wcss_smp2p_in 1 0>, 442 <&wcss_smp2p_in 2 0>, 443 <&wcss_smp2p_in 3 0>; 444 interrupt-names = "wdog", 445 "fatal", 446 "ready", 447 "handover", 448 "stop-ack"; 449 450 resets = <&gcc GCC_WCSSAON_RESET>, 451 <&gcc GCC_WCSS_BCR>, 452 <&gcc GCC_WCSS_Q6_BCR>; 453 454 reset-names = "wcss_aon_reset", 455 "wcss_reset", 456 "wcss_q6_reset"; 457 458 clocks = <&gcc GCC_PRNG_AHB_CLK>; 459 clock-names = "prng"; 460 461 qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; 462 463 qcom,smem-states = <&wcss_smp2p_out 0>, 464 <&wcss_smp2p_out 1>; 465 qcom,smem-state-names = "shutdown", 466 "stop"; 467 468 memory-region = <&q6_region>; 469 470 glink-edge { 471 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 472 qcom,remote-pid = <1>; 473 mboxes = <&apcs_glb 8>; 474 475 qrtr_requests { 476 qcom,glink-channels = "IPCRTR"; 477 }; 478 }; 479 }; 480 481 }; 482 483 wcss: wcss-smp2p { 484 compatible = "qcom,smp2p"; 485 qcom,smem = <435>, <428>; 486 487 interrupt-parent = <&intc>; 488 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 489 490 mboxes = <&apcs_glb 9>; 491 492 qcom,local-pid = <0>; 493 qcom,remote-pid = <1>; 494 495 wcss_smp2p_out: master-kernel { 496 qcom,entry-name = "master-kernel"; 497 #qcom,smem-state-cells = <1>; 498 }; 499 500 wcss_smp2p_in: slave-kernel { 501 qcom,entry-name = "slave-kernel"; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 }; 505 }; 506 507 rpm-glink { 508 compatible = "qcom,glink-rpm"; 509 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 510 qcom,rpm-msg-ram = <&rpm_msg_ram>; 511 mboxes = <&apcs_glb 0>; 512 513 rpm_requests: glink-channel { 514 compatible = "qcom,rpm-ipq6018"; 515 qcom,glink-channels = "rpm_requests"; 516 517 regulators { 518 compatible = "qcom,rpm-mp5496-regulators"; 519 520 ipq6018_s2: s2 { 521 regulator-min-microvolt = <725000>; 522 regulator-max-microvolt = <1062500>; 523 regulator-always-on; 524 }; 525 }; 526 }; 527 }; 528}; 529