1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,apr.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32764>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 capacity-dmips-mhz = <1024>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 CPU2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo"; 66 reg = <0x0 0x100>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CPU_SLEEP_0>; 69 capacity-dmips-mhz = <1024>; 70 next-level-cache = <&L2_1>; 71 L2_1: l2-cache { 72 compatible = "cache"; 73 cache-level = <2>; 74 }; 75 }; 76 77 CPU3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo"; 80 reg = <0x0 0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 capacity-dmips-mhz = <1024>; 84 next-level-cache = <&L2_1>; 85 }; 86 87 cpu-map { 88 cluster0 { 89 core0 { 90 cpu = <&CPU0>; 91 }; 92 93 core1 { 94 cpu = <&CPU1>; 95 }; 96 }; 97 98 cluster1 { 99 core0 { 100 cpu = <&CPU2>; 101 }; 102 103 core1 { 104 cpu = <&CPU3>; 105 }; 106 }; 107 }; 108 109 idle-states { 110 entry-method = "psci"; 111 112 CPU_SLEEP_0: cpu-sleep-0 { 113 compatible = "arm,idle-state"; 114 idle-state-name = "standalone-power-collapse"; 115 arm,psci-suspend-param = <0x00000004>; 116 entry-latency-us = <130>; 117 exit-latency-us = <80>; 118 min-residency-us = <300>; 119 }; 120 }; 121 }; 122 123 firmware { 124 scm { 125 compatible = "qcom,scm-msm8996"; 126 qcom,dload-mode = <&tcsr 0x13000>; 127 }; 128 }; 129 130 tcsr_mutex: hwlock { 131 compatible = "qcom,tcsr-mutex"; 132 syscon = <&tcsr_mutex_regs 0 0x1000>; 133 #hwlock-cells = <1>; 134 }; 135 136 memory { 137 device_type = "memory"; 138 /* We expect the bootloader to fill in the reg */ 139 reg = <0 0 0 0>; 140 }; 141 142 etm { 143 compatible = "qcom,coresight-remote-etm"; 144 145 out-ports { 146 port { 147 modem_etm_out_funnel_in2: endpoint { 148 remote-endpoint = 149 <&funnel_in2_in_modem_etm>; 150 }; 151 }; 152 }; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0"; 157 method = "smc"; 158 }; 159 160 reserved-memory { 161 #address-cells = <2>; 162 #size-cells = <2>; 163 ranges; 164 165 mba_region: mba@91500000 { 166 reg = <0x0 0x91500000 0x0 0x200000>; 167 no-map; 168 }; 169 170 slpi_region: slpi@90b00000 { 171 reg = <0x0 0x90b00000 0x0 0xa00000>; 172 no-map; 173 }; 174 175 venus_region: venus@90400000 { 176 reg = <0x0 0x90400000 0x0 0x700000>; 177 no-map; 178 }; 179 180 adsp_region: adsp@8ea00000 { 181 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 182 no-map; 183 }; 184 185 mpss_region: mpss@88800000 { 186 reg = <0x0 0x88800000 0x0 0x6200000>; 187 no-map; 188 }; 189 190 smem_mem: smem-mem@86000000 { 191 reg = <0x0 0x86000000 0x0 0x200000>; 192 no-map; 193 }; 194 195 memory@85800000 { 196 reg = <0x0 0x85800000 0x0 0x800000>; 197 no-map; 198 }; 199 200 memory@86200000 { 201 reg = <0x0 0x86200000 0x0 0x2600000>; 202 no-map; 203 }; 204 205 rmtfs@86700000 { 206 compatible = "qcom,rmtfs-mem"; 207 208 size = <0x0 0x200000>; 209 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 210 no-map; 211 212 qcom,client-id = <1>; 213 qcom,vmid = <15>; 214 }; 215 216 zap_shader_region: gpu@8f200000 { 217 compatible = "shared-dma-pool"; 218 reg = <0x0 0x90b00000 0x0 0xa00000>; 219 no-map; 220 }; 221 }; 222 223 rpm-glink { 224 compatible = "qcom,glink-rpm"; 225 226 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 227 228 qcom,rpm-msg-ram = <&rpm_msg_ram>; 229 230 mboxes = <&apcs_glb 0>; 231 232 rpm_requests: rpm-requests { 233 compatible = "qcom,rpm-msm8996"; 234 qcom,glink-channels = "rpm_requests"; 235 236 rpmcc: qcom,rpmcc { 237 compatible = "qcom,rpmcc-msm8996"; 238 #clock-cells = <1>; 239 }; 240 241 rpmpd: power-controller { 242 compatible = "qcom,msm8996-rpmpd"; 243 #power-domain-cells = <1>; 244 operating-points-v2 = <&rpmpd_opp_table>; 245 246 rpmpd_opp_table: opp-table { 247 compatible = "operating-points-v2"; 248 249 rpmpd_opp1: opp1 { 250 opp-level = <1>; 251 }; 252 253 rpmpd_opp2: opp2 { 254 opp-level = <2>; 255 }; 256 257 rpmpd_opp3: opp3 { 258 opp-level = <3>; 259 }; 260 261 rpmpd_opp4: opp4 { 262 opp-level = <4>; 263 }; 264 265 rpmpd_opp5: opp5 { 266 opp-level = <5>; 267 }; 268 269 rpmpd_opp6: opp6 { 270 opp-level = <6>; 271 }; 272 }; 273 }; 274 }; 275 }; 276 277 smem { 278 compatible = "qcom,smem"; 279 memory-region = <&smem_mem>; 280 hwlocks = <&tcsr_mutex 3>; 281 }; 282 283 smp2p-adsp { 284 compatible = "qcom,smp2p"; 285 qcom,smem = <443>, <429>; 286 287 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 288 289 mboxes = <&apcs_glb 10>; 290 291 qcom,local-pid = <0>; 292 qcom,remote-pid = <2>; 293 294 smp2p_adsp_out: master-kernel { 295 qcom,entry-name = "master-kernel"; 296 #qcom,smem-state-cells = <1>; 297 }; 298 299 smp2p_adsp_in: slave-kernel { 300 qcom,entry-name = "slave-kernel"; 301 302 interrupt-controller; 303 #interrupt-cells = <2>; 304 }; 305 }; 306 307 smp2p-modem { 308 compatible = "qcom,smp2p"; 309 qcom,smem = <435>, <428>; 310 311 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 312 313 mboxes = <&apcs_glb 14>; 314 315 qcom,local-pid = <0>; 316 qcom,remote-pid = <1>; 317 318 modem_smp2p_out: master-kernel { 319 qcom,entry-name = "master-kernel"; 320 #qcom,smem-state-cells = <1>; 321 }; 322 323 modem_smp2p_in: slave-kernel { 324 qcom,entry-name = "slave-kernel"; 325 326 interrupt-controller; 327 #interrupt-cells = <2>; 328 }; 329 }; 330 331 smp2p-slpi { 332 compatible = "qcom,smp2p"; 333 qcom,smem = <481>, <430>; 334 335 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 336 337 mboxes = <&apcs_glb 26>; 338 339 qcom,local-pid = <0>; 340 qcom,remote-pid = <3>; 341 342 smp2p_slpi_in: slave-kernel { 343 qcom,entry-name = "slave-kernel"; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 }; 347 348 smp2p_slpi_out: master-kernel { 349 qcom,entry-name = "master-kernel"; 350 #qcom,smem-state-cells = <1>; 351 }; 352 }; 353 354 soc: soc { 355 #address-cells = <1>; 356 #size-cells = <1>; 357 ranges = <0 0 0 0xffffffff>; 358 compatible = "simple-bus"; 359 360 pcie_phy: phy@34000 { 361 compatible = "qcom,msm8996-qmp-pcie-phy"; 362 reg = <0x00034000 0x488>; 363 #clock-cells = <1>; 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges; 367 368 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 369 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 370 <&gcc GCC_PCIE_CLKREF_CLK>; 371 clock-names = "aux", "cfg_ahb", "ref"; 372 373 resets = <&gcc GCC_PCIE_PHY_BCR>, 374 <&gcc GCC_PCIE_PHY_COM_BCR>, 375 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 376 reset-names = "phy", "common", "cfg"; 377 status = "disabled"; 378 379 pciephy_0: lane@35000 { 380 reg = <0x00035000 0x130>, 381 <0x00035200 0x200>, 382 <0x00035400 0x1dc>; 383 #phy-cells = <0>; 384 385 clock-output-names = "pcie_0_pipe_clk_src"; 386 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 387 clock-names = "pipe0"; 388 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 389 reset-names = "lane0"; 390 }; 391 392 pciephy_1: lane@36000 { 393 reg = <0x00036000 0x130>, 394 <0x00036200 0x200>, 395 <0x00036400 0x1dc>; 396 #phy-cells = <0>; 397 398 clock-output-names = "pcie_1_pipe_clk_src"; 399 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 400 clock-names = "pipe1"; 401 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 402 reset-names = "lane1"; 403 }; 404 405 pciephy_2: lane@37000 { 406 reg = <0x00037000 0x130>, 407 <0x00037200 0x200>, 408 <0x00037400 0x1dc>; 409 #phy-cells = <0>; 410 411 clock-output-names = "pcie_2_pipe_clk_src"; 412 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 413 clock-names = "pipe2"; 414 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 415 reset-names = "lane2"; 416 }; 417 }; 418 419 rpm_msg_ram: memory@68000 { 420 compatible = "qcom,rpm-msg-ram"; 421 reg = <0x00068000 0x6000>; 422 }; 423 424 qfprom@74000 { 425 compatible = "qcom,qfprom"; 426 reg = <0x00074000 0x8ff>; 427 #address-cells = <1>; 428 #size-cells = <1>; 429 430 qusb2p_hstx_trim: hstx_trim@24e { 431 reg = <0x24e 0x2>; 432 bits = <5 4>; 433 }; 434 435 qusb2s_hstx_trim: hstx_trim@24f { 436 reg = <0x24f 0x1>; 437 bits = <1 4>; 438 }; 439 440 gpu_speed_bin: gpu_speed_bin@133 { 441 reg = <0x133 0x1>; 442 bits = <5 3>; 443 }; 444 }; 445 446 rng: rng@83000 { 447 compatible = "qcom,prng-ee"; 448 reg = <0x00083000 0x1000>; 449 clocks = <&gcc GCC_PRNG_AHB_CLK>; 450 clock-names = "core"; 451 }; 452 453 gcc: clock-controller@300000 { 454 compatible = "qcom,gcc-msm8996"; 455 #clock-cells = <1>; 456 #reset-cells = <1>; 457 #power-domain-cells = <1>; 458 reg = <0x00300000 0x90000>; 459 460 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; 461 clock-names = "cxo2"; 462 }; 463 464 tsens0: thermal-sensor@4a9000 { 465 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 466 reg = <0x004a9000 0x1000>, /* TM */ 467 <0x004a8000 0x1000>; /* SROT */ 468 #qcom,sensors = <13>; 469 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 471 interrupt-names = "uplow", "critical"; 472 #thermal-sensor-cells = <1>; 473 }; 474 475 tsens1: thermal-sensor@4ad000 { 476 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 477 reg = <0x004ad000 0x1000>, /* TM */ 478 <0x004ac000 0x1000>; /* SROT */ 479 #qcom,sensors = <8>; 480 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "uplow", "critical"; 483 #thermal-sensor-cells = <1>; 484 }; 485 486 tcsr_mutex_regs: syscon@740000 { 487 compatible = "syscon"; 488 reg = <0x00740000 0x20000>; 489 }; 490 491 tcsr: syscon@7a0000 { 492 compatible = "qcom,tcsr-msm8996", "syscon"; 493 reg = <0x007a0000 0x18000>; 494 }; 495 496 mmcc: clock-controller@8c0000 { 497 compatible = "qcom,mmcc-msm8996"; 498 #clock-cells = <1>; 499 #reset-cells = <1>; 500 #power-domain-cells = <1>; 501 reg = <0x008c0000 0x40000>; 502 assigned-clocks = <&mmcc MMPLL9_PLL>, 503 <&mmcc MMPLL1_PLL>, 504 <&mmcc MMPLL3_PLL>, 505 <&mmcc MMPLL4_PLL>, 506 <&mmcc MMPLL5_PLL>; 507 assigned-clock-rates = <624000000>, 508 <810000000>, 509 <980000000>, 510 <960000000>, 511 <825000000>; 512 }; 513 514 mdss: mdss@900000 { 515 compatible = "qcom,mdss"; 516 517 reg = <0x00900000 0x1000>, 518 <0x009b0000 0x1040>, 519 <0x009b8000 0x1040>; 520 reg-names = "mdss_phys", 521 "vbif_phys", 522 "vbif_nrt_phys"; 523 524 power-domains = <&mmcc MDSS_GDSC>; 525 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 526 527 interrupt-controller; 528 #interrupt-cells = <1>; 529 530 clocks = <&mmcc MDSS_AHB_CLK>; 531 clock-names = "iface"; 532 533 #address-cells = <1>; 534 #size-cells = <1>; 535 ranges; 536 537 mdp: mdp@901000 { 538 compatible = "qcom,mdp5"; 539 reg = <0x00901000 0x90000>; 540 reg-names = "mdp_phys"; 541 542 interrupt-parent = <&mdss>; 543 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 544 545 clocks = <&mmcc MDSS_AHB_CLK>, 546 <&mmcc MDSS_AXI_CLK>, 547 <&mmcc MDSS_MDP_CLK>, 548 <&mmcc SMMU_MDP_AXI_CLK>, 549 <&mmcc MDSS_VSYNC_CLK>; 550 clock-names = "iface", 551 "bus", 552 "core", 553 "iommu", 554 "vsync"; 555 556 iommus = <&mdp_smmu 0>; 557 558 ports { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 562 port@0 { 563 reg = <0>; 564 mdp5_intf3_out: endpoint { 565 remote-endpoint = <&hdmi_in>; 566 }; 567 }; 568 }; 569 }; 570 571 hdmi: hdmi-tx@9a0000 { 572 compatible = "qcom,hdmi-tx-8996"; 573 reg = <0x009a0000 0x50c>, 574 <0x00070000 0x6158>, 575 <0x009e0000 0xfff>; 576 reg-names = "core_physical", 577 "qfprom_physical", 578 "hdcp_physical"; 579 580 interrupt-parent = <&mdss>; 581 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 582 583 clocks = <&mmcc MDSS_MDP_CLK>, 584 <&mmcc MDSS_AHB_CLK>, 585 <&mmcc MDSS_HDMI_CLK>, 586 <&mmcc MDSS_HDMI_AHB_CLK>, 587 <&mmcc MDSS_EXTPCLK_CLK>; 588 clock-names = 589 "mdp_core", 590 "iface", 591 "core", 592 "alt_iface", 593 "extp"; 594 595 phys = <&hdmi_phy>; 596 phy-names = "hdmi_phy"; 597 #sound-dai-cells = <1>; 598 599 ports { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 603 port@0 { 604 reg = <0>; 605 hdmi_in: endpoint { 606 remote-endpoint = <&mdp5_intf3_out>; 607 }; 608 }; 609 }; 610 }; 611 612 hdmi_phy: hdmi-phy@9a0600 { 613 #phy-cells = <0>; 614 compatible = "qcom,hdmi-phy-8996"; 615 reg = <0x009a0600 0x1c4>, 616 <0x009a0a00 0x124>, 617 <0x009a0c00 0x124>, 618 <0x009a0e00 0x124>, 619 <0x009a1000 0x124>, 620 <0x009a1200 0x0c8>; 621 reg-names = "hdmi_pll", 622 "hdmi_tx_l0", 623 "hdmi_tx_l1", 624 "hdmi_tx_l2", 625 "hdmi_tx_l3", 626 "hdmi_phy"; 627 628 clocks = <&mmcc MDSS_AHB_CLK>, 629 <&gcc GCC_HDMI_CLKREF_CLK>; 630 clock-names = "iface", 631 "ref"; 632 }; 633 }; 634 gpu@b00000 { 635 compatible = "qcom,adreno-530.2", "qcom,adreno"; 636 #stream-id-cells = <16>; 637 638 reg = <0x00b00000 0x3f000>; 639 reg-names = "kgsl_3d0_reg_memory"; 640 641 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 642 643 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 644 <&mmcc GPU_AHB_CLK>, 645 <&mmcc GPU_GX_RBBMTIMER_CLK>, 646 <&gcc GCC_BIMC_GFX_CLK>, 647 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 648 649 clock-names = "core", 650 "iface", 651 "rbbmtimer", 652 "mem", 653 "mem_iface"; 654 655 power-domains = <&mmcc GPU_GX_GDSC>; 656 iommus = <&adreno_smmu 0>; 657 658 nvmem-cells = <&gpu_speed_bin>; 659 nvmem-cell-names = "speed_bin"; 660 661 operating-points-v2 = <&gpu_opp_table>; 662 663 gpu_opp_table: opp-table { 664 compatible ="operating-points-v2"; 665 666 /* 667 * 624Mhz is only available on speed bins 0 and 3. 668 * 560Mhz is only available on speed bins 0, 2 and 3. 669 * All the rest are available on all bins of the hardware. 670 */ 671 opp-624000000 { 672 opp-hz = /bits/ 64 <624000000>; 673 opp-supported-hw = <0x09>; 674 }; 675 opp-560000000 { 676 opp-hz = /bits/ 64 <560000000>; 677 opp-supported-hw = <0x0d>; 678 }; 679 opp-510000000 { 680 opp-hz = /bits/ 64 <510000000>; 681 opp-supported-hw = <0xFF>; 682 }; 683 opp-401800000 { 684 opp-hz = /bits/ 64 <401800000>; 685 opp-supported-hw = <0xFF>; 686 }; 687 opp-315000000 { 688 opp-hz = /bits/ 64 <315000000>; 689 opp-supported-hw = <0xFF>; 690 }; 691 opp-214000000 { 692 opp-hz = /bits/ 64 <214000000>; 693 opp-supported-hw = <0xFF>; 694 }; 695 opp-133000000 { 696 opp-hz = /bits/ 64 <133000000>; 697 opp-supported-hw = <0xFF>; 698 }; 699 }; 700 701 zap-shader { 702 memory-region = <&zap_shader_region>; 703 }; 704 }; 705 706 msmgpio: pinctrl@1010000 { 707 compatible = "qcom,msm8996-pinctrl"; 708 reg = <0x01010000 0x300000>; 709 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 710 gpio-controller; 711 gpio-ranges = <&msmgpio 0 0 150>; 712 #gpio-cells = <2>; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 717 spmi_bus: qcom,spmi@400f000 { 718 compatible = "qcom,spmi-pmic-arb"; 719 reg = <0x0400f000 0x1000>, 720 <0x04400000 0x800000>, 721 <0x04c00000 0x800000>, 722 <0x05800000 0x200000>, 723 <0x0400a000 0x002100>; 724 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 725 interrupt-names = "periph_irq"; 726 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 727 qcom,ee = <0>; 728 qcom,channel = <0>; 729 #address-cells = <2>; 730 #size-cells = <0>; 731 interrupt-controller; 732 #interrupt-cells = <4>; 733 }; 734 735 agnoc@0 { 736 power-domains = <&gcc AGGRE0_NOC_GDSC>; 737 compatible = "simple-pm-bus"; 738 #address-cells = <1>; 739 #size-cells = <1>; 740 ranges; 741 742 pcie0: pcie@600000 { 743 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 744 status = "disabled"; 745 power-domains = <&gcc PCIE0_GDSC>; 746 bus-range = <0x00 0xff>; 747 num-lanes = <1>; 748 749 reg = <0x00600000 0x2000>, 750 <0x0c000000 0xf1d>, 751 <0x0c000f20 0xa8>, 752 <0x0c100000 0x100000>; 753 reg-names = "parf", "dbi", "elbi","config"; 754 755 phys = <&pciephy_0>; 756 phy-names = "pciephy"; 757 758 #address-cells = <3>; 759 #size-cells = <2>; 760 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 761 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 762 763 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 764 interrupt-names = "msi"; 765 #interrupt-cells = <1>; 766 interrupt-map-mask = <0 0 0 0x7>; 767 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 768 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 769 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 770 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 771 772 pinctrl-names = "default", "sleep"; 773 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 774 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 775 776 linux,pci-domain = <0>; 777 778 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 779 <&gcc GCC_PCIE_0_AUX_CLK>, 780 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 781 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 782 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 783 784 clock-names = "pipe", 785 "aux", 786 "cfg", 787 "bus_master", 788 "bus_slave"; 789 790 }; 791 792 pcie1: pcie@608000 { 793 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 794 power-domains = <&gcc PCIE1_GDSC>; 795 bus-range = <0x00 0xff>; 796 num-lanes = <1>; 797 798 status = "disabled"; 799 800 reg = <0x00608000 0x2000>, 801 <0x0d000000 0xf1d>, 802 <0x0d000f20 0xa8>, 803 <0x0d100000 0x100000>; 804 805 reg-names = "parf", "dbi", "elbi","config"; 806 807 phys = <&pciephy_1>; 808 phy-names = "pciephy"; 809 810 #address-cells = <3>; 811 #size-cells = <2>; 812 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 813 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 814 815 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "msi"; 817 #interrupt-cells = <1>; 818 interrupt-map-mask = <0 0 0 0x7>; 819 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 820 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 821 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 822 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 823 824 pinctrl-names = "default", "sleep"; 825 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 826 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 827 828 linux,pci-domain = <1>; 829 830 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 831 <&gcc GCC_PCIE_1_AUX_CLK>, 832 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 833 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 834 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 835 836 clock-names = "pipe", 837 "aux", 838 "cfg", 839 "bus_master", 840 "bus_slave"; 841 }; 842 843 pcie2: pcie@610000 { 844 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 845 power-domains = <&gcc PCIE2_GDSC>; 846 bus-range = <0x00 0xff>; 847 num-lanes = <1>; 848 status = "disabled"; 849 reg = <0x00610000 0x2000>, 850 <0x0e000000 0xf1d>, 851 <0x0e000f20 0xa8>, 852 <0x0e100000 0x100000>; 853 854 reg-names = "parf", "dbi", "elbi","config"; 855 856 phys = <&pciephy_2>; 857 phy-names = "pciephy"; 858 859 #address-cells = <3>; 860 #size-cells = <2>; 861 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 862 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 863 864 device_type = "pci"; 865 866 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-names = "msi"; 868 #interrupt-cells = <1>; 869 interrupt-map-mask = <0 0 0 0x7>; 870 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 871 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 872 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 873 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 874 875 pinctrl-names = "default", "sleep"; 876 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 877 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 878 879 linux,pci-domain = <2>; 880 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 881 <&gcc GCC_PCIE_2_AUX_CLK>, 882 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 883 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 884 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 885 886 clock-names = "pipe", 887 "aux", 888 "cfg", 889 "bus_master", 890 "bus_slave"; 891 }; 892 }; 893 894 ufshc: ufshc@624000 { 895 compatible = "qcom,ufshc"; 896 reg = <0x00624000 0x2500>; 897 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 898 899 phys = <&ufsphy_lane>; 900 phy-names = "ufsphy"; 901 902 power-domains = <&gcc UFS_GDSC>; 903 904 clock-names = 905 "core_clk_src", 906 "core_clk", 907 "bus_clk", 908 "bus_aggr_clk", 909 "iface_clk", 910 "core_clk_unipro_src", 911 "core_clk_unipro", 912 "core_clk_ice", 913 "ref_clk", 914 "tx_lane0_sync_clk", 915 "rx_lane0_sync_clk"; 916 clocks = 917 <&gcc UFS_AXI_CLK_SRC>, 918 <&gcc GCC_UFS_AXI_CLK>, 919 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 920 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 921 <&gcc GCC_UFS_AHB_CLK>, 922 <&gcc UFS_ICE_CORE_CLK_SRC>, 923 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 924 <&gcc GCC_UFS_ICE_CORE_CLK>, 925 <&rpmcc RPM_SMD_LN_BB_CLK>, 926 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 927 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 928 freq-table-hz = 929 <100000000 200000000>, 930 <0 0>, 931 <0 0>, 932 <0 0>, 933 <0 0>, 934 <150000000 300000000>, 935 <0 0>, 936 <0 0>, 937 <0 0>, 938 <0 0>, 939 <0 0>; 940 941 lanes-per-direction = <1>; 942 #reset-cells = <1>; 943 status = "disabled"; 944 945 ufs_variant { 946 compatible = "qcom,ufs_variant"; 947 }; 948 }; 949 950 ufsphy: phy@627000 { 951 compatible = "qcom,msm8996-qmp-ufs-phy"; 952 reg = <0x00627000 0x1c4>; 953 #address-cells = <1>; 954 #size-cells = <1>; 955 ranges; 956 957 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 958 clock-names = "ref"; 959 960 resets = <&ufshc 0>; 961 reset-names = "ufsphy"; 962 status = "disabled"; 963 964 ufsphy_lane: lanes@627400 { 965 reg = <0x627400 0x12c>, 966 <0x627600 0x200>, 967 <0x627c00 0x1b4>; 968 #phy-cells = <0>; 969 }; 970 }; 971 972 camss: camss@a34000 { 973 compatible = "qcom,msm8996-camss"; 974 reg = <0x00a34000 0x1000>, 975 <0x00a00030 0x4>, 976 <0x00a35000 0x1000>, 977 <0x00a00038 0x4>, 978 <0x00a36000 0x1000>, 979 <0x00a00040 0x4>, 980 <0x00a30000 0x100>, 981 <0x00a30400 0x100>, 982 <0x00a30800 0x100>, 983 <0x00a30c00 0x100>, 984 <0x00a31000 0x500>, 985 <0x00a00020 0x10>, 986 <0x00a10000 0x1000>, 987 <0x00a14000 0x1000>; 988 reg-names = "csiphy0", 989 "csiphy0_clk_mux", 990 "csiphy1", 991 "csiphy1_clk_mux", 992 "csiphy2", 993 "csiphy2_clk_mux", 994 "csid0", 995 "csid1", 996 "csid2", 997 "csid3", 998 "ispif", 999 "csi_clk_mux", 1000 "vfe0", 1001 "vfe1"; 1002 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1003 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1004 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1005 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1006 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1007 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1008 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1009 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1010 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1011 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1012 interrupt-names = "csiphy0", 1013 "csiphy1", 1014 "csiphy2", 1015 "csid0", 1016 "csid1", 1017 "csid2", 1018 "csid3", 1019 "ispif", 1020 "vfe0", 1021 "vfe1"; 1022 power-domains = <&mmcc VFE0_GDSC>, 1023 <&mmcc VFE1_GDSC>; 1024 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1025 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1026 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1027 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1028 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1029 <&mmcc CAMSS_CSI0_AHB_CLK>, 1030 <&mmcc CAMSS_CSI0_CLK>, 1031 <&mmcc CAMSS_CSI0PHY_CLK>, 1032 <&mmcc CAMSS_CSI0PIX_CLK>, 1033 <&mmcc CAMSS_CSI0RDI_CLK>, 1034 <&mmcc CAMSS_CSI1_AHB_CLK>, 1035 <&mmcc CAMSS_CSI1_CLK>, 1036 <&mmcc CAMSS_CSI1PHY_CLK>, 1037 <&mmcc CAMSS_CSI1PIX_CLK>, 1038 <&mmcc CAMSS_CSI1RDI_CLK>, 1039 <&mmcc CAMSS_CSI2_AHB_CLK>, 1040 <&mmcc CAMSS_CSI2_CLK>, 1041 <&mmcc CAMSS_CSI2PHY_CLK>, 1042 <&mmcc CAMSS_CSI2PIX_CLK>, 1043 <&mmcc CAMSS_CSI2RDI_CLK>, 1044 <&mmcc CAMSS_CSI3_AHB_CLK>, 1045 <&mmcc CAMSS_CSI3_CLK>, 1046 <&mmcc CAMSS_CSI3PHY_CLK>, 1047 <&mmcc CAMSS_CSI3PIX_CLK>, 1048 <&mmcc CAMSS_CSI3RDI_CLK>, 1049 <&mmcc CAMSS_AHB_CLK>, 1050 <&mmcc CAMSS_VFE0_CLK>, 1051 <&mmcc CAMSS_CSI_VFE0_CLK>, 1052 <&mmcc CAMSS_VFE0_AHB_CLK>, 1053 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1054 <&mmcc CAMSS_VFE1_CLK>, 1055 <&mmcc CAMSS_CSI_VFE1_CLK>, 1056 <&mmcc CAMSS_VFE1_AHB_CLK>, 1057 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1058 <&mmcc CAMSS_VFE_AHB_CLK>, 1059 <&mmcc CAMSS_VFE_AXI_CLK>; 1060 clock-names = "top_ahb", 1061 "ispif_ahb", 1062 "csiphy0_timer", 1063 "csiphy1_timer", 1064 "csiphy2_timer", 1065 "csi0_ahb", 1066 "csi0", 1067 "csi0_phy", 1068 "csi0_pix", 1069 "csi0_rdi", 1070 "csi1_ahb", 1071 "csi1", 1072 "csi1_phy", 1073 "csi1_pix", 1074 "csi1_rdi", 1075 "csi2_ahb", 1076 "csi2", 1077 "csi2_phy", 1078 "csi2_pix", 1079 "csi2_rdi", 1080 "csi3_ahb", 1081 "csi3", 1082 "csi3_phy", 1083 "csi3_pix", 1084 "csi3_rdi", 1085 "ahb", 1086 "vfe0", 1087 "csi_vfe0", 1088 "vfe0_ahb", 1089 "vfe0_stream", 1090 "vfe1", 1091 "csi_vfe1", 1092 "vfe1_ahb", 1093 "vfe1_stream", 1094 "vfe_ahb", 1095 "vfe_axi"; 1096 iommus = <&vfe_smmu 0>, 1097 <&vfe_smmu 1>, 1098 <&vfe_smmu 2>, 1099 <&vfe_smmu 3>; 1100 status = "disabled"; 1101 ports { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 }; 1105 }; 1106 1107 cci: cci@a0c000 { 1108 compatible = "qcom,msm8996-cci"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 reg = <0xa0c000 0x1000>; 1112 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1113 power-domains = <&mmcc CAMSS_GDSC>; 1114 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1115 <&mmcc CAMSS_CCI_AHB_CLK>, 1116 <&mmcc CAMSS_CCI_CLK>, 1117 <&mmcc CAMSS_AHB_CLK>; 1118 clock-names = "camss_top_ahb", 1119 "cci_ahb", 1120 "cci", 1121 "camss_ahb"; 1122 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1123 <&mmcc CAMSS_CCI_CLK>; 1124 assigned-clock-rates = <80000000>, <37500000>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&cci0_default &cci1_default>; 1127 status = "disabled"; 1128 1129 cci_i2c0: i2c-bus@0 { 1130 reg = <0>; 1131 clock-frequency = <400000>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 }; 1135 1136 cci_i2c1: i2c-bus@1 { 1137 reg = <1>; 1138 clock-frequency = <400000>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 }; 1142 }; 1143 1144 adreno_smmu: iommu@b40000 { 1145 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1146 reg = <0x00b40000 0x10000>; 1147 1148 #global-interrupts = <1>; 1149 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1152 #iommu-cells = <1>; 1153 1154 clocks = <&mmcc GPU_AHB_CLK>, 1155 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1156 clock-names = "iface", "bus"; 1157 1158 power-domains = <&mmcc GPU_GDSC>; 1159 }; 1160 1161 video-codec@c00000 { 1162 compatible = "qcom,msm8996-venus"; 1163 reg = <0x00c00000 0xff000>; 1164 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 1165 power-domains = <&mmcc VENUS_GDSC>; 1166 clocks = <&mmcc VIDEO_CORE_CLK>, 1167 <&mmcc VIDEO_AHB_CLK>, 1168 <&mmcc VIDEO_AXI_CLK>, 1169 <&mmcc VIDEO_MAXI_CLK>; 1170 clock-names = "core", "iface", "bus", "mbus"; 1171 iommus = <&venus_smmu 0x00>, 1172 <&venus_smmu 0x01>, 1173 <&venus_smmu 0x0a>, 1174 <&venus_smmu 0x07>, 1175 <&venus_smmu 0x0e>, 1176 <&venus_smmu 0x0f>, 1177 <&venus_smmu 0x08>, 1178 <&venus_smmu 0x09>, 1179 <&venus_smmu 0x0b>, 1180 <&venus_smmu 0x0c>, 1181 <&venus_smmu 0x0d>, 1182 <&venus_smmu 0x10>, 1183 <&venus_smmu 0x11>, 1184 <&venus_smmu 0x21>, 1185 <&venus_smmu 0x28>, 1186 <&venus_smmu 0x29>, 1187 <&venus_smmu 0x2b>, 1188 <&venus_smmu 0x2c>, 1189 <&venus_smmu 0x2d>, 1190 <&venus_smmu 0x31>; 1191 memory-region = <&venus_region>; 1192 status = "okay"; 1193 1194 video-decoder { 1195 compatible = "venus-decoder"; 1196 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 1197 clock-names = "core"; 1198 power-domains = <&mmcc VENUS_CORE0_GDSC>; 1199 }; 1200 1201 video-encoder { 1202 compatible = "venus-encoder"; 1203 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 1204 clock-names = "core"; 1205 power-domains = <&mmcc VENUS_CORE1_GDSC>; 1206 }; 1207 }; 1208 1209 mdp_smmu: iommu@d00000 { 1210 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1211 reg = <0x00d00000 0x10000>; 1212 1213 #global-interrupts = <1>; 1214 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1217 #iommu-cells = <1>; 1218 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 1219 <&mmcc SMMU_MDP_AXI_CLK>; 1220 clock-names = "iface", "bus"; 1221 1222 power-domains = <&mmcc MDSS_GDSC>; 1223 }; 1224 1225 venus_smmu: iommu@d40000 { 1226 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1227 reg = <0x00d40000 0x20000>; 1228 #global-interrupts = <1>; 1229 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1237 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 1238 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 1239 <&mmcc SMMU_VIDEO_AXI_CLK>; 1240 clock-names = "iface", "bus"; 1241 #iommu-cells = <1>; 1242 status = "okay"; 1243 }; 1244 1245 vfe_smmu: iommu@da0000 { 1246 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1247 reg = <0x00da0000 0x10000>; 1248 1249 #global-interrupts = <1>; 1250 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1253 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 1254 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 1255 <&mmcc SMMU_VFE_AXI_CLK>; 1256 clock-names = "iface", 1257 "bus"; 1258 #iommu-cells = <1>; 1259 }; 1260 1261 lpass_q6_smmu: iommu@1600000 { 1262 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1263 reg = <0x01600000 0x20000>; 1264 #iommu-cells = <1>; 1265 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 1266 1267 #global-interrupts = <1>; 1268 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 1281 1282 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 1283 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1284 clock-names = "iface", "bus"; 1285 }; 1286 1287 stm@3002000 { 1288 compatible = "arm,coresight-stm", "arm,primecell"; 1289 reg = <0x3002000 0x1000>, 1290 <0x8280000 0x180000>; 1291 reg-names = "stm-base", "stm-stimulus-base"; 1292 1293 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1294 clock-names = "apb_pclk", "atclk"; 1295 1296 out-ports { 1297 port { 1298 stm_out: endpoint { 1299 remote-endpoint = 1300 <&funnel0_in>; 1301 }; 1302 }; 1303 }; 1304 }; 1305 1306 tpiu@3020000 { 1307 compatible = "arm,coresight-tpiu", "arm,primecell"; 1308 reg = <0x3020000 0x1000>; 1309 1310 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1311 clock-names = "apb_pclk", "atclk"; 1312 1313 in-ports { 1314 port { 1315 tpiu_in: endpoint { 1316 remote-endpoint = 1317 <&replicator_out1>; 1318 }; 1319 }; 1320 }; 1321 }; 1322 1323 funnel@3021000 { 1324 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1325 reg = <0x3021000 0x1000>; 1326 1327 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1328 clock-names = "apb_pclk", "atclk"; 1329 1330 in-ports { 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 1334 port@7 { 1335 reg = <7>; 1336 funnel0_in: endpoint { 1337 remote-endpoint = 1338 <&stm_out>; 1339 }; 1340 }; 1341 }; 1342 1343 out-ports { 1344 port { 1345 funnel0_out: endpoint { 1346 remote-endpoint = 1347 <&merge_funnel_in0>; 1348 }; 1349 }; 1350 }; 1351 }; 1352 1353 funnel@3022000 { 1354 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1355 reg = <0x3022000 0x1000>; 1356 1357 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1358 clock-names = "apb_pclk", "atclk"; 1359 1360 in-ports { 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 1364 port@6 { 1365 reg = <6>; 1366 funnel1_in: endpoint { 1367 remote-endpoint = 1368 <&apss_merge_funnel_out>; 1369 }; 1370 }; 1371 }; 1372 1373 out-ports { 1374 port { 1375 funnel1_out: endpoint { 1376 remote-endpoint = 1377 <&merge_funnel_in1>; 1378 }; 1379 }; 1380 }; 1381 }; 1382 1383 funnel@3023000 { 1384 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1385 reg = <0x3023000 0x1000>; 1386 1387 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1388 clock-names = "apb_pclk", "atclk"; 1389 1390 in-ports { 1391 port { 1392 funnel_in2_in_modem_etm: endpoint { 1393 remote-endpoint = 1394 <&modem_etm_out_funnel_in2>; 1395 }; 1396 }; 1397 }; 1398 1399 out-ports { 1400 port { 1401 funnel2_out: endpoint { 1402 remote-endpoint = 1403 <&merge_funnel_in2>; 1404 }; 1405 }; 1406 }; 1407 }; 1408 1409 funnel@3025000 { 1410 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1411 reg = <0x3025000 0x1000>; 1412 1413 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1414 clock-names = "apb_pclk", "atclk"; 1415 1416 in-ports { 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 1420 port@0 { 1421 reg = <0>; 1422 merge_funnel_in0: endpoint { 1423 remote-endpoint = 1424 <&funnel0_out>; 1425 }; 1426 }; 1427 1428 port@1 { 1429 reg = <1>; 1430 merge_funnel_in1: endpoint { 1431 remote-endpoint = 1432 <&funnel1_out>; 1433 }; 1434 }; 1435 1436 port@2 { 1437 reg = <2>; 1438 merge_funnel_in2: endpoint { 1439 remote-endpoint = 1440 <&funnel2_out>; 1441 }; 1442 }; 1443 }; 1444 1445 out-ports { 1446 port { 1447 merge_funnel_out: endpoint { 1448 remote-endpoint = 1449 <&etf_in>; 1450 }; 1451 }; 1452 }; 1453 }; 1454 1455 replicator@3026000 { 1456 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1457 reg = <0x3026000 0x1000>; 1458 1459 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1460 clock-names = "apb_pclk", "atclk"; 1461 1462 in-ports { 1463 port { 1464 replicator_in: endpoint { 1465 remote-endpoint = 1466 <&etf_out>; 1467 }; 1468 }; 1469 }; 1470 1471 out-ports { 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 1475 port@0 { 1476 reg = <0>; 1477 replicator_out0: endpoint { 1478 remote-endpoint = 1479 <&etr_in>; 1480 }; 1481 }; 1482 1483 port@1 { 1484 reg = <1>; 1485 replicator_out1: endpoint { 1486 remote-endpoint = 1487 <&tpiu_in>; 1488 }; 1489 }; 1490 }; 1491 }; 1492 1493 etf@3027000 { 1494 compatible = "arm,coresight-tmc", "arm,primecell"; 1495 reg = <0x3027000 0x1000>; 1496 1497 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1498 clock-names = "apb_pclk", "atclk"; 1499 1500 in-ports { 1501 port { 1502 etf_in: endpoint { 1503 remote-endpoint = 1504 <&merge_funnel_out>; 1505 }; 1506 }; 1507 }; 1508 1509 out-ports { 1510 port { 1511 etf_out: endpoint { 1512 remote-endpoint = 1513 <&replicator_in>; 1514 }; 1515 }; 1516 }; 1517 }; 1518 1519 etr@3028000 { 1520 compatible = "arm,coresight-tmc", "arm,primecell"; 1521 reg = <0x3028000 0x1000>; 1522 1523 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1524 clock-names = "apb_pclk", "atclk"; 1525 arm,scatter-gather; 1526 1527 in-ports { 1528 port { 1529 etr_in: endpoint { 1530 remote-endpoint = 1531 <&replicator_out0>; 1532 }; 1533 }; 1534 }; 1535 }; 1536 1537 debug@3810000 { 1538 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1539 reg = <0x3810000 0x1000>; 1540 1541 clocks = <&rpmcc RPM_QDSS_CLK>; 1542 clock-names = "apb_pclk"; 1543 1544 cpu = <&CPU0>; 1545 }; 1546 1547 etm@3840000 { 1548 compatible = "arm,coresight-etm4x", "arm,primecell"; 1549 reg = <0x3840000 0x1000>; 1550 1551 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1552 clock-names = "apb_pclk", "atclk"; 1553 1554 cpu = <&CPU0>; 1555 1556 out-ports { 1557 port { 1558 etm0_out: endpoint { 1559 remote-endpoint = 1560 <&apss_funnel0_in0>; 1561 }; 1562 }; 1563 }; 1564 }; 1565 1566 debug@3910000 { 1567 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1568 reg = <0x3910000 0x1000>; 1569 1570 clocks = <&rpmcc RPM_QDSS_CLK>; 1571 clock-names = "apb_pclk"; 1572 1573 cpu = <&CPU1>; 1574 }; 1575 1576 etm@3940000 { 1577 compatible = "arm,coresight-etm4x", "arm,primecell"; 1578 reg = <0x3940000 0x1000>; 1579 1580 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1581 clock-names = "apb_pclk", "atclk"; 1582 1583 cpu = <&CPU1>; 1584 1585 out-ports { 1586 port { 1587 etm1_out: endpoint { 1588 remote-endpoint = 1589 <&apss_funnel0_in1>; 1590 }; 1591 }; 1592 }; 1593 }; 1594 1595 funnel@39b0000 { /* APSS Funnel 0 */ 1596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1597 reg = <0x39b0000 0x1000>; 1598 1599 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1600 clock-names = "apb_pclk", "atclk"; 1601 1602 in-ports { 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 1606 port@0 { 1607 reg = <0>; 1608 apss_funnel0_in0: endpoint { 1609 remote-endpoint = <&etm0_out>; 1610 }; 1611 }; 1612 1613 port@1 { 1614 reg = <1>; 1615 apss_funnel0_in1: endpoint { 1616 remote-endpoint = <&etm1_out>; 1617 }; 1618 }; 1619 }; 1620 1621 out-ports { 1622 port { 1623 apss_funnel0_out: endpoint { 1624 remote-endpoint = 1625 <&apss_merge_funnel_in0>; 1626 }; 1627 }; 1628 }; 1629 }; 1630 1631 debug@3a10000 { 1632 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1633 reg = <0x3a10000 0x1000>; 1634 1635 clocks = <&rpmcc RPM_QDSS_CLK>; 1636 clock-names = "apb_pclk"; 1637 1638 cpu = <&CPU2>; 1639 }; 1640 1641 etm@3a40000 { 1642 compatible = "arm,coresight-etm4x", "arm,primecell"; 1643 reg = <0x3a40000 0x1000>; 1644 1645 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1646 clock-names = "apb_pclk", "atclk"; 1647 1648 cpu = <&CPU2>; 1649 1650 out-ports { 1651 port { 1652 etm2_out: endpoint { 1653 remote-endpoint = 1654 <&apss_funnel1_in0>; 1655 }; 1656 }; 1657 }; 1658 }; 1659 1660 debug@3b10000 { 1661 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1662 reg = <0x3b10000 0x1000>; 1663 1664 clocks = <&rpmcc RPM_QDSS_CLK>; 1665 clock-names = "apb_pclk"; 1666 1667 cpu = <&CPU3>; 1668 }; 1669 1670 etm@3b40000 { 1671 compatible = "arm,coresight-etm4x", "arm,primecell"; 1672 reg = <0x3b40000 0x1000>; 1673 1674 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1675 clock-names = "apb_pclk", "atclk"; 1676 1677 cpu = <&CPU3>; 1678 1679 out-ports { 1680 port { 1681 etm3_out: endpoint { 1682 remote-endpoint = 1683 <&apss_funnel1_in1>; 1684 }; 1685 }; 1686 }; 1687 }; 1688 1689 funnel@3bb0000 { /* APSS Funnel 1 */ 1690 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1691 reg = <0x3bb0000 0x1000>; 1692 1693 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1694 clock-names = "apb_pclk", "atclk"; 1695 1696 in-ports { 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 1700 port@0 { 1701 reg = <0>; 1702 apss_funnel1_in0: endpoint { 1703 remote-endpoint = <&etm2_out>; 1704 }; 1705 }; 1706 1707 port@1 { 1708 reg = <1>; 1709 apss_funnel1_in1: endpoint { 1710 remote-endpoint = <&etm3_out>; 1711 }; 1712 }; 1713 }; 1714 1715 out-ports { 1716 port { 1717 apss_funnel1_out: endpoint { 1718 remote-endpoint = 1719 <&apss_merge_funnel_in1>; 1720 }; 1721 }; 1722 }; 1723 }; 1724 1725 funnel@3bc0000 { 1726 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1727 reg = <0x3bc0000 0x1000>; 1728 1729 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1730 clock-names = "apb_pclk", "atclk"; 1731 1732 in-ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 port@0 { 1737 reg = <0>; 1738 apss_merge_funnel_in0: endpoint { 1739 remote-endpoint = 1740 <&apss_funnel0_out>; 1741 }; 1742 }; 1743 1744 port@1 { 1745 reg = <1>; 1746 apss_merge_funnel_in1: endpoint { 1747 remote-endpoint = 1748 <&apss_funnel1_out>; 1749 }; 1750 }; 1751 }; 1752 1753 out-ports { 1754 port { 1755 apss_merge_funnel_out: endpoint { 1756 remote-endpoint = 1757 <&funnel1_in>; 1758 }; 1759 }; 1760 }; 1761 }; 1762 kryocc: clock-controller@6400000 { 1763 compatible = "qcom,apcc-msm8996"; 1764 reg = <0x06400000 0x90000>; 1765 #clock-cells = <1>; 1766 }; 1767 1768 usb3: usb@6af8800 { 1769 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1770 reg = <0x06af8800 0x400>; 1771 #address-cells = <1>; 1772 #size-cells = <1>; 1773 ranges; 1774 1775 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 1776 <&gcc GCC_USB30_MASTER_CLK>, 1777 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1778 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1779 <&gcc GCC_USB30_SLEEP_CLK>, 1780 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1781 1782 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1783 <&gcc GCC_USB30_MASTER_CLK>; 1784 assigned-clock-rates = <19200000>, <120000000>; 1785 1786 power-domains = <&gcc USB30_GDSC>; 1787 status = "disabled"; 1788 1789 dwc3@6a00000 { 1790 compatible = "snps,dwc3"; 1791 reg = <0x06a00000 0xcc00>; 1792 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 1793 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 1794 phy-names = "usb2-phy", "usb3-phy"; 1795 snps,hird-threshold = /bits/ 8 <0>; 1796 snps,dis_u2_susphy_quirk; 1797 snps,dis_enblslpm_quirk; 1798 snps,is-utmi-l1-suspend; 1799 tx-fifo-resize; 1800 }; 1801 }; 1802 1803 usb3phy: phy@7410000 { 1804 compatible = "qcom,msm8996-qmp-usb3-phy"; 1805 reg = <0x07410000 0x1c4>; 1806 #clock-cells = <1>; 1807 #address-cells = <1>; 1808 #size-cells = <1>; 1809 ranges; 1810 1811 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1812 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1813 <&gcc GCC_USB3_CLKREF_CLK>; 1814 clock-names = "aux", "cfg_ahb", "ref"; 1815 1816 resets = <&gcc GCC_USB3_PHY_BCR>, 1817 <&gcc GCC_USB3PHY_PHY_BCR>; 1818 reset-names = "phy", "common"; 1819 status = "disabled"; 1820 1821 ssusb_phy_0: lane@7410200 { 1822 reg = <0x07410200 0x200>, 1823 <0x07410400 0x130>, 1824 <0x07410600 0x1a8>; 1825 #phy-cells = <0>; 1826 1827 clock-output-names = "usb3_phy_pipe_clk_src"; 1828 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1829 clock-names = "pipe0"; 1830 }; 1831 }; 1832 1833 hsusb_phy1: phy@7411000 { 1834 compatible = "qcom,msm8996-qusb2-phy"; 1835 reg = <0x07411000 0x180>; 1836 #phy-cells = <0>; 1837 1838 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1839 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1840 clock-names = "cfg_ahb", "ref"; 1841 1842 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1843 nvmem-cells = <&qusb2p_hstx_trim>; 1844 status = "disabled"; 1845 }; 1846 1847 hsusb_phy2: phy@7412000 { 1848 compatible = "qcom,msm8996-qusb2-phy"; 1849 reg = <0x07412000 0x180>; 1850 #phy-cells = <0>; 1851 1852 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1853 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 1854 clock-names = "cfg_ahb", "ref"; 1855 1856 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1857 nvmem-cells = <&qusb2s_hstx_trim>; 1858 status = "disabled"; 1859 }; 1860 1861 sdhc2: sdhci@74a4900 { 1862 status = "disabled"; 1863 compatible = "qcom,sdhci-msm-v4"; 1864 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 1865 reg-names = "hc_mem", "core_mem"; 1866 1867 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, 1868 <0 221 IRQ_TYPE_LEVEL_HIGH>; 1869 interrupt-names = "hc_irq", "pwr_irq"; 1870 1871 clock-names = "iface", "core", "xo"; 1872 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1873 <&gcc GCC_SDCC2_APPS_CLK>, 1874 <&xo_board>; 1875 bus-width = <4>; 1876 }; 1877 1878 blsp1_uart1: serial@7570000 { 1879 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1880 reg = <0x07570000 0x1000>; 1881 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1882 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1883 <&gcc GCC_BLSP1_AHB_CLK>; 1884 clock-names = "core", "iface"; 1885 status = "disabled"; 1886 }; 1887 1888 blsp1_spi0: spi@7575000 { 1889 compatible = "qcom,spi-qup-v2.2.1"; 1890 reg = <0x07575000 0x600>; 1891 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1892 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1893 <&gcc GCC_BLSP1_AHB_CLK>; 1894 clock-names = "core", "iface"; 1895 pinctrl-names = "default", "sleep"; 1896 pinctrl-0 = <&blsp1_spi0_default>; 1897 pinctrl-1 = <&blsp1_spi0_sleep>; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 status = "disabled"; 1901 }; 1902 1903 blsp1_i2c2: i2c@7577000 { 1904 compatible = "qcom,i2c-qup-v2.2.1"; 1905 reg = <0x07577000 0x1000>; 1906 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1908 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 1909 clock-names = "iface", "core"; 1910 pinctrl-names = "default", "sleep"; 1911 pinctrl-0 = <&blsp1_i2c2_default>; 1912 pinctrl-1 = <&blsp1_i2c2_sleep>; 1913 #address-cells = <1>; 1914 #size-cells = <0>; 1915 status = "disabled"; 1916 }; 1917 1918 blsp2_uart1: serial@75b0000 { 1919 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1920 reg = <0x075b0000 0x1000>; 1921 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1922 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1923 <&gcc GCC_BLSP2_AHB_CLK>; 1924 clock-names = "core", "iface"; 1925 status = "disabled"; 1926 }; 1927 1928 blsp2_uart2: serial@75b1000 { 1929 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1930 reg = <0x075b1000 0x1000>; 1931 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1932 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 1933 <&gcc GCC_BLSP2_AHB_CLK>; 1934 clock-names = "core", "iface"; 1935 status = "disabled"; 1936 }; 1937 1938 blsp2_i2c0: i2c@75b5000 { 1939 compatible = "qcom,i2c-qup-v2.2.1"; 1940 reg = <0x075b5000 0x1000>; 1941 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1943 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 1944 clock-names = "iface", "core"; 1945 pinctrl-names = "default", "sleep"; 1946 pinctrl-0 = <&blsp2_i2c0_default>; 1947 pinctrl-1 = <&blsp2_i2c0_sleep>; 1948 #address-cells = <1>; 1949 #size-cells = <0>; 1950 status = "disabled"; 1951 }; 1952 1953 blsp2_i2c1: i2c@75b6000 { 1954 compatible = "qcom,i2c-qup-v2.2.1"; 1955 reg = <0x075b6000 0x1000>; 1956 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1957 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1958 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 1959 clock-names = "iface", "core"; 1960 pinctrl-names = "default", "sleep"; 1961 pinctrl-0 = <&blsp2_i2c1_default>; 1962 pinctrl-1 = <&blsp2_i2c1_sleep>; 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 status = "disabled"; 1966 }; 1967 1968 blsp2_spi5: spi@75ba000{ 1969 compatible = "qcom,spi-qup-v2.2.1"; 1970 reg = <0x075ba000 0x600>; 1971 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1972 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 1973 <&gcc GCC_BLSP2_AHB_CLK>; 1974 clock-names = "core", "iface"; 1975 pinctrl-names = "default", "sleep"; 1976 pinctrl-0 = <&blsp2_spi5_default>; 1977 pinctrl-1 = <&blsp2_spi5_sleep>; 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 status = "disabled"; 1981 }; 1982 1983 usb2: usb@76f8800 { 1984 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1985 reg = <0x076f8800 0x400>; 1986 #address-cells = <1>; 1987 #size-cells = <1>; 1988 ranges; 1989 1990 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1991 interrupt-names = "hs_phy_irq"; 1992 1993 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 1994 <&gcc GCC_USB20_MASTER_CLK>, 1995 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1996 <&gcc GCC_USB20_SLEEP_CLK>, 1997 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1998 1999 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 2000 <&gcc GCC_USB20_MASTER_CLK>; 2001 assigned-clock-rates = <19200000>, <60000000>; 2002 2003 power-domains = <&gcc USB30_GDSC>; 2004 status = "disabled"; 2005 2006 dwc3@7600000 { 2007 compatible = "snps,dwc3"; 2008 reg = <0x07600000 0xcc00>; 2009 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 2010 phys = <&hsusb_phy2>; 2011 phy-names = "usb2-phy"; 2012 snps,dis_u2_susphy_quirk; 2013 snps,dis_enblslpm_quirk; 2014 }; 2015 }; 2016 2017 slimbam: dma@9184000 { 2018 compatible = "qcom,bam-v1.7.0"; 2019 qcom,controlled-remotely; 2020 reg = <0x09184000 0x32000>; 2021 num-channels = <31>; 2022 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 2023 #dma-cells = <1>; 2024 qcom,ee = <1>; 2025 qcom,num-ees = <2>; 2026 }; 2027 2028 slim_msm: slim@91c0000 { 2029 compatible = "qcom,slim-ngd-v1.5.0"; 2030 reg = <0x091c0000 0x2C000>; 2031 reg-names = "ctrl"; 2032 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 2033 dmas = <&slimbam 3>, <&slimbam 4>, 2034 <&slimbam 5>, <&slimbam 6>; 2035 dma-names = "rx", "tx", "tx2", "rx2"; 2036 #address-cells = <1>; 2037 #size-cells = <0>; 2038 ngd@1 { 2039 reg = <1>; 2040 #address-cells = <1>; 2041 #size-cells = <1>; 2042 2043 tasha_ifd: tas-ifd { 2044 compatible = "slim217,1a0"; 2045 reg = <0 0>; 2046 }; 2047 2048 wcd9335: codec@1{ 2049 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 2050 pinctrl-names = "default"; 2051 2052 compatible = "slim217,1a0"; 2053 reg = <1 0>; 2054 2055 interrupt-parent = <&msmgpio>; 2056 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 2057 <53 IRQ_TYPE_LEVEL_HIGH>; 2058 interrupt-names = "intr1", "intr2"; 2059 interrupt-controller; 2060 #interrupt-cells = <1>; 2061 reset-gpios = <&msmgpio 64 0>; 2062 2063 slim-ifc-dev = <&tasha_ifd>; 2064 2065 #sound-dai-cells = <1>; 2066 }; 2067 }; 2068 }; 2069 2070 adsp_pil: remoteproc@9300000 { 2071 compatible = "qcom,msm8996-adsp-pil"; 2072 reg = <0x09300000 0x80000>; 2073 2074 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 2075 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2076 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2077 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2078 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2079 interrupt-names = "wdog", "fatal", "ready", 2080 "handover", "stop-ack"; 2081 2082 clocks = <&xo_board>; 2083 clock-names = "xo"; 2084 2085 memory-region = <&adsp_region>; 2086 2087 qcom,smem-states = <&smp2p_adsp_out 0>; 2088 qcom,smem-state-names = "stop"; 2089 2090 smd-edge { 2091 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2092 2093 label = "lpass"; 2094 mboxes = <&apcs_glb 8>; 2095 qcom,smd-edge = <1>; 2096 qcom,remote-pid = <2>; 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 apr { 2100 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 2101 compatible = "qcom,apr-v2"; 2102 qcom,smd-channels = "apr_audio_svc"; 2103 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 q6core { 2108 reg = <APR_SVC_ADSP_CORE>; 2109 compatible = "qcom,q6core"; 2110 }; 2111 2112 q6afe: q6afe { 2113 compatible = "qcom,q6afe"; 2114 reg = <APR_SVC_AFE>; 2115 q6afedai: dais { 2116 compatible = "qcom,q6afe-dais"; 2117 #address-cells = <1>; 2118 #size-cells = <0>; 2119 #sound-dai-cells = <1>; 2120 hdmi@1 { 2121 reg = <1>; 2122 }; 2123 }; 2124 }; 2125 2126 q6asm: q6asm { 2127 compatible = "qcom,q6asm"; 2128 reg = <APR_SVC_ASM>; 2129 q6asmdai: dais { 2130 compatible = "qcom,q6asm-dais"; 2131 #address-cells = <1>; 2132 #size-cells = <0>; 2133 #sound-dai-cells = <1>; 2134 iommus = <&lpass_q6_smmu 1>; 2135 }; 2136 }; 2137 2138 q6adm: q6adm { 2139 compatible = "qcom,q6adm"; 2140 reg = <APR_SVC_ADM>; 2141 q6routing: routing { 2142 compatible = "qcom,q6adm-routing"; 2143 #sound-dai-cells = <0>; 2144 }; 2145 }; 2146 }; 2147 2148 }; 2149 }; 2150 2151 apcs_glb: mailbox@9820000 { 2152 compatible = "qcom,msm8996-apcs-hmss-global"; 2153 reg = <0x09820000 0x1000>; 2154 2155 #mbox-cells = <1>; 2156 }; 2157 2158 timer@9840000 { 2159 #address-cells = <1>; 2160 #size-cells = <1>; 2161 ranges; 2162 compatible = "arm,armv7-timer-mem"; 2163 reg = <0x09840000 0x1000>; 2164 clock-frequency = <19200000>; 2165 2166 frame@9850000 { 2167 frame-number = <0>; 2168 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2170 reg = <0x09850000 0x1000>, 2171 <0x09860000 0x1000>; 2172 }; 2173 2174 frame@9870000 { 2175 frame-number = <1>; 2176 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2177 reg = <0x09870000 0x1000>; 2178 status = "disabled"; 2179 }; 2180 2181 frame@9880000 { 2182 frame-number = <2>; 2183 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2184 reg = <0x09880000 0x1000>; 2185 status = "disabled"; 2186 }; 2187 2188 frame@9890000 { 2189 frame-number = <3>; 2190 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2191 reg = <0x09890000 0x1000>; 2192 status = "disabled"; 2193 }; 2194 2195 frame@98a0000 { 2196 frame-number = <4>; 2197 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2198 reg = <0x098a0000 0x1000>; 2199 status = "disabled"; 2200 }; 2201 2202 frame@98b0000 { 2203 frame-number = <5>; 2204 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2205 reg = <0x098b0000 0x1000>; 2206 status = "disabled"; 2207 }; 2208 2209 frame@98c0000 { 2210 frame-number = <6>; 2211 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2212 reg = <0x098c0000 0x1000>; 2213 status = "disabled"; 2214 }; 2215 }; 2216 2217 saw3: syscon@9a10000 { 2218 compatible = "syscon"; 2219 reg = <0x09a10000 0x1000>; 2220 }; 2221 2222 intc: interrupt-controller@9bc0000 { 2223 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 2224 #interrupt-cells = <3>; 2225 interrupt-controller; 2226 #redistributor-regions = <1>; 2227 redistributor-stride = <0x0 0x40000>; 2228 reg = <0x09bc0000 0x10000>, 2229 <0x09c00000 0x100000>; 2230 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2231 }; 2232 }; 2233 2234 sound: sound { 2235 }; 2236 2237 thermal-zones { 2238 cpu0-thermal { 2239 polling-delay-passive = <250>; 2240 polling-delay = <1000>; 2241 2242 thermal-sensors = <&tsens0 3>; 2243 2244 trips { 2245 cpu0_alert0: trip-point0 { 2246 temperature = <75000>; 2247 hysteresis = <2000>; 2248 type = "passive"; 2249 }; 2250 2251 cpu0_crit: cpu_crit { 2252 temperature = <110000>; 2253 hysteresis = <2000>; 2254 type = "critical"; 2255 }; 2256 }; 2257 }; 2258 2259 cpu1-thermal { 2260 polling-delay-passive = <250>; 2261 polling-delay = <1000>; 2262 2263 thermal-sensors = <&tsens0 5>; 2264 2265 trips { 2266 cpu1_alert0: trip-point0 { 2267 temperature = <75000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 2272 cpu1_crit: cpu_crit { 2273 temperature = <110000>; 2274 hysteresis = <2000>; 2275 type = "critical"; 2276 }; 2277 }; 2278 }; 2279 2280 cpu2-thermal { 2281 polling-delay-passive = <250>; 2282 polling-delay = <1000>; 2283 2284 thermal-sensors = <&tsens0 8>; 2285 2286 trips { 2287 cpu2_alert0: trip-point0 { 2288 temperature = <75000>; 2289 hysteresis = <2000>; 2290 type = "passive"; 2291 }; 2292 2293 cpu2_crit: cpu_crit { 2294 temperature = <110000>; 2295 hysteresis = <2000>; 2296 type = "critical"; 2297 }; 2298 }; 2299 }; 2300 2301 cpu3-thermal { 2302 polling-delay-passive = <250>; 2303 polling-delay = <1000>; 2304 2305 thermal-sensors = <&tsens0 10>; 2306 2307 trips { 2308 cpu3_alert0: trip-point0 { 2309 temperature = <75000>; 2310 hysteresis = <2000>; 2311 type = "passive"; 2312 }; 2313 2314 cpu3_crit: cpu_crit { 2315 temperature = <110000>; 2316 hysteresis = <2000>; 2317 type = "critical"; 2318 }; 2319 }; 2320 }; 2321 2322 gpu-thermal-top { 2323 polling-delay-passive = <250>; 2324 polling-delay = <1000>; 2325 2326 thermal-sensors = <&tsens1 6>; 2327 2328 trips { 2329 gpu1_alert0: trip-point0 { 2330 temperature = <90000>; 2331 hysteresis = <2000>; 2332 type = "hot"; 2333 }; 2334 }; 2335 }; 2336 2337 gpu-thermal-bottom { 2338 polling-delay-passive = <250>; 2339 polling-delay = <1000>; 2340 2341 thermal-sensors = <&tsens1 7>; 2342 2343 trips { 2344 gpu2_alert0: trip-point0 { 2345 temperature = <90000>; 2346 hysteresis = <2000>; 2347 type = "hot"; 2348 }; 2349 }; 2350 }; 2351 2352 m4m-thermal { 2353 polling-delay-passive = <250>; 2354 polling-delay = <1000>; 2355 2356 thermal-sensors = <&tsens0 1>; 2357 2358 trips { 2359 m4m_alert0: trip-point0 { 2360 temperature = <90000>; 2361 hysteresis = <2000>; 2362 type = "hot"; 2363 }; 2364 }; 2365 }; 2366 2367 l3-or-venus-thermal { 2368 polling-delay-passive = <250>; 2369 polling-delay = <1000>; 2370 2371 thermal-sensors = <&tsens0 2>; 2372 2373 trips { 2374 l3_or_venus_alert0: trip-point0 { 2375 temperature = <90000>; 2376 hysteresis = <2000>; 2377 type = "hot"; 2378 }; 2379 }; 2380 }; 2381 2382 cluster0-l2-thermal { 2383 polling-delay-passive = <250>; 2384 polling-delay = <1000>; 2385 2386 thermal-sensors = <&tsens0 7>; 2387 2388 trips { 2389 cluster0_l2_alert0: trip-point0 { 2390 temperature = <90000>; 2391 hysteresis = <2000>; 2392 type = "hot"; 2393 }; 2394 }; 2395 }; 2396 2397 cluster1-l2-thermal { 2398 polling-delay-passive = <250>; 2399 polling-delay = <1000>; 2400 2401 thermal-sensors = <&tsens0 12>; 2402 2403 trips { 2404 cluster1_l2_alert0: trip-point0 { 2405 temperature = <90000>; 2406 hysteresis = <2000>; 2407 type = "hot"; 2408 }; 2409 }; 2410 }; 2411 2412 camera-thermal { 2413 polling-delay-passive = <250>; 2414 polling-delay = <1000>; 2415 2416 thermal-sensors = <&tsens1 1>; 2417 2418 trips { 2419 camera_alert0: trip-point0 { 2420 temperature = <90000>; 2421 hysteresis = <2000>; 2422 type = "hot"; 2423 }; 2424 }; 2425 }; 2426 2427 q6-dsp-thermal { 2428 polling-delay-passive = <250>; 2429 polling-delay = <1000>; 2430 2431 thermal-sensors = <&tsens1 2>; 2432 2433 trips { 2434 q6_dsp_alert0: trip-point0 { 2435 temperature = <90000>; 2436 hysteresis = <2000>; 2437 type = "hot"; 2438 }; 2439 }; 2440 }; 2441 2442 mem-thermal { 2443 polling-delay-passive = <250>; 2444 polling-delay = <1000>; 2445 2446 thermal-sensors = <&tsens1 3>; 2447 2448 trips { 2449 mem_alert0: trip-point0 { 2450 temperature = <90000>; 2451 hysteresis = <2000>; 2452 type = "hot"; 2453 }; 2454 }; 2455 }; 2456 2457 modemtx-thermal { 2458 polling-delay-passive = <250>; 2459 polling-delay = <1000>; 2460 2461 thermal-sensors = <&tsens1 4>; 2462 2463 trips { 2464 modemtx_alert0: trip-point0 { 2465 temperature = <90000>; 2466 hysteresis = <2000>; 2467 type = "hot"; 2468 }; 2469 }; 2470 }; 2471 }; 2472 2473 timer { 2474 compatible = "arm,armv8-timer"; 2475 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2476 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2477 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2478 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2479 }; 2480}; 2481#include "msm8996-pins.dtsi" 2482