1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774a1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c_dvfs; 29 }; 30 31 /* 32 * The external audio clocks are configured as 0 Hz fixed frequency 33 * clocks by default. 34 * Boards that provide audio clocks should override them. 35 */ 36 audio_clk_a: audio_clk_a { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 audio_clk_b: audio_clk_b { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 audio_clk_c: audio_clk_c { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 }; 53 54 /* External CAN clock - to be overridden by boards that provide it */ 55 can_clk: can { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 cluster0_opp: opp_table0 { 62 compatible = "operating-points-v2"; 63 opp-shared; 64 65 opp-500000000 { 66 opp-hz = /bits/ 64 <500000000>; 67 opp-microvolt = <820000>; 68 clock-latency-ns = <300000>; 69 }; 70 opp-1000000000 { 71 opp-hz = /bits/ 64 <1000000000>; 72 opp-microvolt = <820000>; 73 clock-latency-ns = <300000>; 74 }; 75 opp-1500000000 { 76 opp-hz = /bits/ 64 <1500000000>; 77 opp-microvolt = <820000>; 78 clock-latency-ns = <300000>; 79 opp-suspend; 80 }; 81 }; 82 83 cluster1_opp: opp_table1 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-800000000 { 88 opp-hz = /bits/ 64 <800000000>; 89 opp-microvolt = <820000>; 90 clock-latency-ns = <300000>; 91 }; 92 opp-1000000000 { 93 opp-hz = /bits/ 64 <1000000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 }; 103 104 cpus { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 cpu-map { 109 cluster0 { 110 core0 { 111 cpu = <&a57_0>; 112 }; 113 core1 { 114 cpu = <&a57_1>; 115 }; 116 }; 117 118 cluster1 { 119 core0 { 120 cpu = <&a53_0>; 121 }; 122 core1 { 123 cpu = <&a53_1>; 124 }; 125 core2 { 126 cpu = <&a53_2>; 127 }; 128 core3 { 129 cpu = <&a53_3>; 130 }; 131 }; 132 }; 133 134 a57_0: cpu@0 { 135 compatible = "arm,cortex-a57"; 136 reg = <0x0>; 137 device_type = "cpu"; 138 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 139 next-level-cache = <&L2_CA57>; 140 enable-method = "psci"; 141 dynamic-power-coefficient = <854>; 142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 143 operating-points-v2 = <&cluster0_opp>; 144 capacity-dmips-mhz = <1024>; 145 #cooling-cells = <2>; 146 }; 147 148 a57_1: cpu@1 { 149 compatible = "arm,cortex-a57"; 150 reg = <0x1>; 151 device_type = "cpu"; 152 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 153 next-level-cache = <&L2_CA57>; 154 enable-method = "psci"; 155 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 156 operating-points-v2 = <&cluster0_opp>; 157 capacity-dmips-mhz = <1024>; 158 #cooling-cells = <2>; 159 }; 160 161 a53_0: cpu@100 { 162 compatible = "arm,cortex-a53"; 163 reg = <0x100>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 166 next-level-cache = <&L2_CA53>; 167 enable-method = "psci"; 168 #cooling-cells = <2>; 169 dynamic-power-coefficient = <277>; 170 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 171 operating-points-v2 = <&cluster1_opp>; 172 capacity-dmips-mhz = <560>; 173 }; 174 175 a53_1: cpu@101 { 176 compatible = "arm,cortex-a53"; 177 reg = <0x101>; 178 device_type = "cpu"; 179 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 180 next-level-cache = <&L2_CA53>; 181 enable-method = "psci"; 182 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 183 operating-points-v2 = <&cluster1_opp>; 184 capacity-dmips-mhz = <560>; 185 }; 186 187 a53_2: cpu@102 { 188 compatible = "arm,cortex-a53"; 189 reg = <0x102>; 190 device_type = "cpu"; 191 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 192 next-level-cache = <&L2_CA53>; 193 enable-method = "psci"; 194 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 195 operating-points-v2 = <&cluster1_opp>; 196 capacity-dmips-mhz = <560>; 197 }; 198 199 a53_3: cpu@103 { 200 compatible = "arm,cortex-a53"; 201 reg = <0x103>; 202 device_type = "cpu"; 203 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 204 next-level-cache = <&L2_CA53>; 205 enable-method = "psci"; 206 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 207 operating-points-v2 = <&cluster1_opp>; 208 capacity-dmips-mhz = <560>; 209 }; 210 211 L2_CA57: cache-controller-0 { 212 compatible = "cache"; 213 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 214 cache-unified; 215 cache-level = <2>; 216 }; 217 218 L2_CA53: cache-controller-1 { 219 compatible = "cache"; 220 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 221 cache-unified; 222 cache-level = <2>; 223 }; 224 }; 225 226 extal_clk: extal { 227 compatible = "fixed-clock"; 228 #clock-cells = <0>; 229 /* This value must be overridden by the board */ 230 clock-frequency = <0>; 231 }; 232 233 extalr_clk: extalr { 234 compatible = "fixed-clock"; 235 #clock-cells = <0>; 236 /* This value must be overridden by the board */ 237 clock-frequency = <0>; 238 }; 239 240 /* External PCIe clock - can be overridden by the board */ 241 pcie_bus_clk: pcie_bus { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <0>; 245 }; 246 247 pmu_a53 { 248 compatible = "arm,cortex-a53-pmu"; 249 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 250 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 251 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 252 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 254 }; 255 256 pmu_a57 { 257 compatible = "arm,cortex-a57-pmu"; 258 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 259 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-affinity = <&a57_0>, <&a57_1>; 261 }; 262 263 psci { 264 compatible = "arm,psci-1.0", "arm,psci-0.2"; 265 method = "smc"; 266 }; 267 268 /* External SCIF clock - to be overridden by boards that provide it */ 269 scif_clk: scif { 270 compatible = "fixed-clock"; 271 #clock-cells = <0>; 272 clock-frequency = <0>; 273 }; 274 275 soc { 276 compatible = "simple-bus"; 277 interrupt-parent = <&gic>; 278 #address-cells = <2>; 279 #size-cells = <2>; 280 ranges; 281 282 rwdt: watchdog@e6020000 { 283 compatible = "renesas,r8a774a1-wdt", 284 "renesas,rcar-gen3-wdt"; 285 reg = <0 0xe6020000 0 0x0c>; 286 clocks = <&cpg CPG_MOD 402>; 287 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 288 resets = <&cpg 402>; 289 status = "disabled"; 290 }; 291 292 gpio0: gpio@e6050000 { 293 compatible = "renesas,gpio-r8a774a1", 294 "renesas,rcar-gen3-gpio"; 295 reg = <0 0xe6050000 0 0x50>; 296 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 297 #gpio-cells = <2>; 298 gpio-controller; 299 gpio-ranges = <&pfc 0 0 16>; 300 #interrupt-cells = <2>; 301 interrupt-controller; 302 clocks = <&cpg CPG_MOD 912>; 303 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 304 resets = <&cpg 912>; 305 }; 306 307 gpio1: gpio@e6051000 { 308 compatible = "renesas,gpio-r8a774a1", 309 "renesas,rcar-gen3-gpio"; 310 reg = <0 0xe6051000 0 0x50>; 311 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 312 #gpio-cells = <2>; 313 gpio-controller; 314 gpio-ranges = <&pfc 0 32 29>; 315 #interrupt-cells = <2>; 316 interrupt-controller; 317 clocks = <&cpg CPG_MOD 911>; 318 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 319 resets = <&cpg 911>; 320 }; 321 322 gpio2: gpio@e6052000 { 323 compatible = "renesas,gpio-r8a774a1", 324 "renesas,rcar-gen3-gpio"; 325 reg = <0 0xe6052000 0 0x50>; 326 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 327 #gpio-cells = <2>; 328 gpio-controller; 329 gpio-ranges = <&pfc 0 64 15>; 330 #interrupt-cells = <2>; 331 interrupt-controller; 332 clocks = <&cpg CPG_MOD 910>; 333 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 334 resets = <&cpg 910>; 335 }; 336 337 gpio3: gpio@e6053000 { 338 compatible = "renesas,gpio-r8a774a1", 339 "renesas,rcar-gen3-gpio"; 340 reg = <0 0xe6053000 0 0x50>; 341 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 342 #gpio-cells = <2>; 343 gpio-controller; 344 gpio-ranges = <&pfc 0 96 16>; 345 #interrupt-cells = <2>; 346 interrupt-controller; 347 clocks = <&cpg CPG_MOD 909>; 348 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 349 resets = <&cpg 909>; 350 }; 351 352 gpio4: gpio@e6054000 { 353 compatible = "renesas,gpio-r8a774a1", 354 "renesas,rcar-gen3-gpio"; 355 reg = <0 0xe6054000 0 0x50>; 356 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 357 #gpio-cells = <2>; 358 gpio-controller; 359 gpio-ranges = <&pfc 0 128 18>; 360 #interrupt-cells = <2>; 361 interrupt-controller; 362 clocks = <&cpg CPG_MOD 908>; 363 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 364 resets = <&cpg 908>; 365 }; 366 367 gpio5: gpio@e6055000 { 368 compatible = "renesas,gpio-r8a774a1", 369 "renesas,rcar-gen3-gpio"; 370 reg = <0 0xe6055000 0 0x50>; 371 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 372 #gpio-cells = <2>; 373 gpio-controller; 374 gpio-ranges = <&pfc 0 160 26>; 375 #interrupt-cells = <2>; 376 interrupt-controller; 377 clocks = <&cpg CPG_MOD 907>; 378 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 379 resets = <&cpg 907>; 380 }; 381 382 gpio6: gpio@e6055400 { 383 compatible = "renesas,gpio-r8a774a1", 384 "renesas,rcar-gen3-gpio"; 385 reg = <0 0xe6055400 0 0x50>; 386 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 387 #gpio-cells = <2>; 388 gpio-controller; 389 gpio-ranges = <&pfc 0 192 32>; 390 #interrupt-cells = <2>; 391 interrupt-controller; 392 clocks = <&cpg CPG_MOD 906>; 393 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 394 resets = <&cpg 906>; 395 }; 396 397 gpio7: gpio@e6055800 { 398 compatible = "renesas,gpio-r8a774a1", 399 "renesas,rcar-gen3-gpio"; 400 reg = <0 0xe6055800 0 0x50>; 401 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 402 #gpio-cells = <2>; 403 gpio-controller; 404 gpio-ranges = <&pfc 0 224 4>; 405 #interrupt-cells = <2>; 406 interrupt-controller; 407 clocks = <&cpg CPG_MOD 905>; 408 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 409 resets = <&cpg 905>; 410 }; 411 412 pfc: pinctrl@e6060000 { 413 compatible = "renesas,pfc-r8a774a1"; 414 reg = <0 0xe6060000 0 0x50c>; 415 }; 416 417 cmt0: timer@e60f0000 { 418 compatible = "renesas,r8a774a1-cmt0", 419 "renesas,rcar-gen3-cmt0"; 420 reg = <0 0xe60f0000 0 0x1004>; 421 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&cpg CPG_MOD 303>; 424 clock-names = "fck"; 425 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 426 resets = <&cpg 303>; 427 status = "disabled"; 428 }; 429 430 cmt1: timer@e6130000 { 431 compatible = "renesas,r8a774a1-cmt1", 432 "renesas,rcar-gen3-cmt1"; 433 reg = <0 0xe6130000 0 0x1004>; 434 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&cpg CPG_MOD 302>; 443 clock-names = "fck"; 444 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 445 resets = <&cpg 302>; 446 status = "disabled"; 447 }; 448 449 cmt2: timer@e6140000 { 450 compatible = "renesas,r8a774a1-cmt1", 451 "renesas,rcar-gen3-cmt1"; 452 reg = <0 0xe6140000 0 0x1004>; 453 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&cpg CPG_MOD 301>; 462 clock-names = "fck"; 463 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 464 resets = <&cpg 301>; 465 status = "disabled"; 466 }; 467 468 cmt3: timer@e6148000 { 469 compatible = "renesas,r8a774a1-cmt1", 470 "renesas,rcar-gen3-cmt1"; 471 reg = <0 0xe6148000 0 0x1004>; 472 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cpg CPG_MOD 300>; 481 clock-names = "fck"; 482 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 483 resets = <&cpg 300>; 484 status = "disabled"; 485 }; 486 487 cpg: clock-controller@e6150000 { 488 compatible = "renesas,r8a774a1-cpg-mssr"; 489 reg = <0 0xe6150000 0 0x0bb0>; 490 clocks = <&extal_clk>, <&extalr_clk>; 491 clock-names = "extal", "extalr"; 492 #clock-cells = <2>; 493 #power-domain-cells = <0>; 494 #reset-cells = <1>; 495 }; 496 497 rst: reset-controller@e6160000 { 498 compatible = "renesas,r8a774a1-rst"; 499 reg = <0 0xe6160000 0 0x018c>; 500 }; 501 502 sysc: system-controller@e6180000 { 503 compatible = "renesas,r8a774a1-sysc"; 504 reg = <0 0xe6180000 0 0x0400>; 505 #power-domain-cells = <1>; 506 }; 507 508 tsc: thermal@e6198000 { 509 compatible = "renesas,r8a774a1-thermal"; 510 reg = <0 0xe6198000 0 0x100>, 511 <0 0xe61a0000 0 0x100>, 512 <0 0xe61a8000 0 0x100>; 513 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cpg CPG_MOD 522>; 517 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 518 resets = <&cpg 522>; 519 #thermal-sensor-cells = <1>; 520 }; 521 522 intc_ex: interrupt-controller@e61c0000 { 523 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 524 #interrupt-cells = <2>; 525 interrupt-controller; 526 reg = <0 0xe61c0000 0 0x200>; 527 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cpg CPG_MOD 407>; 534 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 535 resets = <&cpg 407>; 536 }; 537 538 tmu0: timer@e61e0000 { 539 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 540 reg = <0 0xe61e0000 0 0x30>; 541 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cpg CPG_MOD 125>; 545 clock-names = "fck"; 546 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 547 resets = <&cpg 125>; 548 status = "disabled"; 549 }; 550 551 tmu1: timer@e6fc0000 { 552 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 553 reg = <0 0xe6fc0000 0 0x30>; 554 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cpg CPG_MOD 124>; 558 clock-names = "fck"; 559 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 560 resets = <&cpg 124>; 561 status = "disabled"; 562 }; 563 564 tmu2: timer@e6fd0000 { 565 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 566 reg = <0 0xe6fd0000 0 0x30>; 567 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 123>; 571 clock-names = "fck"; 572 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 573 resets = <&cpg 123>; 574 status = "disabled"; 575 }; 576 577 tmu3: timer@e6fe0000 { 578 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 579 reg = <0 0xe6fe0000 0 0x30>; 580 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cpg CPG_MOD 122>; 584 clock-names = "fck"; 585 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 586 resets = <&cpg 122>; 587 status = "disabled"; 588 }; 589 590 tmu4: timer@ffc00000 { 591 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 592 reg = <0 0xffc00000 0 0x30>; 593 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cpg CPG_MOD 121>; 597 clock-names = "fck"; 598 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 599 resets = <&cpg 121>; 600 status = "disabled"; 601 }; 602 603 i2c0: i2c@e6500000 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 compatible = "renesas,i2c-r8a774a1", 607 "renesas,rcar-gen3-i2c"; 608 reg = <0 0xe6500000 0 0x40>; 609 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&cpg CPG_MOD 931>; 611 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 612 resets = <&cpg 931>; 613 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 614 <&dmac2 0x91>, <&dmac2 0x90>; 615 dma-names = "tx", "rx", "tx", "rx"; 616 i2c-scl-internal-delay-ns = <110>; 617 status = "disabled"; 618 }; 619 620 i2c1: i2c@e6508000 { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 compatible = "renesas,i2c-r8a774a1", 624 "renesas,rcar-gen3-i2c"; 625 reg = <0 0xe6508000 0 0x40>; 626 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cpg CPG_MOD 930>; 628 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 629 resets = <&cpg 930>; 630 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 631 <&dmac2 0x93>, <&dmac2 0x92>; 632 dma-names = "tx", "rx", "tx", "rx"; 633 i2c-scl-internal-delay-ns = <6>; 634 status = "disabled"; 635 }; 636 637 i2c2: i2c@e6510000 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 compatible = "renesas,i2c-r8a774a1", 641 "renesas,rcar-gen3-i2c"; 642 reg = <0 0xe6510000 0 0x40>; 643 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cpg CPG_MOD 929>; 645 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 646 resets = <&cpg 929>; 647 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 648 <&dmac2 0x95>, <&dmac2 0x94>; 649 dma-names = "tx", "rx", "tx", "rx"; 650 i2c-scl-internal-delay-ns = <6>; 651 status = "disabled"; 652 }; 653 654 i2c3: i2c@e66d0000 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 compatible = "renesas,i2c-r8a774a1", 658 "renesas,rcar-gen3-i2c"; 659 reg = <0 0xe66d0000 0 0x40>; 660 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&cpg CPG_MOD 928>; 662 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 663 resets = <&cpg 928>; 664 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 665 dma-names = "tx", "rx"; 666 i2c-scl-internal-delay-ns = <110>; 667 status = "disabled"; 668 }; 669 670 i2c4: i2c@e66d8000 { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 compatible = "renesas,i2c-r8a774a1", 674 "renesas,rcar-gen3-i2c"; 675 reg = <0 0xe66d8000 0 0x40>; 676 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cpg CPG_MOD 927>; 678 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 679 resets = <&cpg 927>; 680 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 681 dma-names = "tx", "rx"; 682 i2c-scl-internal-delay-ns = <110>; 683 status = "disabled"; 684 }; 685 686 i2c5: i2c@e66e0000 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 compatible = "renesas,i2c-r8a774a1", 690 "renesas,rcar-gen3-i2c"; 691 reg = <0 0xe66e0000 0 0x40>; 692 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cpg CPG_MOD 919>; 694 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 695 resets = <&cpg 919>; 696 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 697 dma-names = "tx", "rx"; 698 i2c-scl-internal-delay-ns = <110>; 699 status = "disabled"; 700 }; 701 702 i2c6: i2c@e66e8000 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 compatible = "renesas,i2c-r8a774a1", 706 "renesas,rcar-gen3-i2c"; 707 reg = <0 0xe66e8000 0 0x40>; 708 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cpg CPG_MOD 918>; 710 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 711 resets = <&cpg 918>; 712 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 713 dma-names = "tx", "rx"; 714 i2c-scl-internal-delay-ns = <6>; 715 status = "disabled"; 716 }; 717 718 i2c_dvfs: i2c@e60b0000 { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 compatible = "renesas,iic-r8a774a1", 722 "renesas,rcar-gen3-iic", 723 "renesas,rmobile-iic"; 724 reg = <0 0xe60b0000 0 0x425>; 725 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&cpg CPG_MOD 926>; 727 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 728 resets = <&cpg 926>; 729 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 730 dma-names = "tx", "rx"; 731 status = "disabled"; 732 }; 733 734 hscif0: serial@e6540000 { 735 compatible = "renesas,hscif-r8a774a1", 736 "renesas,rcar-gen3-hscif", 737 "renesas,hscif"; 738 reg = <0 0xe6540000 0 0x60>; 739 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&cpg CPG_MOD 520>, 741 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 742 <&scif_clk>; 743 clock-names = "fck", "brg_int", "scif_clk"; 744 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 745 <&dmac2 0x31>, <&dmac2 0x30>; 746 dma-names = "tx", "rx", "tx", "rx"; 747 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 748 resets = <&cpg 520>; 749 status = "disabled"; 750 }; 751 752 hscif1: serial@e6550000 { 753 compatible = "renesas,hscif-r8a774a1", 754 "renesas,rcar-gen3-hscif", 755 "renesas,hscif"; 756 reg = <0 0xe6550000 0 0x60>; 757 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cpg CPG_MOD 519>, 759 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 760 <&scif_clk>; 761 clock-names = "fck", "brg_int", "scif_clk"; 762 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 763 <&dmac2 0x33>, <&dmac2 0x32>; 764 dma-names = "tx", "rx", "tx", "rx"; 765 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 766 resets = <&cpg 519>; 767 status = "disabled"; 768 }; 769 770 hscif2: serial@e6560000 { 771 compatible = "renesas,hscif-r8a774a1", 772 "renesas,rcar-gen3-hscif", 773 "renesas,hscif"; 774 reg = <0 0xe6560000 0 0x60>; 775 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cpg CPG_MOD 518>, 777 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 778 <&scif_clk>; 779 clock-names = "fck", "brg_int", "scif_clk"; 780 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 781 <&dmac2 0x35>, <&dmac2 0x34>; 782 dma-names = "tx", "rx", "tx", "rx"; 783 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 784 resets = <&cpg 518>; 785 status = "disabled"; 786 }; 787 788 hscif3: serial@e66a0000 { 789 compatible = "renesas,hscif-r8a774a1", 790 "renesas,rcar-gen3-hscif", 791 "renesas,hscif"; 792 reg = <0 0xe66a0000 0 0x60>; 793 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cpg CPG_MOD 517>, 795 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 796 <&scif_clk>; 797 clock-names = "fck", "brg_int", "scif_clk"; 798 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 799 dma-names = "tx", "rx"; 800 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 801 resets = <&cpg 517>; 802 status = "disabled"; 803 }; 804 805 hscif4: serial@e66b0000 { 806 compatible = "renesas,hscif-r8a774a1", 807 "renesas,rcar-gen3-hscif", 808 "renesas,hscif"; 809 reg = <0 0xe66b0000 0 0x60>; 810 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&cpg CPG_MOD 516>, 812 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 813 <&scif_clk>; 814 clock-names = "fck", "brg_int", "scif_clk"; 815 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 816 dma-names = "tx", "rx"; 817 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 818 resets = <&cpg 516>; 819 status = "disabled"; 820 }; 821 822 hsusb: usb@e6590000 { 823 compatible = "renesas,usbhs-r8a774a1", 824 "renesas,rcar-gen3-usbhs"; 825 reg = <0 0xe6590000 0 0x200>; 826 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 828 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 829 <&usb_dmac1 0>, <&usb_dmac1 1>; 830 dma-names = "ch0", "ch1", "ch2", "ch3"; 831 renesas,buswait = <11>; 832 phys = <&usb2_phy0 3>; 833 phy-names = "usb"; 834 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 835 resets = <&cpg 704>, <&cpg 703>; 836 status = "disabled"; 837 }; 838 839 usb2_clksel: clock-controller@e6590630 { 840 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", 841 "renesas,rcar-gen3-usb2-clock-sel"; 842 reg = <0 0xe6590630 0 0x02>; 843 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, 844 <&usb_extal_clk>, <&usb3s0_clk>; 845 clock-names = "ehci_ohci", "hs-usb-if", 846 "usb_extal", "usb_xtal"; 847 #clock-cells = <0>; 848 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 849 resets = <&cpg 703>, <&cpg 704>; 850 reset-names = "ehci_ohci", "hs-usb-if"; 851 status = "disabled"; 852 }; 853 854 usb_dmac0: dma-controller@e65a0000 { 855 compatible = "renesas,r8a774a1-usb-dmac", 856 "renesas,usb-dmac"; 857 reg = <0 0xe65a0000 0 0x100>; 858 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-names = "ch0", "ch1"; 861 clocks = <&cpg CPG_MOD 330>; 862 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 863 resets = <&cpg 330>; 864 #dma-cells = <1>; 865 dma-channels = <2>; 866 }; 867 868 usb_dmac1: dma-controller@e65b0000 { 869 compatible = "renesas,r8a774a1-usb-dmac", 870 "renesas,usb-dmac"; 871 reg = <0 0xe65b0000 0 0x100>; 872 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "ch0", "ch1"; 875 clocks = <&cpg CPG_MOD 331>; 876 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 877 resets = <&cpg 331>; 878 #dma-cells = <1>; 879 dma-channels = <2>; 880 }; 881 882 usb3_phy0: usb-phy@e65ee000 { 883 compatible = "renesas,r8a774a1-usb3-phy", 884 "renesas,rcar-gen3-usb3-phy"; 885 reg = <0 0xe65ee000 0 0x90>; 886 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 887 <&usb_extal_clk>; 888 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 889 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 890 resets = <&cpg 328>; 891 #phy-cells = <0>; 892 status = "disabled"; 893 }; 894 895 dmac0: dma-controller@e6700000 { 896 compatible = "renesas,dmac-r8a774a1", 897 "renesas,rcar-dmac"; 898 reg = <0 0xe6700000 0 0x10000>; 899 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "error", 917 "ch0", "ch1", "ch2", "ch3", 918 "ch4", "ch5", "ch6", "ch7", 919 "ch8", "ch9", "ch10", "ch11", 920 "ch12", "ch13", "ch14", "ch15"; 921 clocks = <&cpg CPG_MOD 219>; 922 clock-names = "fck"; 923 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 924 resets = <&cpg 219>; 925 #dma-cells = <1>; 926 dma-channels = <16>; 927 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 928 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 929 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 930 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 931 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 932 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 933 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 934 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 935 }; 936 937 dmac1: dma-controller@e7300000 { 938 compatible = "renesas,dmac-r8a774a1", 939 "renesas,rcar-dmac"; 940 reg = <0 0xe7300000 0 0x10000>; 941 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "error", 959 "ch0", "ch1", "ch2", "ch3", 960 "ch4", "ch5", "ch6", "ch7", 961 "ch8", "ch9", "ch10", "ch11", 962 "ch12", "ch13", "ch14", "ch15"; 963 clocks = <&cpg CPG_MOD 218>; 964 clock-names = "fck"; 965 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 966 resets = <&cpg 218>; 967 #dma-cells = <1>; 968 dma-channels = <16>; 969 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 970 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 971 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 972 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 973 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 974 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 975 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 976 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 977 }; 978 979 dmac2: dma-controller@e7310000 { 980 compatible = "renesas,dmac-r8a774a1", 981 "renesas,rcar-dmac"; 982 reg = <0 0xe7310000 0 0x10000>; 983 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1000 interrupt-names = "error", 1001 "ch0", "ch1", "ch2", "ch3", 1002 "ch4", "ch5", "ch6", "ch7", 1003 "ch8", "ch9", "ch10", "ch11", 1004 "ch12", "ch13", "ch14", "ch15"; 1005 clocks = <&cpg CPG_MOD 217>; 1006 clock-names = "fck"; 1007 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1008 resets = <&cpg 217>; 1009 #dma-cells = <1>; 1010 dma-channels = <16>; 1011 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1012 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1013 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1014 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1015 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1016 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1017 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1018 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1019 }; 1020 1021 ipmmu_ds0: iommu@e6740000 { 1022 compatible = "renesas,ipmmu-r8a774a1"; 1023 reg = <0 0xe6740000 0 0x1000>; 1024 renesas,ipmmu-main = <&ipmmu_mm 0>; 1025 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1026 #iommu-cells = <1>; 1027 }; 1028 1029 ipmmu_ds1: iommu@e7740000 { 1030 compatible = "renesas,ipmmu-r8a774a1"; 1031 reg = <0 0xe7740000 0 0x1000>; 1032 renesas,ipmmu-main = <&ipmmu_mm 1>; 1033 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1034 #iommu-cells = <1>; 1035 }; 1036 1037 ipmmu_hc: iommu@e6570000 { 1038 compatible = "renesas,ipmmu-r8a774a1"; 1039 reg = <0 0xe6570000 0 0x1000>; 1040 renesas,ipmmu-main = <&ipmmu_mm 2>; 1041 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1042 #iommu-cells = <1>; 1043 }; 1044 1045 ipmmu_mm: iommu@e67b0000 { 1046 compatible = "renesas,ipmmu-r8a774a1"; 1047 reg = <0 0xe67b0000 0 0x1000>; 1048 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1050 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1051 #iommu-cells = <1>; 1052 }; 1053 1054 ipmmu_mp: iommu@ec670000 { 1055 compatible = "renesas,ipmmu-r8a774a1"; 1056 reg = <0 0xec670000 0 0x1000>; 1057 renesas,ipmmu-main = <&ipmmu_mm 4>; 1058 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1059 #iommu-cells = <1>; 1060 }; 1061 1062 ipmmu_pv0: iommu@fd800000 { 1063 compatible = "renesas,ipmmu-r8a774a1"; 1064 reg = <0 0xfd800000 0 0x1000>; 1065 renesas,ipmmu-main = <&ipmmu_mm 5>; 1066 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1067 #iommu-cells = <1>; 1068 }; 1069 1070 ipmmu_pv1: iommu@fd950000 { 1071 compatible = "renesas,ipmmu-r8a774a1"; 1072 reg = <0 0xfd950000 0 0x1000>; 1073 renesas,ipmmu-main = <&ipmmu_mm 6>; 1074 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1075 #iommu-cells = <1>; 1076 }; 1077 1078 ipmmu_vc0: iommu@fe6b0000 { 1079 compatible = "renesas,ipmmu-r8a774a1"; 1080 reg = <0 0xfe6b0000 0 0x1000>; 1081 renesas,ipmmu-main = <&ipmmu_mm 8>; 1082 power-domains = <&sysc R8A774A1_PD_A3VC>; 1083 #iommu-cells = <1>; 1084 }; 1085 1086 ipmmu_vi0: iommu@febd0000 { 1087 compatible = "renesas,ipmmu-r8a774a1"; 1088 reg = <0 0xfebd0000 0 0x1000>; 1089 renesas,ipmmu-main = <&ipmmu_mm 9>; 1090 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1091 #iommu-cells = <1>; 1092 }; 1093 1094 avb: ethernet@e6800000 { 1095 compatible = "renesas,etheravb-r8a774a1", 1096 "renesas,etheravb-rcar-gen3"; 1097 reg = <0 0xe6800000 0 0x800>; 1098 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1123 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1124 "ch4", "ch5", "ch6", "ch7", 1125 "ch8", "ch9", "ch10", "ch11", 1126 "ch12", "ch13", "ch14", "ch15", 1127 "ch16", "ch17", "ch18", "ch19", 1128 "ch20", "ch21", "ch22", "ch23", 1129 "ch24"; 1130 clocks = <&cpg CPG_MOD 812>; 1131 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1132 resets = <&cpg 812>; 1133 phy-mode = "rgmii"; 1134 rx-internal-delay-ps = <0>; 1135 tx-internal-delay-ps = <0>; 1136 iommus = <&ipmmu_ds0 16>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 can0: can@e6c30000 { 1143 compatible = "renesas,can-r8a774a1", 1144 "renesas,rcar-gen3-can"; 1145 reg = <0 0xe6c30000 0 0x1000>; 1146 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&cpg CPG_MOD 916>, 1148 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1149 <&can_clk>; 1150 clock-names = "clkp1", "clkp2", "can_clk"; 1151 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1152 assigned-clock-rates = <40000000>; 1153 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1154 resets = <&cpg 916>; 1155 status = "disabled"; 1156 }; 1157 1158 can1: can@e6c38000 { 1159 compatible = "renesas,can-r8a774a1", 1160 "renesas,rcar-gen3-can"; 1161 reg = <0 0xe6c38000 0 0x1000>; 1162 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&cpg CPG_MOD 915>, 1164 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1165 <&can_clk>; 1166 clock-names = "clkp1", "clkp2", "can_clk"; 1167 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1168 assigned-clock-rates = <40000000>; 1169 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1170 resets = <&cpg 915>; 1171 status = "disabled"; 1172 }; 1173 1174 canfd: can@e66c0000 { 1175 compatible = "renesas,r8a774a1-canfd", 1176 "renesas,rcar-gen3-canfd"; 1177 reg = <0 0xe66c0000 0 0x8000>; 1178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&cpg CPG_MOD 914>, 1181 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1182 <&can_clk>; 1183 clock-names = "fck", "canfd", "can_clk"; 1184 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1185 assigned-clock-rates = <40000000>; 1186 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1187 resets = <&cpg 914>; 1188 status = "disabled"; 1189 1190 channel0 { 1191 status = "disabled"; 1192 }; 1193 1194 channel1 { 1195 status = "disabled"; 1196 }; 1197 }; 1198 1199 pwm0: pwm@e6e30000 { 1200 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1201 reg = <0 0xe6e30000 0 0x8>; 1202 #pwm-cells = <2>; 1203 clocks = <&cpg CPG_MOD 523>; 1204 resets = <&cpg 523>; 1205 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1206 status = "disabled"; 1207 }; 1208 1209 pwm1: pwm@e6e31000 { 1210 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1211 reg = <0 0xe6e31000 0 0x8>; 1212 #pwm-cells = <2>; 1213 clocks = <&cpg CPG_MOD 523>; 1214 resets = <&cpg 523>; 1215 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1216 status = "disabled"; 1217 }; 1218 1219 pwm2: pwm@e6e32000 { 1220 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1221 reg = <0 0xe6e32000 0 0x8>; 1222 #pwm-cells = <2>; 1223 clocks = <&cpg CPG_MOD 523>; 1224 resets = <&cpg 523>; 1225 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1226 status = "disabled"; 1227 }; 1228 1229 pwm3: pwm@e6e33000 { 1230 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1231 reg = <0 0xe6e33000 0 0x8>; 1232 #pwm-cells = <2>; 1233 clocks = <&cpg CPG_MOD 523>; 1234 resets = <&cpg 523>; 1235 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1236 status = "disabled"; 1237 }; 1238 1239 pwm4: pwm@e6e34000 { 1240 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1241 reg = <0 0xe6e34000 0 0x8>; 1242 #pwm-cells = <2>; 1243 clocks = <&cpg CPG_MOD 523>; 1244 resets = <&cpg 523>; 1245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1246 status = "disabled"; 1247 }; 1248 1249 pwm5: pwm@e6e35000 { 1250 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1251 reg = <0 0xe6e35000 0 0x8>; 1252 #pwm-cells = <2>; 1253 clocks = <&cpg CPG_MOD 523>; 1254 resets = <&cpg 523>; 1255 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1256 status = "disabled"; 1257 }; 1258 1259 pwm6: pwm@e6e36000 { 1260 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1261 reg = <0 0xe6e36000 0 0x8>; 1262 #pwm-cells = <2>; 1263 clocks = <&cpg CPG_MOD 523>; 1264 resets = <&cpg 523>; 1265 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1266 status = "disabled"; 1267 }; 1268 1269 scif0: serial@e6e60000 { 1270 compatible = "renesas,scif-r8a774a1", 1271 "renesas,rcar-gen3-scif", "renesas,scif"; 1272 reg = <0 0xe6e60000 0 0x40>; 1273 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&cpg CPG_MOD 207>, 1275 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1276 <&scif_clk>; 1277 clock-names = "fck", "brg_int", "scif_clk"; 1278 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1279 <&dmac2 0x51>, <&dmac2 0x50>; 1280 dma-names = "tx", "rx", "tx", "rx"; 1281 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1282 resets = <&cpg 207>; 1283 status = "disabled"; 1284 }; 1285 1286 scif1: serial@e6e68000 { 1287 compatible = "renesas,scif-r8a774a1", 1288 "renesas,rcar-gen3-scif", "renesas,scif"; 1289 reg = <0 0xe6e68000 0 0x40>; 1290 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&cpg CPG_MOD 206>, 1292 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1293 <&scif_clk>; 1294 clock-names = "fck", "brg_int", "scif_clk"; 1295 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1296 <&dmac2 0x53>, <&dmac2 0x52>; 1297 dma-names = "tx", "rx", "tx", "rx"; 1298 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1299 resets = <&cpg 206>; 1300 status = "disabled"; 1301 }; 1302 1303 scif2: serial@e6e88000 { 1304 compatible = "renesas,scif-r8a774a1", 1305 "renesas,rcar-gen3-scif", "renesas,scif"; 1306 reg = <0 0xe6e88000 0 0x40>; 1307 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&cpg CPG_MOD 310>, 1309 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1310 <&scif_clk>; 1311 clock-names = "fck", "brg_int", "scif_clk"; 1312 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1313 <&dmac2 0x13>, <&dmac2 0x12>; 1314 dma-names = "tx", "rx", "tx", "rx"; 1315 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1316 resets = <&cpg 310>; 1317 status = "disabled"; 1318 }; 1319 1320 scif3: serial@e6c50000 { 1321 compatible = "renesas,scif-r8a774a1", 1322 "renesas,rcar-gen3-scif", "renesas,scif"; 1323 reg = <0 0xe6c50000 0 0x40>; 1324 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&cpg CPG_MOD 204>, 1326 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1327 <&scif_clk>; 1328 clock-names = "fck", "brg_int", "scif_clk"; 1329 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1330 dma-names = "tx", "rx"; 1331 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1332 resets = <&cpg 204>; 1333 status = "disabled"; 1334 }; 1335 1336 scif4: serial@e6c40000 { 1337 compatible = "renesas,scif-r8a774a1", 1338 "renesas,rcar-gen3-scif", "renesas,scif"; 1339 reg = <0 0xe6c40000 0 0x40>; 1340 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&cpg CPG_MOD 203>, 1342 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1343 <&scif_clk>; 1344 clock-names = "fck", "brg_int", "scif_clk"; 1345 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1346 dma-names = "tx", "rx"; 1347 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1348 resets = <&cpg 203>; 1349 status = "disabled"; 1350 }; 1351 1352 scif5: serial@e6f30000 { 1353 compatible = "renesas,scif-r8a774a1", 1354 "renesas,rcar-gen3-scif", "renesas,scif"; 1355 reg = <0 0xe6f30000 0 0x40>; 1356 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&cpg CPG_MOD 202>, 1358 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1359 <&scif_clk>; 1360 clock-names = "fck", "brg_int", "scif_clk"; 1361 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1362 <&dmac2 0x5b>, <&dmac2 0x5a>; 1363 dma-names = "tx", "rx", "tx", "rx"; 1364 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1365 resets = <&cpg 202>; 1366 status = "disabled"; 1367 }; 1368 1369 msiof0: spi@e6e90000 { 1370 compatible = "renesas,msiof-r8a774a1", 1371 "renesas,rcar-gen3-msiof"; 1372 reg = <0 0xe6e90000 0 0x0064>; 1373 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&cpg CPG_MOD 211>; 1375 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1376 <&dmac2 0x41>, <&dmac2 0x40>; 1377 dma-names = "tx", "rx", "tx", "rx"; 1378 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1379 resets = <&cpg 211>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 msiof1: spi@e6ea0000 { 1386 compatible = "renesas,msiof-r8a774a1", 1387 "renesas,rcar-gen3-msiof"; 1388 reg = <0 0xe6ea0000 0 0x0064>; 1389 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cpg CPG_MOD 210>; 1391 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1392 <&dmac2 0x43>, <&dmac2 0x42>; 1393 dma-names = "tx", "rx", "tx", "rx"; 1394 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1395 resets = <&cpg 210>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 msiof2: spi@e6c00000 { 1402 compatible = "renesas,msiof-r8a774a1", 1403 "renesas,rcar-gen3-msiof"; 1404 reg = <0 0xe6c00000 0 0x0064>; 1405 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&cpg CPG_MOD 209>; 1407 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1408 dma-names = "tx", "rx"; 1409 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1410 resets = <&cpg 209>; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 status = "disabled"; 1414 }; 1415 1416 msiof3: spi@e6c10000 { 1417 compatible = "renesas,msiof-r8a774a1", 1418 "renesas,rcar-gen3-msiof"; 1419 reg = <0 0xe6c10000 0 0x0064>; 1420 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1421 clocks = <&cpg CPG_MOD 208>; 1422 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1423 dma-names = "tx", "rx"; 1424 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1425 resets = <&cpg 208>; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 status = "disabled"; 1429 }; 1430 1431 vin0: video@e6ef0000 { 1432 compatible = "renesas,vin-r8a774a1"; 1433 reg = <0 0xe6ef0000 0 0x1000>; 1434 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&cpg CPG_MOD 811>; 1436 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1437 resets = <&cpg 811>; 1438 renesas,id = <0>; 1439 status = "disabled"; 1440 1441 ports { 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 1445 port@1 { 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 1449 reg = <1>; 1450 1451 vin0csi20: endpoint@0 { 1452 reg = <0>; 1453 remote-endpoint = <&csi20vin0>; 1454 }; 1455 vin0csi40: endpoint@2 { 1456 reg = <2>; 1457 remote-endpoint = <&csi40vin0>; 1458 }; 1459 }; 1460 }; 1461 }; 1462 1463 vin1: video@e6ef1000 { 1464 compatible = "renesas,vin-r8a774a1"; 1465 reg = <0 0xe6ef1000 0 0x1000>; 1466 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1467 clocks = <&cpg CPG_MOD 810>; 1468 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1469 resets = <&cpg 810>; 1470 renesas,id = <1>; 1471 status = "disabled"; 1472 1473 ports { 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 1477 port@1 { 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 1481 reg = <1>; 1482 1483 vin1csi20: endpoint@0 { 1484 reg = <0>; 1485 remote-endpoint = <&csi20vin1>; 1486 }; 1487 vin1csi40: endpoint@2 { 1488 reg = <2>; 1489 remote-endpoint = <&csi40vin1>; 1490 }; 1491 }; 1492 }; 1493 }; 1494 1495 vin2: video@e6ef2000 { 1496 compatible = "renesas,vin-r8a774a1"; 1497 reg = <0 0xe6ef2000 0 0x1000>; 1498 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1499 clocks = <&cpg CPG_MOD 809>; 1500 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1501 resets = <&cpg 809>; 1502 renesas,id = <2>; 1503 status = "disabled"; 1504 1505 ports { 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 1509 port@1 { 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 1513 reg = <1>; 1514 1515 vin2csi20: endpoint@0 { 1516 reg = <0>; 1517 remote-endpoint = <&csi20vin2>; 1518 }; 1519 vin2csi40: endpoint@2 { 1520 reg = <2>; 1521 remote-endpoint = <&csi40vin2>; 1522 }; 1523 }; 1524 }; 1525 }; 1526 1527 vin3: video@e6ef3000 { 1528 compatible = "renesas,vin-r8a774a1"; 1529 reg = <0 0xe6ef3000 0 0x1000>; 1530 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1531 clocks = <&cpg CPG_MOD 808>; 1532 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1533 resets = <&cpg 808>; 1534 renesas,id = <3>; 1535 status = "disabled"; 1536 1537 ports { 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 port@1 { 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 1545 reg = <1>; 1546 1547 vin3csi20: endpoint@0 { 1548 reg = <0>; 1549 remote-endpoint = <&csi20vin3>; 1550 }; 1551 vin3csi40: endpoint@2 { 1552 reg = <2>; 1553 remote-endpoint = <&csi40vin3>; 1554 }; 1555 }; 1556 }; 1557 }; 1558 1559 vin4: video@e6ef4000 { 1560 compatible = "renesas,vin-r8a774a1"; 1561 reg = <0 0xe6ef4000 0 0x1000>; 1562 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1563 clocks = <&cpg CPG_MOD 807>; 1564 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1565 resets = <&cpg 807>; 1566 renesas,id = <4>; 1567 status = "disabled"; 1568 1569 ports { 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 1573 port@1 { 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 1577 reg = <1>; 1578 1579 vin4csi20: endpoint@0 { 1580 reg = <0>; 1581 remote-endpoint = <&csi20vin4>; 1582 }; 1583 vin4csi40: endpoint@2 { 1584 reg = <2>; 1585 remote-endpoint = <&csi40vin4>; 1586 }; 1587 }; 1588 }; 1589 }; 1590 1591 vin5: video@e6ef5000 { 1592 compatible = "renesas,vin-r8a774a1"; 1593 reg = <0 0xe6ef5000 0 0x1000>; 1594 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&cpg CPG_MOD 806>; 1596 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1597 resets = <&cpg 806>; 1598 renesas,id = <5>; 1599 status = "disabled"; 1600 1601 ports { 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 port@1 { 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 1609 reg = <1>; 1610 1611 vin5csi20: endpoint@0 { 1612 reg = <0>; 1613 remote-endpoint = <&csi20vin5>; 1614 }; 1615 vin5csi40: endpoint@2 { 1616 reg = <2>; 1617 remote-endpoint = <&csi40vin5>; 1618 }; 1619 }; 1620 }; 1621 }; 1622 1623 vin6: video@e6ef6000 { 1624 compatible = "renesas,vin-r8a774a1"; 1625 reg = <0 0xe6ef6000 0 0x1000>; 1626 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1627 clocks = <&cpg CPG_MOD 805>; 1628 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1629 resets = <&cpg 805>; 1630 renesas,id = <6>; 1631 status = "disabled"; 1632 1633 ports { 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 1637 port@1 { 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 reg = <1>; 1642 1643 vin6csi20: endpoint@0 { 1644 reg = <0>; 1645 remote-endpoint = <&csi20vin6>; 1646 }; 1647 vin6csi40: endpoint@2 { 1648 reg = <2>; 1649 remote-endpoint = <&csi40vin6>; 1650 }; 1651 }; 1652 }; 1653 }; 1654 1655 vin7: video@e6ef7000 { 1656 compatible = "renesas,vin-r8a774a1"; 1657 reg = <0 0xe6ef7000 0 0x1000>; 1658 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&cpg CPG_MOD 804>; 1660 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1661 resets = <&cpg 804>; 1662 renesas,id = <7>; 1663 status = "disabled"; 1664 1665 ports { 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 1669 port@1 { 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 1673 reg = <1>; 1674 1675 vin7csi20: endpoint@0 { 1676 reg = <0>; 1677 remote-endpoint = <&csi20vin7>; 1678 }; 1679 vin7csi40: endpoint@2 { 1680 reg = <2>; 1681 remote-endpoint = <&csi40vin7>; 1682 }; 1683 }; 1684 }; 1685 }; 1686 1687 rcar_sound: sound@ec500000 { 1688 /* 1689 * #sound-dai-cells is required 1690 * 1691 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1692 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1693 */ 1694 /* 1695 * #clock-cells is required for audio_clkout0/1/2/3 1696 * 1697 * clkout : #clock-cells = <0>; <&rcar_sound>; 1698 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1699 */ 1700 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1701 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1702 <0 0xec5a0000 0 0x100>, /* ADG */ 1703 <0 0xec540000 0 0x1000>, /* SSIU */ 1704 <0 0xec541000 0 0x280>, /* SSI */ 1705 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1706 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1707 1708 clocks = <&cpg CPG_MOD 1005>, 1709 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1710 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1711 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1712 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1713 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1714 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1715 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1716 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1717 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1718 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1719 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1720 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1721 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1722 <&audio_clk_a>, <&audio_clk_b>, 1723 <&audio_clk_c>, 1724 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1725 clock-names = "ssi-all", 1726 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1727 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1728 "ssi.1", "ssi.0", 1729 "src.9", "src.8", "src.7", "src.6", 1730 "src.5", "src.4", "src.3", "src.2", 1731 "src.1", "src.0", 1732 "mix.1", "mix.0", 1733 "ctu.1", "ctu.0", 1734 "dvc.0", "dvc.1", 1735 "clk_a", "clk_b", "clk_c", "clk_i"; 1736 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1737 resets = <&cpg 1005>, 1738 <&cpg 1006>, <&cpg 1007>, 1739 <&cpg 1008>, <&cpg 1009>, 1740 <&cpg 1010>, <&cpg 1011>, 1741 <&cpg 1012>, <&cpg 1013>, 1742 <&cpg 1014>, <&cpg 1015>; 1743 reset-names = "ssi-all", 1744 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1745 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1746 "ssi.1", "ssi.0"; 1747 status = "disabled"; 1748 1749 rcar_sound,ctu { 1750 ctu00: ctu-0 { }; 1751 ctu01: ctu-1 { }; 1752 ctu02: ctu-2 { }; 1753 ctu03: ctu-3 { }; 1754 ctu10: ctu-4 { }; 1755 ctu11: ctu-5 { }; 1756 ctu12: ctu-6 { }; 1757 ctu13: ctu-7 { }; 1758 }; 1759 1760 rcar_sound,dvc { 1761 dvc0: dvc-0 { 1762 dmas = <&audma1 0xbc>; 1763 dma-names = "tx"; 1764 }; 1765 dvc1: dvc-1 { 1766 dmas = <&audma1 0xbe>; 1767 dma-names = "tx"; 1768 }; 1769 }; 1770 1771 rcar_sound,mix { 1772 mix0: mix-0 { }; 1773 mix1: mix-1 { }; 1774 }; 1775 1776 rcar_sound,src { 1777 src0: src-0 { 1778 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1779 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1780 dma-names = "rx", "tx"; 1781 }; 1782 src1: src-1 { 1783 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1784 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1785 dma-names = "rx", "tx"; 1786 }; 1787 src2: src-2 { 1788 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1789 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1790 dma-names = "rx", "tx"; 1791 }; 1792 src3: src-3 { 1793 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1794 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1795 dma-names = "rx", "tx"; 1796 }; 1797 src4: src-4 { 1798 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1799 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1800 dma-names = "rx", "tx"; 1801 }; 1802 src5: src-5 { 1803 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1804 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1805 dma-names = "rx", "tx"; 1806 }; 1807 src6: src-6 { 1808 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1809 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1810 dma-names = "rx", "tx"; 1811 }; 1812 src7: src-7 { 1813 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1814 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1815 dma-names = "rx", "tx"; 1816 }; 1817 src8: src-8 { 1818 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1819 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1820 dma-names = "rx", "tx"; 1821 }; 1822 src9: src-9 { 1823 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1824 dmas = <&audma0 0x97>, <&audma1 0xba>; 1825 dma-names = "rx", "tx"; 1826 }; 1827 }; 1828 1829 rcar_sound,ssi { 1830 ssi0: ssi-0 { 1831 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1832 dmas = <&audma0 0x01>, <&audma1 0x02>; 1833 dma-names = "rx", "tx"; 1834 }; 1835 ssi1: ssi-1 { 1836 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1837 dmas = <&audma0 0x03>, <&audma1 0x04>; 1838 dma-names = "rx", "tx"; 1839 }; 1840 ssi2: ssi-2 { 1841 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&audma0 0x05>, <&audma1 0x06>; 1843 dma-names = "rx", "tx"; 1844 }; 1845 ssi3: ssi-3 { 1846 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1847 dmas = <&audma0 0x07>, <&audma1 0x08>; 1848 dma-names = "rx", "tx"; 1849 }; 1850 ssi4: ssi-4 { 1851 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1852 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1853 dma-names = "rx", "tx"; 1854 }; 1855 ssi5: ssi-5 { 1856 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1857 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1858 dma-names = "rx", "tx"; 1859 }; 1860 ssi6: ssi-6 { 1861 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1862 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1863 dma-names = "rx", "tx"; 1864 }; 1865 ssi7: ssi-7 { 1866 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1867 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1868 dma-names = "rx", "tx"; 1869 }; 1870 ssi8: ssi-8 { 1871 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1872 dmas = <&audma0 0x11>, <&audma1 0x12>; 1873 dma-names = "rx", "tx"; 1874 }; 1875 ssi9: ssi-9 { 1876 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1877 dmas = <&audma0 0x13>, <&audma1 0x14>; 1878 dma-names = "rx", "tx"; 1879 }; 1880 }; 1881 1882 rcar_sound,ssiu { 1883 ssiu00: ssiu-0 { 1884 dmas = <&audma0 0x15>, <&audma1 0x16>; 1885 dma-names = "rx", "tx"; 1886 }; 1887 ssiu01: ssiu-1 { 1888 dmas = <&audma0 0x35>, <&audma1 0x36>; 1889 dma-names = "rx", "tx"; 1890 }; 1891 ssiu02: ssiu-2 { 1892 dmas = <&audma0 0x37>, <&audma1 0x38>; 1893 dma-names = "rx", "tx"; 1894 }; 1895 ssiu03: ssiu-3 { 1896 dmas = <&audma0 0x47>, <&audma1 0x48>; 1897 dma-names = "rx", "tx"; 1898 }; 1899 ssiu04: ssiu-4 { 1900 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1901 dma-names = "rx", "tx"; 1902 }; 1903 ssiu05: ssiu-5 { 1904 dmas = <&audma0 0x43>, <&audma1 0x44>; 1905 dma-names = "rx", "tx"; 1906 }; 1907 ssiu06: ssiu-6 { 1908 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1909 dma-names = "rx", "tx"; 1910 }; 1911 ssiu07: ssiu-7 { 1912 dmas = <&audma0 0x53>, <&audma1 0x54>; 1913 dma-names = "rx", "tx"; 1914 }; 1915 ssiu10: ssiu-8 { 1916 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1917 dma-names = "rx", "tx"; 1918 }; 1919 ssiu11: ssiu-9 { 1920 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1921 dma-names = "rx", "tx"; 1922 }; 1923 ssiu12: ssiu-10 { 1924 dmas = <&audma0 0x57>, <&audma1 0x58>; 1925 dma-names = "rx", "tx"; 1926 }; 1927 ssiu13: ssiu-11 { 1928 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1929 dma-names = "rx", "tx"; 1930 }; 1931 ssiu14: ssiu-12 { 1932 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1933 dma-names = "rx", "tx"; 1934 }; 1935 ssiu15: ssiu-13 { 1936 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1937 dma-names = "rx", "tx"; 1938 }; 1939 ssiu16: ssiu-14 { 1940 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1941 dma-names = "rx", "tx"; 1942 }; 1943 ssiu17: ssiu-15 { 1944 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1945 dma-names = "rx", "tx"; 1946 }; 1947 ssiu20: ssiu-16 { 1948 dmas = <&audma0 0x63>, <&audma1 0x64>; 1949 dma-names = "rx", "tx"; 1950 }; 1951 ssiu21: ssiu-17 { 1952 dmas = <&audma0 0x67>, <&audma1 0x68>; 1953 dma-names = "rx", "tx"; 1954 }; 1955 ssiu22: ssiu-18 { 1956 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1957 dma-names = "rx", "tx"; 1958 }; 1959 ssiu23: ssiu-19 { 1960 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1961 dma-names = "rx", "tx"; 1962 }; 1963 ssiu24: ssiu-20 { 1964 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1965 dma-names = "rx", "tx"; 1966 }; 1967 ssiu25: ssiu-21 { 1968 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1969 dma-names = "rx", "tx"; 1970 }; 1971 ssiu26: ssiu-22 { 1972 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1973 dma-names = "rx", "tx"; 1974 }; 1975 ssiu27: ssiu-23 { 1976 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1977 dma-names = "rx", "tx"; 1978 }; 1979 ssiu30: ssiu-24 { 1980 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1981 dma-names = "rx", "tx"; 1982 }; 1983 ssiu31: ssiu-25 { 1984 dmas = <&audma0 0x21>, <&audma1 0x22>; 1985 dma-names = "rx", "tx"; 1986 }; 1987 ssiu32: ssiu-26 { 1988 dmas = <&audma0 0x23>, <&audma1 0x24>; 1989 dma-names = "rx", "tx"; 1990 }; 1991 ssiu33: ssiu-27 { 1992 dmas = <&audma0 0x25>, <&audma1 0x26>; 1993 dma-names = "rx", "tx"; 1994 }; 1995 ssiu34: ssiu-28 { 1996 dmas = <&audma0 0x27>, <&audma1 0x28>; 1997 dma-names = "rx", "tx"; 1998 }; 1999 ssiu35: ssiu-29 { 2000 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2001 dma-names = "rx", "tx"; 2002 }; 2003 ssiu36: ssiu-30 { 2004 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2005 dma-names = "rx", "tx"; 2006 }; 2007 ssiu37: ssiu-31 { 2008 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2009 dma-names = "rx", "tx"; 2010 }; 2011 ssiu40: ssiu-32 { 2012 dmas = <&audma0 0x71>, <&audma1 0x72>; 2013 dma-names = "rx", "tx"; 2014 }; 2015 ssiu41: ssiu-33 { 2016 dmas = <&audma0 0x17>, <&audma1 0x18>; 2017 dma-names = "rx", "tx"; 2018 }; 2019 ssiu42: ssiu-34 { 2020 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2021 dma-names = "rx", "tx"; 2022 }; 2023 ssiu43: ssiu-35 { 2024 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2025 dma-names = "rx", "tx"; 2026 }; 2027 ssiu44: ssiu-36 { 2028 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2029 dma-names = "rx", "tx"; 2030 }; 2031 ssiu45: ssiu-37 { 2032 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2033 dma-names = "rx", "tx"; 2034 }; 2035 ssiu46: ssiu-38 { 2036 dmas = <&audma0 0x31>, <&audma1 0x32>; 2037 dma-names = "rx", "tx"; 2038 }; 2039 ssiu47: ssiu-39 { 2040 dmas = <&audma0 0x33>, <&audma1 0x34>; 2041 dma-names = "rx", "tx"; 2042 }; 2043 ssiu50: ssiu-40 { 2044 dmas = <&audma0 0x73>, <&audma1 0x74>; 2045 dma-names = "rx", "tx"; 2046 }; 2047 ssiu60: ssiu-41 { 2048 dmas = <&audma0 0x75>, <&audma1 0x76>; 2049 dma-names = "rx", "tx"; 2050 }; 2051 ssiu70: ssiu-42 { 2052 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2053 dma-names = "rx", "tx"; 2054 }; 2055 ssiu80: ssiu-43 { 2056 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2057 dma-names = "rx", "tx"; 2058 }; 2059 ssiu90: ssiu-44 { 2060 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2061 dma-names = "rx", "tx"; 2062 }; 2063 ssiu91: ssiu-45 { 2064 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2065 dma-names = "rx", "tx"; 2066 }; 2067 ssiu92: ssiu-46 { 2068 dmas = <&audma0 0x81>, <&audma1 0x82>; 2069 dma-names = "rx", "tx"; 2070 }; 2071 ssiu93: ssiu-47 { 2072 dmas = <&audma0 0x83>, <&audma1 0x84>; 2073 dma-names = "rx", "tx"; 2074 }; 2075 ssiu94: ssiu-48 { 2076 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2077 dma-names = "rx", "tx"; 2078 }; 2079 ssiu95: ssiu-49 { 2080 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2081 dma-names = "rx", "tx"; 2082 }; 2083 ssiu96: ssiu-50 { 2084 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2085 dma-names = "rx", "tx"; 2086 }; 2087 ssiu97: ssiu-51 { 2088 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2089 dma-names = "rx", "tx"; 2090 }; 2091 }; 2092 }; 2093 2094 audma0: dma-controller@ec700000 { 2095 compatible = "renesas,dmac-r8a774a1", 2096 "renesas,rcar-dmac"; 2097 reg = <0 0xec700000 0 0x10000>; 2098 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2115 interrupt-names = "error", 2116 "ch0", "ch1", "ch2", "ch3", 2117 "ch4", "ch5", "ch6", "ch7", 2118 "ch8", "ch9", "ch10", "ch11", 2119 "ch12", "ch13", "ch14", "ch15"; 2120 clocks = <&cpg CPG_MOD 502>; 2121 clock-names = "fck"; 2122 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2123 resets = <&cpg 502>; 2124 #dma-cells = <1>; 2125 dma-channels = <16>; 2126 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2127 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2128 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2129 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2130 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2131 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2132 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2133 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2134 }; 2135 2136 audma1: dma-controller@ec720000 { 2137 compatible = "renesas,dmac-r8a774a1", 2138 "renesas,rcar-dmac"; 2139 reg = <0 0xec720000 0 0x10000>; 2140 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2157 interrupt-names = "error", 2158 "ch0", "ch1", "ch2", "ch3", 2159 "ch4", "ch5", "ch6", "ch7", 2160 "ch8", "ch9", "ch10", "ch11", 2161 "ch12", "ch13", "ch14", "ch15"; 2162 clocks = <&cpg CPG_MOD 501>; 2163 clock-names = "fck"; 2164 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2165 resets = <&cpg 501>; 2166 #dma-cells = <1>; 2167 dma-channels = <16>; 2168 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2169 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2170 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2171 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2172 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2173 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2174 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2175 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2176 }; 2177 2178 xhci0: usb@ee000000 { 2179 compatible = "renesas,xhci-r8a774a1", 2180 "renesas,rcar-gen3-xhci"; 2181 reg = <0 0xee000000 0 0xc00>; 2182 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2183 clocks = <&cpg CPG_MOD 328>; 2184 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2185 resets = <&cpg 328>; 2186 status = "disabled"; 2187 }; 2188 2189 usb3_peri0: usb@ee020000 { 2190 compatible = "renesas,r8a774a1-usb3-peri", 2191 "renesas,rcar-gen3-usb3-peri"; 2192 reg = <0 0xee020000 0 0x400>; 2193 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2194 clocks = <&cpg CPG_MOD 328>; 2195 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2196 resets = <&cpg 328>; 2197 status = "disabled"; 2198 }; 2199 2200 ohci0: usb@ee080000 { 2201 compatible = "generic-ohci"; 2202 reg = <0 0xee080000 0 0x100>; 2203 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2204 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2205 phys = <&usb2_phy0 1>; 2206 phy-names = "usb"; 2207 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2208 resets = <&cpg 703>, <&cpg 704>; 2209 status = "disabled"; 2210 }; 2211 2212 ohci1: usb@ee0a0000 { 2213 compatible = "generic-ohci"; 2214 reg = <0 0xee0a0000 0 0x100>; 2215 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&cpg CPG_MOD 702>; 2217 phys = <&usb2_phy1 1>; 2218 phy-names = "usb"; 2219 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2220 resets = <&cpg 702>; 2221 status = "disabled"; 2222 }; 2223 2224 ehci0: usb@ee080100 { 2225 compatible = "generic-ehci"; 2226 reg = <0 0xee080100 0 0x100>; 2227 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2229 phys = <&usb2_phy0 2>; 2230 phy-names = "usb"; 2231 companion = <&ohci0>; 2232 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2233 resets = <&cpg 703>, <&cpg 704>; 2234 status = "disabled"; 2235 }; 2236 2237 ehci1: usb@ee0a0100 { 2238 compatible = "generic-ehci"; 2239 reg = <0 0xee0a0100 0 0x100>; 2240 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2241 clocks = <&cpg CPG_MOD 702>; 2242 phys = <&usb2_phy1 2>; 2243 phy-names = "usb"; 2244 companion = <&ohci1>; 2245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2246 resets = <&cpg 702>; 2247 status = "disabled"; 2248 }; 2249 2250 usb2_phy0: usb-phy@ee080200 { 2251 compatible = "renesas,usb2-phy-r8a774a1", 2252 "renesas,rcar-gen3-usb2-phy"; 2253 reg = <0 0xee080200 0 0x700>; 2254 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2256 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2257 resets = <&cpg 703>, <&cpg 704>; 2258 #phy-cells = <1>; 2259 status = "disabled"; 2260 }; 2261 2262 usb2_phy1: usb-phy@ee0a0200 { 2263 compatible = "renesas,usb2-phy-r8a774a1", 2264 "renesas,rcar-gen3-usb2-phy"; 2265 reg = <0 0xee0a0200 0 0x700>; 2266 clocks = <&cpg CPG_MOD 702>; 2267 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2268 resets = <&cpg 702>; 2269 #phy-cells = <1>; 2270 status = "disabled"; 2271 }; 2272 2273 sdhi0: mmc@ee100000 { 2274 compatible = "renesas,sdhi-r8a774a1", 2275 "renesas,rcar-gen3-sdhi"; 2276 reg = <0 0xee100000 0 0x2000>; 2277 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2278 clocks = <&cpg CPG_MOD 314>; 2279 max-frequency = <200000000>; 2280 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2281 resets = <&cpg 314>; 2282 status = "disabled"; 2283 }; 2284 2285 sdhi1: mmc@ee120000 { 2286 compatible = "renesas,sdhi-r8a774a1", 2287 "renesas,rcar-gen3-sdhi"; 2288 reg = <0 0xee120000 0 0x2000>; 2289 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2290 clocks = <&cpg CPG_MOD 313>; 2291 max-frequency = <200000000>; 2292 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2293 resets = <&cpg 313>; 2294 status = "disabled"; 2295 }; 2296 2297 sdhi2: mmc@ee140000 { 2298 compatible = "renesas,sdhi-r8a774a1", 2299 "renesas,rcar-gen3-sdhi"; 2300 reg = <0 0xee140000 0 0x2000>; 2301 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&cpg CPG_MOD 312>; 2303 max-frequency = <200000000>; 2304 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2305 resets = <&cpg 312>; 2306 status = "disabled"; 2307 }; 2308 2309 sdhi3: mmc@ee160000 { 2310 compatible = "renesas,sdhi-r8a774a1", 2311 "renesas,rcar-gen3-sdhi"; 2312 reg = <0 0xee160000 0 0x2000>; 2313 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2314 clocks = <&cpg CPG_MOD 311>; 2315 max-frequency = <200000000>; 2316 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2317 resets = <&cpg 311>; 2318 status = "disabled"; 2319 }; 2320 2321 gic: interrupt-controller@f1010000 { 2322 compatible = "arm,gic-400"; 2323 #interrupt-cells = <3>; 2324 #address-cells = <0>; 2325 interrupt-controller; 2326 reg = <0x0 0xf1010000 0 0x1000>, 2327 <0x0 0xf1020000 0 0x20000>, 2328 <0x0 0xf1040000 0 0x20000>, 2329 <0x0 0xf1060000 0 0x20000>; 2330 interrupts = <GIC_PPI 9 2331 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2332 clocks = <&cpg CPG_MOD 408>; 2333 clock-names = "clk"; 2334 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2335 resets = <&cpg 408>; 2336 }; 2337 2338 pciec0: pcie@fe000000 { 2339 compatible = "renesas,pcie-r8a774a1", 2340 "renesas,pcie-rcar-gen3"; 2341 reg = <0 0xfe000000 0 0x80000>; 2342 #address-cells = <3>; 2343 #size-cells = <2>; 2344 bus-range = <0x00 0xff>; 2345 device_type = "pci"; 2346 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2347 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2348 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2349 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2350 /* Map all possible DDR as inbound ranges */ 2351 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2352 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2355 #interrupt-cells = <1>; 2356 interrupt-map-mask = <0 0 0 0>; 2357 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2358 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2359 clock-names = "pcie", "pcie_bus"; 2360 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2361 resets = <&cpg 319>; 2362 status = "disabled"; 2363 }; 2364 2365 pciec1: pcie@ee800000 { 2366 compatible = "renesas,pcie-r8a774a1", 2367 "renesas,pcie-rcar-gen3"; 2368 reg = <0 0xee800000 0 0x80000>; 2369 #address-cells = <3>; 2370 #size-cells = <2>; 2371 bus-range = <0x00 0xff>; 2372 device_type = "pci"; 2373 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2374 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2375 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2376 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2377 /* Map all possible DDR as inbound ranges */ 2378 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2379 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2382 #interrupt-cells = <1>; 2383 interrupt-map-mask = <0 0 0 0>; 2384 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2385 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2386 clock-names = "pcie", "pcie_bus"; 2387 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2388 resets = <&cpg 318>; 2389 status = "disabled"; 2390 }; 2391 2392 pciec0_ep: pcie-ep@fe000000 { 2393 compatible = "renesas,r8a774a1-pcie-ep", 2394 "renesas,rcar-gen3-pcie-ep"; 2395 reg = <0x0 0xfe000000 0 0x80000>, 2396 <0x0 0xfe100000 0 0x100000>, 2397 <0x0 0xfe200000 0 0x200000>, 2398 <0x0 0x30000000 0 0x8000000>, 2399 <0x0 0x38000000 0 0x8000000>; 2400 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2401 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2404 clocks = <&cpg CPG_MOD 319>; 2405 clock-names = "pcie"; 2406 resets = <&cpg 319>; 2407 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2408 status = "disabled"; 2409 }; 2410 2411 pciec1_ep: pcie-ep@ee800000 { 2412 compatible = "renesas,r8a774a1-pcie-ep", 2413 "renesas,rcar-gen3-pcie-ep"; 2414 reg = <0x0 0xee800000 0 0x80000>, 2415 <0x0 0xee900000 0 0x100000>, 2416 <0x0 0xeea00000 0 0x200000>, 2417 <0x0 0xc0000000 0 0x8000000>, 2418 <0x0 0xc8000000 0 0x8000000>; 2419 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2420 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2421 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2423 clocks = <&cpg CPG_MOD 318>; 2424 clock-names = "pcie"; 2425 resets = <&cpg 318>; 2426 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2427 status = "disabled"; 2428 }; 2429 2430 fdp1@fe940000 { 2431 compatible = "renesas,fdp1"; 2432 reg = <0 0xfe940000 0 0x2400>; 2433 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2434 clocks = <&cpg CPG_MOD 119>; 2435 power-domains = <&sysc R8A774A1_PD_A3VC>; 2436 resets = <&cpg 119>; 2437 renesas,fcp = <&fcpf0>; 2438 }; 2439 2440 fcpf0: fcp@fe950000 { 2441 compatible = "renesas,fcpf"; 2442 reg = <0 0xfe950000 0 0x200>; 2443 clocks = <&cpg CPG_MOD 615>; 2444 power-domains = <&sysc R8A774A1_PD_A3VC>; 2445 resets = <&cpg 615>; 2446 }; 2447 2448 fcpvb0: fcp@fe96f000 { 2449 compatible = "renesas,fcpv"; 2450 reg = <0 0xfe96f000 0 0x200>; 2451 clocks = <&cpg CPG_MOD 607>; 2452 power-domains = <&sysc R8A774A1_PD_A3VC>; 2453 resets = <&cpg 607>; 2454 }; 2455 2456 fcpvd0: fcp@fea27000 { 2457 compatible = "renesas,fcpv"; 2458 reg = <0 0xfea27000 0 0x200>; 2459 clocks = <&cpg CPG_MOD 603>; 2460 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2461 resets = <&cpg 603>; 2462 iommus = <&ipmmu_vi0 8>; 2463 }; 2464 2465 fcpvd1: fcp@fea2f000 { 2466 compatible = "renesas,fcpv"; 2467 reg = <0 0xfea2f000 0 0x200>; 2468 clocks = <&cpg CPG_MOD 602>; 2469 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2470 resets = <&cpg 602>; 2471 iommus = <&ipmmu_vi0 9>; 2472 }; 2473 2474 fcpvd2: fcp@fea37000 { 2475 compatible = "renesas,fcpv"; 2476 reg = <0 0xfea37000 0 0x200>; 2477 clocks = <&cpg CPG_MOD 601>; 2478 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2479 resets = <&cpg 601>; 2480 iommus = <&ipmmu_vi0 10>; 2481 }; 2482 2483 fcpvi0: fcp@fe9af000 { 2484 compatible = "renesas,fcpv"; 2485 reg = <0 0xfe9af000 0 0x200>; 2486 clocks = <&cpg CPG_MOD 611>; 2487 power-domains = <&sysc R8A774A1_PD_A3VC>; 2488 resets = <&cpg 611>; 2489 iommus = <&ipmmu_vc0 19>; 2490 }; 2491 2492 vspb: vsp@fe960000 { 2493 compatible = "renesas,vsp2"; 2494 reg = <0 0xfe960000 0 0x8000>; 2495 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2496 clocks = <&cpg CPG_MOD 626>; 2497 power-domains = <&sysc R8A774A1_PD_A3VC>; 2498 resets = <&cpg 626>; 2499 2500 renesas,fcp = <&fcpvb0>; 2501 }; 2502 2503 vspd0: vsp@fea20000 { 2504 compatible = "renesas,vsp2"; 2505 reg = <0 0xfea20000 0 0x5000>; 2506 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2507 clocks = <&cpg CPG_MOD 623>; 2508 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2509 resets = <&cpg 623>; 2510 2511 renesas,fcp = <&fcpvd0>; 2512 }; 2513 2514 vspd1: vsp@fea28000 { 2515 compatible = "renesas,vsp2"; 2516 reg = <0 0xfea28000 0 0x5000>; 2517 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2518 clocks = <&cpg CPG_MOD 622>; 2519 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2520 resets = <&cpg 622>; 2521 2522 renesas,fcp = <&fcpvd1>; 2523 }; 2524 2525 vspd2: vsp@fea30000 { 2526 compatible = "renesas,vsp2"; 2527 reg = <0 0xfea30000 0 0x5000>; 2528 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2529 clocks = <&cpg CPG_MOD 621>; 2530 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2531 resets = <&cpg 621>; 2532 2533 renesas,fcp = <&fcpvd2>; 2534 }; 2535 2536 vspi0: vsp@fe9a0000 { 2537 compatible = "renesas,vsp2"; 2538 reg = <0 0xfe9a0000 0 0x8000>; 2539 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2540 clocks = <&cpg CPG_MOD 631>; 2541 power-domains = <&sysc R8A774A1_PD_A3VC>; 2542 resets = <&cpg 631>; 2543 2544 renesas,fcp = <&fcpvi0>; 2545 }; 2546 2547 csi20: csi2@fea80000 { 2548 compatible = "renesas,r8a774a1-csi2"; 2549 reg = <0 0xfea80000 0 0x10000>; 2550 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2551 clocks = <&cpg CPG_MOD 714>; 2552 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2553 resets = <&cpg 714>; 2554 status = "disabled"; 2555 2556 ports { 2557 #address-cells = <1>; 2558 #size-cells = <0>; 2559 2560 port@1 { 2561 #address-cells = <1>; 2562 #size-cells = <0>; 2563 2564 reg = <1>; 2565 2566 csi20vin0: endpoint@0 { 2567 reg = <0>; 2568 remote-endpoint = <&vin0csi20>; 2569 }; 2570 csi20vin1: endpoint@1 { 2571 reg = <1>; 2572 remote-endpoint = <&vin1csi20>; 2573 }; 2574 csi20vin2: endpoint@2 { 2575 reg = <2>; 2576 remote-endpoint = <&vin2csi20>; 2577 }; 2578 csi20vin3: endpoint@3 { 2579 reg = <3>; 2580 remote-endpoint = <&vin3csi20>; 2581 }; 2582 csi20vin4: endpoint@4 { 2583 reg = <4>; 2584 remote-endpoint = <&vin4csi20>; 2585 }; 2586 csi20vin5: endpoint@5 { 2587 reg = <5>; 2588 remote-endpoint = <&vin5csi20>; 2589 }; 2590 csi20vin6: endpoint@6 { 2591 reg = <6>; 2592 remote-endpoint = <&vin6csi20>; 2593 }; 2594 csi20vin7: endpoint@7 { 2595 reg = <7>; 2596 remote-endpoint = <&vin7csi20>; 2597 }; 2598 }; 2599 }; 2600 }; 2601 2602 csi40: csi2@feaa0000 { 2603 compatible = "renesas,r8a774a1-csi2"; 2604 reg = <0 0xfeaa0000 0 0x10000>; 2605 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2606 clocks = <&cpg CPG_MOD 716>; 2607 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2608 resets = <&cpg 716>; 2609 status = "disabled"; 2610 2611 ports { 2612 #address-cells = <1>; 2613 #size-cells = <0>; 2614 2615 port@1 { 2616 #address-cells = <1>; 2617 #size-cells = <0>; 2618 2619 reg = <1>; 2620 2621 csi40vin0: endpoint@0 { 2622 reg = <0>; 2623 remote-endpoint = <&vin0csi40>; 2624 }; 2625 csi40vin1: endpoint@1 { 2626 reg = <1>; 2627 remote-endpoint = <&vin1csi40>; 2628 }; 2629 csi40vin2: endpoint@2 { 2630 reg = <2>; 2631 remote-endpoint = <&vin2csi40>; 2632 }; 2633 csi40vin3: endpoint@3 { 2634 reg = <3>; 2635 remote-endpoint = <&vin3csi40>; 2636 }; 2637 csi40vin4: endpoint@4 { 2638 reg = <4>; 2639 remote-endpoint = <&vin4csi40>; 2640 }; 2641 csi40vin5: endpoint@5 { 2642 reg = <5>; 2643 remote-endpoint = <&vin5csi40>; 2644 }; 2645 csi40vin6: endpoint@6 { 2646 reg = <6>; 2647 remote-endpoint = <&vin6csi40>; 2648 }; 2649 csi40vin7: endpoint@7 { 2650 reg = <7>; 2651 remote-endpoint = <&vin7csi40>; 2652 }; 2653 }; 2654 2655 }; 2656 }; 2657 2658 hdmi0: hdmi@fead0000 { 2659 compatible = "renesas,r8a774a1-hdmi", 2660 "renesas,rcar-gen3-hdmi"; 2661 reg = <0 0xfead0000 0 0x10000>; 2662 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2663 clocks = <&cpg CPG_MOD 729>, 2664 <&cpg CPG_CORE R8A774A1_CLK_HDMI>; 2665 clock-names = "iahb", "isfr"; 2666 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2667 resets = <&cpg 729>; 2668 status = "disabled"; 2669 2670 ports { 2671 #address-cells = <1>; 2672 #size-cells = <0>; 2673 port@0 { 2674 reg = <0>; 2675 dw_hdmi0_in: endpoint { 2676 remote-endpoint = <&du_out_hdmi0>; 2677 }; 2678 }; 2679 port@1 { 2680 reg = <1>; 2681 }; 2682 port@2 { 2683 /* HDMI sound */ 2684 reg = <2>; 2685 }; 2686 }; 2687 }; 2688 2689 du: display@feb00000 { 2690 compatible = "renesas,du-r8a774a1"; 2691 reg = <0 0xfeb00000 0 0x70000>; 2692 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2695 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2696 <&cpg CPG_MOD 722>; 2697 clock-names = "du.0", "du.1", "du.2"; 2698 resets = <&cpg 724>, <&cpg 722>; 2699 reset-names = "du.0", "du.2"; 2700 status = "disabled"; 2701 2702 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2703 2704 ports { 2705 #address-cells = <1>; 2706 #size-cells = <0>; 2707 2708 port@0 { 2709 reg = <0>; 2710 du_out_rgb: endpoint { 2711 }; 2712 }; 2713 port@1 { 2714 reg = <1>; 2715 du_out_hdmi0: endpoint { 2716 remote-endpoint = <&dw_hdmi0_in>; 2717 }; 2718 }; 2719 port@2 { 2720 reg = <2>; 2721 du_out_lvds0: endpoint { 2722 remote-endpoint = <&lvds0_in>; 2723 }; 2724 }; 2725 }; 2726 }; 2727 2728 lvds0: lvds@feb90000 { 2729 compatible = "renesas,r8a774a1-lvds"; 2730 reg = <0 0xfeb90000 0 0x14>; 2731 clocks = <&cpg CPG_MOD 727>; 2732 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2733 resets = <&cpg 727>; 2734 status = "disabled"; 2735 2736 ports { 2737 #address-cells = <1>; 2738 #size-cells = <0>; 2739 2740 port@0 { 2741 reg = <0>; 2742 lvds0_in: endpoint { 2743 remote-endpoint = <&du_out_lvds0>; 2744 }; 2745 }; 2746 port@1 { 2747 reg = <1>; 2748 lvds0_out: endpoint { 2749 }; 2750 }; 2751 }; 2752 }; 2753 2754 prr: chipid@fff00044 { 2755 compatible = "renesas,prr"; 2756 reg = <0 0xfff00044 0 4>; 2757 }; 2758 }; 2759 2760 thermal-zones { 2761 sensor_thermal1: sensor-thermal1 { 2762 polling-delay-passive = <250>; 2763 polling-delay = <1000>; 2764 thermal-sensors = <&tsc 0>; 2765 sustainable-power = <3874>; 2766 2767 trips { 2768 sensor1_crit: sensor1-crit { 2769 temperature = <120000>; 2770 hysteresis = <1000>; 2771 type = "critical"; 2772 }; 2773 }; 2774 }; 2775 2776 sensor_thermal2: sensor-thermal2 { 2777 polling-delay-passive = <250>; 2778 polling-delay = <1000>; 2779 thermal-sensors = <&tsc 1>; 2780 sustainable-power = <3874>; 2781 2782 trips { 2783 sensor2_crit: sensor2-crit { 2784 temperature = <120000>; 2785 hysteresis = <1000>; 2786 type = "critical"; 2787 }; 2788 }; 2789 }; 2790 2791 sensor_thermal3: sensor-thermal3 { 2792 polling-delay-passive = <250>; 2793 polling-delay = <1000>; 2794 thermal-sensors = <&tsc 2>; 2795 sustainable-power = <3874>; 2796 2797 cooling-maps { 2798 map0 { 2799 trip = <&target>; 2800 cooling-device = <&a57_0 0 2>; 2801 contribution = <1024>; 2802 }; 2803 map1 { 2804 trip = <&target>; 2805 cooling-device = <&a53_0 0 2>; 2806 contribution = <1024>; 2807 }; 2808 }; 2809 trips { 2810 target: trip-point1 { 2811 temperature = <100000>; 2812 hysteresis = <1000>; 2813 type = "passive"; 2814 }; 2815 2816 sensor3_crit: sensor3-crit { 2817 temperature = <120000>; 2818 hysteresis = <1000>; 2819 type = "critical"; 2820 }; 2821 }; 2822 }; 2823 }; 2824 2825 timer { 2826 compatible = "arm,armv8-timer"; 2827 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2828 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2829 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2830 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2831 }; 2832 2833 /* External USB clocks - can be overridden by the board */ 2834 usb3s0_clk: usb3s0 { 2835 compatible = "fixed-clock"; 2836 #clock-cells = <0>; 2837 clock-frequency = <0>; 2838 }; 2839 2840 usb_extal_clk: usb_extal { 2841 compatible = "fixed-clock"; 2842 #clock-cells = <0>; 2843 clock-frequency = <0>; 2844 }; 2845}; 2846