1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: cpu0-opp-table { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 power-domain@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 }; 254 power-domain@PX30_PD_SDCARD { 255 reg = <PX30_PD_SDCARD>; 256 clocks = <&cru HCLK_SDMMC>, 257 <&cru SCLK_SDMMC>; 258 pm_qos = <&qos_sdmmc>; 259 }; 260 power-domain@PX30_PD_GMAC { 261 reg = <PX30_PD_GMAC>; 262 clocks = <&cru ACLK_GMAC>, 263 <&cru PCLK_GMAC>, 264 <&cru SCLK_MAC_REF>, 265 <&cru SCLK_GMAC_RX_TX>; 266 pm_qos = <&qos_gmac>; 267 }; 268 power-domain@PX30_PD_MMC_NAND { 269 reg = <PX30_PD_MMC_NAND>; 270 clocks = <&cru HCLK_NANDC>, 271 <&cru HCLK_EMMC>, 272 <&cru HCLK_SDIO>, 273 <&cru HCLK_SFC>, 274 <&cru SCLK_EMMC>, 275 <&cru SCLK_NANDC>, 276 <&cru SCLK_SDIO>, 277 <&cru SCLK_SFC>; 278 pm_qos = <&qos_emmc>, <&qos_nand>, 279 <&qos_sdio>, <&qos_sfc>; 280 }; 281 power-domain@PX30_PD_VPU { 282 reg = <PX30_PD_VPU>; 283 clocks = <&cru ACLK_VPU>, 284 <&cru HCLK_VPU>, 285 <&cru SCLK_CORE_VPU>; 286 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 287 }; 288 power-domain@PX30_PD_VO { 289 reg = <PX30_PD_VO>; 290 clocks = <&cru ACLK_RGA>, 291 <&cru ACLK_VOPB>, 292 <&cru ACLK_VOPL>, 293 <&cru DCLK_VOPB>, 294 <&cru DCLK_VOPL>, 295 <&cru HCLK_RGA>, 296 <&cru HCLK_VOPB>, 297 <&cru HCLK_VOPL>, 298 <&cru PCLK_MIPI_DSI>, 299 <&cru SCLK_RGA_CORE>, 300 <&cru SCLK_VOPB_PWM>; 301 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 302 <&qos_vop_m0>, <&qos_vop_m1>; 303 }; 304 power-domain@PX30_PD_VI { 305 reg = <PX30_PD_VI>; 306 clocks = <&cru ACLK_CIF>, 307 <&cru ACLK_ISP>, 308 <&cru HCLK_CIF>, 309 <&cru HCLK_ISP>, 310 <&cru SCLK_ISP>; 311 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 312 <&qos_isp_wr>, <&qos_isp_m1>, 313 <&qos_vip>; 314 }; 315 power-domain@PX30_PD_GPU { 316 reg = <PX30_PD_GPU>; 317 clocks = <&cru SCLK_GPU>; 318 pm_qos = <&qos_gpu>; 319 }; 320 }; 321 }; 322 323 pmugrf: syscon@ff010000 { 324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 325 reg = <0x0 0xff010000 0x0 0x1000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 pmu_io_domains: io-domains { 330 compatible = "rockchip,px30-pmu-io-voltage-domain"; 331 status = "disabled"; 332 }; 333 334 reboot-mode { 335 compatible = "syscon-reboot-mode"; 336 offset = <0x200>; 337 mode-bootloader = <BOOT_BL_DOWNLOAD>; 338 mode-fastboot = <BOOT_FASTBOOT>; 339 mode-loader = <BOOT_BL_DOWNLOAD>; 340 mode-normal = <BOOT_NORMAL>; 341 mode-recovery = <BOOT_RECOVERY>; 342 }; 343 }; 344 345 uart0: serial@ff030000 { 346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 347 reg = <0x0 0xff030000 0x0 0x100>; 348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 350 clock-names = "baudclk", "apb_pclk"; 351 dmas = <&dmac 0>, <&dmac 1>; 352 dma-names = "tx", "rx"; 353 reg-shift = <2>; 354 reg-io-width = <4>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 357 status = "disabled"; 358 }; 359 360 i2s1_2ch: i2s@ff070000 { 361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 362 reg = <0x0 0xff070000 0x0 0x1000>; 363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 365 clock-names = "i2s_clk", "i2s_hclk"; 366 dmas = <&dmac 18>, <&dmac 19>; 367 dma-names = "tx", "rx"; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 370 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 371 #sound-dai-cells = <0>; 372 status = "disabled"; 373 }; 374 375 i2s2_2ch: i2s@ff080000 { 376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 377 reg = <0x0 0xff080000 0x0 0x1000>; 378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 380 clock-names = "i2s_clk", "i2s_hclk"; 381 dmas = <&dmac 20>, <&dmac 21>; 382 dma-names = "tx", "rx"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 385 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 386 #sound-dai-cells = <0>; 387 status = "disabled"; 388 }; 389 390 gic: interrupt-controller@ff131000 { 391 compatible = "arm,gic-400"; 392 #interrupt-cells = <3>; 393 #address-cells = <0>; 394 interrupt-controller; 395 reg = <0x0 0xff131000 0 0x1000>, 396 <0x0 0xff132000 0 0x2000>, 397 <0x0 0xff134000 0 0x2000>, 398 <0x0 0xff136000 0 0x2000>; 399 interrupts = <GIC_PPI 9 400 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 401 }; 402 403 grf: syscon@ff140000 { 404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 405 reg = <0x0 0xff140000 0x0 0x1000>; 406 #address-cells = <1>; 407 #size-cells = <1>; 408 409 io_domains: io-domains { 410 compatible = "rockchip,px30-io-voltage-domain"; 411 status = "disabled"; 412 }; 413 414 lvds: lvds { 415 compatible = "rockchip,px30-lvds"; 416 phys = <&dsi_dphy>; 417 phy-names = "dphy"; 418 rockchip,grf = <&grf>; 419 rockchip,output = "lvds"; 420 status = "disabled"; 421 422 ports { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 426 port@0 { 427 reg = <0>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 431 lvds_vopb_in: endpoint@0 { 432 reg = <0>; 433 remote-endpoint = <&vopb_out_lvds>; 434 }; 435 436 lvds_vopl_in: endpoint@1 { 437 reg = <1>; 438 remote-endpoint = <&vopl_out_lvds>; 439 }; 440 }; 441 }; 442 }; 443 }; 444 445 uart1: serial@ff158000 { 446 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 447 reg = <0x0 0xff158000 0x0 0x100>; 448 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 450 clock-names = "baudclk", "apb_pclk"; 451 dmas = <&dmac 2>, <&dmac 3>; 452 dma-names = "tx", "rx"; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 457 status = "disabled"; 458 }; 459 460 uart2: serial@ff160000 { 461 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 462 reg = <0x0 0xff160000 0x0 0x100>; 463 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 465 clock-names = "baudclk", "apb_pclk"; 466 dmas = <&dmac 4>, <&dmac 5>; 467 dma-names = "tx", "rx"; 468 reg-shift = <2>; 469 reg-io-width = <4>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&uart2m0_xfer>; 472 status = "disabled"; 473 }; 474 475 uart3: serial@ff168000 { 476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 477 reg = <0x0 0xff168000 0x0 0x100>; 478 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 480 clock-names = "baudclk", "apb_pclk"; 481 dmas = <&dmac 6>, <&dmac 7>; 482 dma-names = "tx", "rx"; 483 reg-shift = <2>; 484 reg-io-width = <4>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 487 status = "disabled"; 488 }; 489 490 uart4: serial@ff170000 { 491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 492 reg = <0x0 0xff170000 0x0 0x100>; 493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 495 clock-names = "baudclk", "apb_pclk"; 496 dmas = <&dmac 8>, <&dmac 9>; 497 dma-names = "tx", "rx"; 498 reg-shift = <2>; 499 reg-io-width = <4>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 502 status = "disabled"; 503 }; 504 505 uart5: serial@ff178000 { 506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 507 reg = <0x0 0xff178000 0x0 0x100>; 508 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 510 clock-names = "baudclk", "apb_pclk"; 511 dmas = <&dmac 10>, <&dmac 11>; 512 dma-names = "tx", "rx"; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 517 status = "disabled"; 518 }; 519 520 i2c0: i2c@ff180000 { 521 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 522 reg = <0x0 0xff180000 0x0 0x1000>; 523 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 524 clock-names = "i2c", "pclk"; 525 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c0_xfer>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 i2c1: i2c@ff190000 { 534 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 535 reg = <0x0 0xff190000 0x0 0x1000>; 536 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 537 clock-names = "i2c", "pclk"; 538 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c1_xfer>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c2: i2c@ff1a0000 { 547 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 548 reg = <0x0 0xff1a0000 0x0 0x1000>; 549 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 550 clock-names = "i2c", "pclk"; 551 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c2_xfer>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 i2c3: i2c@ff1b0000 { 560 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 561 reg = <0x0 0xff1b0000 0x0 0x1000>; 562 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 563 clock-names = "i2c", "pclk"; 564 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&i2c3_xfer>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 spi0: spi@ff1d0000 { 573 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 574 reg = <0x0 0xff1d0000 0x0 0x1000>; 575 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 577 clock-names = "spiclk", "apb_pclk"; 578 dmas = <&dmac 12>, <&dmac 13>; 579 dma-names = "tx", "rx"; 580 num-cs = <2>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 588 spi1: spi@ff1d8000 { 589 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 590 reg = <0x0 0xff1d8000 0x0 0x1000>; 591 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 593 clock-names = "spiclk", "apb_pclk"; 594 dmas = <&dmac 14>, <&dmac 15>; 595 dma-names = "tx", "rx"; 596 num-cs = <2>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 wdt: watchdog@ff1e0000 { 605 compatible = "snps,dw-wdt"; 606 reg = <0x0 0xff1e0000 0x0 0x100>; 607 clocks = <&cru PCLK_WDT_NS>; 608 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 609 status = "disabled"; 610 }; 611 612 pwm0: pwm@ff200000 { 613 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 614 reg = <0x0 0xff200000 0x0 0x10>; 615 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 616 clock-names = "pwm", "pclk"; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pwm0_pin>; 619 #pwm-cells = <3>; 620 status = "disabled"; 621 }; 622 623 pwm1: pwm@ff200010 { 624 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 625 reg = <0x0 0xff200010 0x0 0x10>; 626 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 627 clock-names = "pwm", "pclk"; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&pwm1_pin>; 630 #pwm-cells = <3>; 631 status = "disabled"; 632 }; 633 634 pwm2: pwm@ff200020 { 635 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 636 reg = <0x0 0xff200020 0x0 0x10>; 637 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 638 clock-names = "pwm", "pclk"; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&pwm2_pin>; 641 #pwm-cells = <3>; 642 status = "disabled"; 643 }; 644 645 pwm3: pwm@ff200030 { 646 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 647 reg = <0x0 0xff200030 0x0 0x10>; 648 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 649 clock-names = "pwm", "pclk"; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&pwm3_pin>; 652 #pwm-cells = <3>; 653 status = "disabled"; 654 }; 655 656 pwm4: pwm@ff208000 { 657 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 658 reg = <0x0 0xff208000 0x0 0x10>; 659 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 660 clock-names = "pwm", "pclk"; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pwm4_pin>; 663 #pwm-cells = <3>; 664 status = "disabled"; 665 }; 666 667 pwm5: pwm@ff208010 { 668 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 669 reg = <0x0 0xff208010 0x0 0x10>; 670 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 671 clock-names = "pwm", "pclk"; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pwm5_pin>; 674 #pwm-cells = <3>; 675 status = "disabled"; 676 }; 677 678 pwm6: pwm@ff208020 { 679 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 680 reg = <0x0 0xff208020 0x0 0x10>; 681 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 682 clock-names = "pwm", "pclk"; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pwm6_pin>; 685 #pwm-cells = <3>; 686 status = "disabled"; 687 }; 688 689 pwm7: pwm@ff208030 { 690 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 691 reg = <0x0 0xff208030 0x0 0x10>; 692 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 693 clock-names = "pwm", "pclk"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&pwm7_pin>; 696 #pwm-cells = <3>; 697 status = "disabled"; 698 }; 699 700 rktimer: timer@ff210000 { 701 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 702 reg = <0x0 0xff210000 0x0 0x1000>; 703 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 705 clock-names = "pclk", "timer"; 706 }; 707 708 amba: bus { 709 compatible = "simple-bus"; 710 #address-cells = <2>; 711 #size-cells = <2>; 712 ranges; 713 714 dmac: dmac@ff240000 { 715 compatible = "arm,pl330", "arm,primecell"; 716 reg = <0x0 0xff240000 0x0 0x4000>; 717 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 719 arm,pl330-periph-burst; 720 clocks = <&cru ACLK_DMAC>; 721 clock-names = "apb_pclk"; 722 #dma-cells = <1>; 723 }; 724 }; 725 726 tsadc: tsadc@ff280000 { 727 compatible = "rockchip,px30-tsadc"; 728 reg = <0x0 0xff280000 0x0 0x100>; 729 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 730 assigned-clocks = <&cru SCLK_TSADC>; 731 assigned-clock-rates = <50000>; 732 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 733 clock-names = "tsadc", "apb_pclk"; 734 resets = <&cru SRST_TSADC>; 735 reset-names = "tsadc-apb"; 736 rockchip,grf = <&grf>; 737 rockchip,hw-tshut-temp = <120000>; 738 pinctrl-names = "init", "default", "sleep"; 739 pinctrl-0 = <&tsadc_otp_pin>; 740 pinctrl-1 = <&tsadc_otp_out>; 741 pinctrl-2 = <&tsadc_otp_pin>; 742 #thermal-sensor-cells = <1>; 743 status = "disabled"; 744 }; 745 746 saradc: saradc@ff288000 { 747 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 748 reg = <0x0 0xff288000 0x0 0x100>; 749 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 750 #io-channel-cells = <1>; 751 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 752 clock-names = "saradc", "apb_pclk"; 753 resets = <&cru SRST_SARADC_P>; 754 reset-names = "saradc-apb"; 755 status = "disabled"; 756 }; 757 758 otp: nvmem@ff290000 { 759 compatible = "rockchip,px30-otp"; 760 reg = <0x0 0xff290000 0x0 0x4000>; 761 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 762 <&cru PCLK_OTP_PHY>; 763 clock-names = "otp", "apb_pclk", "phy"; 764 resets = <&cru SRST_OTP_PHY>; 765 reset-names = "phy"; 766 #address-cells = <1>; 767 #size-cells = <1>; 768 769 /* Data cells */ 770 cpu_id: id@7 { 771 reg = <0x07 0x10>; 772 }; 773 cpu_leakage: cpu-leakage@17 { 774 reg = <0x17 0x1>; 775 }; 776 performance: performance@1e { 777 reg = <0x1e 0x1>; 778 bits = <4 3>; 779 }; 780 }; 781 782 cru: clock-controller@ff2b0000 { 783 compatible = "rockchip,px30-cru"; 784 reg = <0x0 0xff2b0000 0x0 0x1000>; 785 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 786 clock-names = "xin24m", "gpll"; 787 rockchip,grf = <&grf>; 788 #clock-cells = <1>; 789 #reset-cells = <1>; 790 791 assigned-clocks = <&cru PLL_NPLL>, 792 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 793 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 794 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 795 796 assigned-clock-rates = <1188000000>, 797 <200000000>, <200000000>, 798 <150000000>, <150000000>, 799 <100000000>, <200000000>; 800 }; 801 802 pmucru: clock-controller@ff2bc000 { 803 compatible = "rockchip,px30-pmucru"; 804 reg = <0x0 0xff2bc000 0x0 0x1000>; 805 clocks = <&xin24m>; 806 clock-names = "xin24m"; 807 rockchip,grf = <&grf>; 808 #clock-cells = <1>; 809 #reset-cells = <1>; 810 811 assigned-clocks = 812 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 813 <&pmucru SCLK_WIFI_PMU>; 814 assigned-clock-rates = 815 <1200000000>, <100000000>, 816 <26000000>; 817 }; 818 819 usb2phy_grf: syscon@ff2c0000 { 820 compatible = "rockchip,px30-usb2phy-grf", "syscon", 821 "simple-mfd"; 822 reg = <0x0 0xff2c0000 0x0 0x10000>; 823 #address-cells = <1>; 824 #size-cells = <1>; 825 826 u2phy: usb2-phy@100 { 827 compatible = "rockchip,px30-usb2phy"; 828 reg = <0x100 0x20>; 829 clocks = <&pmucru SCLK_USBPHY_REF>; 830 clock-names = "phyclk"; 831 #clock-cells = <0>; 832 assigned-clocks = <&cru USB480M>; 833 assigned-clock-parents = <&u2phy>; 834 clock-output-names = "usb480m_phy"; 835 status = "disabled"; 836 837 u2phy_host: host-port { 838 #phy-cells = <0>; 839 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "linestate"; 841 status = "disabled"; 842 }; 843 844 u2phy_otg: otg-port { 845 #phy-cells = <0>; 846 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-names = "otg-bvalid", "otg-id", 850 "linestate"; 851 status = "disabled"; 852 }; 853 }; 854 }; 855 856 dsi_dphy: phy@ff2e0000 { 857 compatible = "rockchip,px30-dsi-dphy"; 858 reg = <0x0 0xff2e0000 0x0 0x10000>; 859 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 860 clock-names = "ref", "pclk"; 861 resets = <&cru SRST_MIPIDSIPHY_P>; 862 reset-names = "apb"; 863 #phy-cells = <0>; 864 power-domains = <&power PX30_PD_VO>; 865 status = "disabled"; 866 }; 867 868 usb20_otg: usb@ff300000 { 869 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 870 "snps,dwc2"; 871 reg = <0x0 0xff300000 0x0 0x40000>; 872 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cru HCLK_OTG>; 874 clock-names = "otg"; 875 dr_mode = "otg"; 876 g-np-tx-fifo-size = <16>; 877 g-rx-fifo-size = <280>; 878 g-tx-fifo-size = <256 128 128 64 32 16>; 879 phys = <&u2phy_otg>; 880 phy-names = "usb2-phy"; 881 power-domains = <&power PX30_PD_USB>; 882 status = "disabled"; 883 }; 884 885 usb_host0_ehci: usb@ff340000 { 886 compatible = "generic-ehci"; 887 reg = <0x0 0xff340000 0x0 0x10000>; 888 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&cru HCLK_HOST>; 890 phys = <&u2phy_host>; 891 phy-names = "usb"; 892 power-domains = <&power PX30_PD_USB>; 893 status = "disabled"; 894 }; 895 896 usb_host0_ohci: usb@ff350000 { 897 compatible = "generic-ohci"; 898 reg = <0x0 0xff350000 0x0 0x10000>; 899 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&cru HCLK_HOST>; 901 phys = <&u2phy_host>; 902 phy-names = "usb"; 903 power-domains = <&power PX30_PD_USB>; 904 status = "disabled"; 905 }; 906 907 gmac: ethernet@ff360000 { 908 compatible = "rockchip,px30-gmac"; 909 reg = <0x0 0xff360000 0x0 0x10000>; 910 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 911 interrupt-names = "macirq"; 912 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 913 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 914 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 915 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 916 clock-names = "stmmaceth", "mac_clk_rx", 917 "mac_clk_tx", "clk_mac_ref", 918 "clk_mac_refout", "aclk_mac", 919 "pclk_mac", "clk_mac_speed"; 920 rockchip,grf = <&grf>; 921 phy-mode = "rmii"; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 924 power-domains = <&power PX30_PD_GMAC>; 925 resets = <&cru SRST_GMAC_A>; 926 reset-names = "stmmaceth"; 927 status = "disabled"; 928 }; 929 930 sdmmc: mmc@ff370000 { 931 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 932 reg = <0x0 0xff370000 0x0 0x4000>; 933 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 935 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 936 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 937 bus-width = <4>; 938 fifo-depth = <0x100>; 939 max-frequency = <150000000>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 942 power-domains = <&power PX30_PD_SDCARD>; 943 status = "disabled"; 944 }; 945 946 sdio: mmc@ff380000 { 947 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 948 reg = <0x0 0xff380000 0x0 0x4000>; 949 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 951 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 952 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 953 bus-width = <4>; 954 fifo-depth = <0x100>; 955 max-frequency = <150000000>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 958 power-domains = <&power PX30_PD_MMC_NAND>; 959 status = "disabled"; 960 }; 961 962 emmc: mmc@ff390000 { 963 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 964 reg = <0x0 0xff390000 0x0 0x4000>; 965 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 967 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 968 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 969 bus-width = <8>; 970 fifo-depth = <0x100>; 971 max-frequency = <150000000>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 974 power-domains = <&power PX30_PD_MMC_NAND>; 975 status = "disabled"; 976 }; 977 978 gpu: gpu@ff400000 { 979 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 980 reg = <0x0 0xff400000 0x0 0x4000>; 981 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 984 interrupt-names = "job", "mmu", "gpu"; 985 clocks = <&cru SCLK_GPU>; 986 #cooling-cells = <2>; 987 power-domains = <&power PX30_PD_GPU>; 988 status = "disabled"; 989 }; 990 991 dsi: dsi@ff450000 { 992 compatible = "rockchip,px30-mipi-dsi"; 993 reg = <0x0 0xff450000 0x0 0x10000>; 994 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&cru PCLK_MIPI_DSI>; 996 clock-names = "pclk"; 997 phys = <&dsi_dphy>; 998 phy-names = "dphy"; 999 power-domains = <&power PX30_PD_VO>; 1000 resets = <&cru SRST_MIPIDSI_HOST_P>; 1001 reset-names = "apb"; 1002 rockchip,grf = <&grf>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 1007 ports { 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 1011 port@0 { 1012 reg = <0>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 1016 dsi_in_vopb: endpoint@0 { 1017 reg = <0>; 1018 remote-endpoint = <&vopb_out_dsi>; 1019 }; 1020 1021 dsi_in_vopl: endpoint@1 { 1022 reg = <1>; 1023 remote-endpoint = <&vopl_out_dsi>; 1024 }; 1025 }; 1026 }; 1027 }; 1028 1029 vopb: vop@ff460000 { 1030 compatible = "rockchip,px30-vop-big"; 1031 reg = <0x0 0xff460000 0x0 0xefc>; 1032 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1034 <&cru HCLK_VOPB>; 1035 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1036 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1037 reset-names = "axi", "ahb", "dclk"; 1038 iommus = <&vopb_mmu>; 1039 power-domains = <&power PX30_PD_VO>; 1040 status = "disabled"; 1041 1042 vopb_out: port { 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 1046 vopb_out_dsi: endpoint@0 { 1047 reg = <0>; 1048 remote-endpoint = <&dsi_in_vopb>; 1049 }; 1050 1051 vopb_out_lvds: endpoint@1 { 1052 reg = <1>; 1053 remote-endpoint = <&lvds_vopb_in>; 1054 }; 1055 }; 1056 }; 1057 1058 vopb_mmu: iommu@ff460f00 { 1059 compatible = "rockchip,iommu"; 1060 reg = <0x0 0xff460f00 0x0 0x100>; 1061 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1062 interrupt-names = "vopb_mmu"; 1063 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1064 clock-names = "aclk", "iface"; 1065 power-domains = <&power PX30_PD_VO>; 1066 #iommu-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 vopl: vop@ff470000 { 1071 compatible = "rockchip,px30-vop-lit"; 1072 reg = <0x0 0xff470000 0x0 0xefc>; 1073 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1075 <&cru HCLK_VOPL>; 1076 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1077 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1078 reset-names = "axi", "ahb", "dclk"; 1079 iommus = <&vopl_mmu>; 1080 power-domains = <&power PX30_PD_VO>; 1081 status = "disabled"; 1082 1083 vopl_out: port { 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 vopl_out_dsi: endpoint@0 { 1088 reg = <0>; 1089 remote-endpoint = <&dsi_in_vopl>; 1090 }; 1091 1092 vopl_out_lvds: endpoint@1 { 1093 reg = <1>; 1094 remote-endpoint = <&lvds_vopl_in>; 1095 }; 1096 }; 1097 }; 1098 1099 vopl_mmu: iommu@ff470f00 { 1100 compatible = "rockchip,iommu"; 1101 reg = <0x0 0xff470f00 0x0 0x100>; 1102 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1103 interrupt-names = "vopl_mmu"; 1104 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1105 clock-names = "aclk", "iface"; 1106 power-domains = <&power PX30_PD_VO>; 1107 #iommu-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 qos_gmac: qos@ff518000 { 1112 compatible = "syscon"; 1113 reg = <0x0 0xff518000 0x0 0x20>; 1114 }; 1115 1116 qos_gpu: qos@ff520000 { 1117 compatible = "syscon"; 1118 reg = <0x0 0xff520000 0x0 0x20>; 1119 }; 1120 1121 qos_sdmmc: qos@ff52c000 { 1122 compatible = "syscon"; 1123 reg = <0x0 0xff52c000 0x0 0x20>; 1124 }; 1125 1126 qos_emmc: qos@ff538000 { 1127 compatible = "syscon"; 1128 reg = <0x0 0xff538000 0x0 0x20>; 1129 }; 1130 1131 qos_nand: qos@ff538080 { 1132 compatible = "syscon"; 1133 reg = <0x0 0xff538080 0x0 0x20>; 1134 }; 1135 1136 qos_sdio: qos@ff538100 { 1137 compatible = "syscon"; 1138 reg = <0x0 0xff538100 0x0 0x20>; 1139 }; 1140 1141 qos_sfc: qos@ff538180 { 1142 compatible = "syscon"; 1143 reg = <0x0 0xff538180 0x0 0x20>; 1144 }; 1145 1146 qos_usb_host: qos@ff540000 { 1147 compatible = "syscon"; 1148 reg = <0x0 0xff540000 0x0 0x20>; 1149 }; 1150 1151 qos_usb_otg: qos@ff540080 { 1152 compatible = "syscon"; 1153 reg = <0x0 0xff540080 0x0 0x20>; 1154 }; 1155 1156 qos_isp_128: qos@ff548000 { 1157 compatible = "syscon"; 1158 reg = <0x0 0xff548000 0x0 0x20>; 1159 }; 1160 1161 qos_isp_rd: qos@ff548080 { 1162 compatible = "syscon"; 1163 reg = <0x0 0xff548080 0x0 0x20>; 1164 }; 1165 1166 qos_isp_wr: qos@ff548100 { 1167 compatible = "syscon"; 1168 reg = <0x0 0xff548100 0x0 0x20>; 1169 }; 1170 1171 qos_isp_m1: qos@ff548180 { 1172 compatible = "syscon"; 1173 reg = <0x0 0xff548180 0x0 0x20>; 1174 }; 1175 1176 qos_vip: qos@ff548200 { 1177 compatible = "syscon"; 1178 reg = <0x0 0xff548200 0x0 0x20>; 1179 }; 1180 1181 qos_rga_rd: qos@ff550000 { 1182 compatible = "syscon"; 1183 reg = <0x0 0xff550000 0x0 0x20>; 1184 }; 1185 1186 qos_rga_wr: qos@ff550080 { 1187 compatible = "syscon"; 1188 reg = <0x0 0xff550080 0x0 0x20>; 1189 }; 1190 1191 qos_vop_m0: qos@ff550100 { 1192 compatible = "syscon"; 1193 reg = <0x0 0xff550100 0x0 0x20>; 1194 }; 1195 1196 qos_vop_m1: qos@ff550180 { 1197 compatible = "syscon"; 1198 reg = <0x0 0xff550180 0x0 0x20>; 1199 }; 1200 1201 qos_vpu: qos@ff558000 { 1202 compatible = "syscon"; 1203 reg = <0x0 0xff558000 0x0 0x20>; 1204 }; 1205 1206 qos_vpu_r128: qos@ff558080 { 1207 compatible = "syscon"; 1208 reg = <0x0 0xff558080 0x0 0x20>; 1209 }; 1210 1211 pinctrl: pinctrl { 1212 compatible = "rockchip,px30-pinctrl"; 1213 rockchip,grf = <&grf>; 1214 rockchip,pmu = <&pmugrf>; 1215 #address-cells = <2>; 1216 #size-cells = <2>; 1217 ranges; 1218 1219 gpio0: gpio0@ff040000 { 1220 compatible = "rockchip,gpio-bank"; 1221 reg = <0x0 0xff040000 0x0 0x100>; 1222 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&pmucru PCLK_GPIO0_PMU>; 1224 gpio-controller; 1225 #gpio-cells = <2>; 1226 1227 interrupt-controller; 1228 #interrupt-cells = <2>; 1229 }; 1230 1231 gpio1: gpio1@ff250000 { 1232 compatible = "rockchip,gpio-bank"; 1233 reg = <0x0 0xff250000 0x0 0x100>; 1234 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&cru PCLK_GPIO1>; 1236 gpio-controller; 1237 #gpio-cells = <2>; 1238 1239 interrupt-controller; 1240 #interrupt-cells = <2>; 1241 }; 1242 1243 gpio2: gpio2@ff260000 { 1244 compatible = "rockchip,gpio-bank"; 1245 reg = <0x0 0xff260000 0x0 0x100>; 1246 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&cru PCLK_GPIO2>; 1248 gpio-controller; 1249 #gpio-cells = <2>; 1250 1251 interrupt-controller; 1252 #interrupt-cells = <2>; 1253 }; 1254 1255 gpio3: gpio3@ff270000 { 1256 compatible = "rockchip,gpio-bank"; 1257 reg = <0x0 0xff270000 0x0 0x100>; 1258 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&cru PCLK_GPIO3>; 1260 gpio-controller; 1261 #gpio-cells = <2>; 1262 1263 interrupt-controller; 1264 #interrupt-cells = <2>; 1265 }; 1266 1267 pcfg_pull_up: pcfg-pull-up { 1268 bias-pull-up; 1269 }; 1270 1271 pcfg_pull_down: pcfg-pull-down { 1272 bias-pull-down; 1273 }; 1274 1275 pcfg_pull_none: pcfg-pull-none { 1276 bias-disable; 1277 }; 1278 1279 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1280 bias-disable; 1281 drive-strength = <2>; 1282 }; 1283 1284 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1285 bias-pull-up; 1286 drive-strength = <2>; 1287 }; 1288 1289 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1290 bias-pull-up; 1291 drive-strength = <4>; 1292 }; 1293 1294 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1295 bias-disable; 1296 drive-strength = <4>; 1297 }; 1298 1299 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1300 bias-pull-down; 1301 drive-strength = <4>; 1302 }; 1303 1304 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1305 bias-disable; 1306 drive-strength = <8>; 1307 }; 1308 1309 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1310 bias-pull-up; 1311 drive-strength = <8>; 1312 }; 1313 1314 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1315 bias-disable; 1316 drive-strength = <12>; 1317 }; 1318 1319 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1320 bias-pull-up; 1321 drive-strength = <12>; 1322 }; 1323 1324 pcfg_pull_none_smt: pcfg-pull-none-smt { 1325 bias-disable; 1326 input-schmitt-enable; 1327 }; 1328 1329 pcfg_output_high: pcfg-output-high { 1330 output-high; 1331 }; 1332 1333 pcfg_output_low: pcfg-output-low { 1334 output-low; 1335 }; 1336 1337 pcfg_input_high: pcfg-input-high { 1338 bias-pull-up; 1339 input-enable; 1340 }; 1341 1342 pcfg_input: pcfg-input { 1343 input-enable; 1344 }; 1345 1346 i2c0 { 1347 i2c0_xfer: i2c0-xfer { 1348 rockchip,pins = 1349 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1350 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1351 }; 1352 }; 1353 1354 i2c1 { 1355 i2c1_xfer: i2c1-xfer { 1356 rockchip,pins = 1357 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1358 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1359 }; 1360 }; 1361 1362 i2c2 { 1363 i2c2_xfer: i2c2-xfer { 1364 rockchip,pins = 1365 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1366 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1367 }; 1368 }; 1369 1370 i2c3 { 1371 i2c3_xfer: i2c3-xfer { 1372 rockchip,pins = 1373 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1374 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1375 }; 1376 }; 1377 1378 tsadc { 1379 tsadc_otp_pin: tsadc-otp-pin { 1380 rockchip,pins = 1381 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1382 }; 1383 1384 tsadc_otp_out: tsadc-otp-out { 1385 rockchip,pins = 1386 <0 RK_PA6 1 &pcfg_pull_none>; 1387 }; 1388 }; 1389 1390 uart0 { 1391 uart0_xfer: uart0-xfer { 1392 rockchip,pins = 1393 <0 RK_PB2 1 &pcfg_pull_up>, 1394 <0 RK_PB3 1 &pcfg_pull_up>; 1395 }; 1396 1397 uart0_cts: uart0-cts { 1398 rockchip,pins = 1399 <0 RK_PB4 1 &pcfg_pull_none>; 1400 }; 1401 1402 uart0_rts: uart0-rts { 1403 rockchip,pins = 1404 <0 RK_PB5 1 &pcfg_pull_none>; 1405 }; 1406 }; 1407 1408 uart1 { 1409 uart1_xfer: uart1-xfer { 1410 rockchip,pins = 1411 <1 RK_PC1 1 &pcfg_pull_up>, 1412 <1 RK_PC0 1 &pcfg_pull_up>; 1413 }; 1414 1415 uart1_cts: uart1-cts { 1416 rockchip,pins = 1417 <1 RK_PC2 1 &pcfg_pull_none>; 1418 }; 1419 1420 uart1_rts: uart1-rts { 1421 rockchip,pins = 1422 <1 RK_PC3 1 &pcfg_pull_none>; 1423 }; 1424 }; 1425 1426 uart2-m0 { 1427 uart2m0_xfer: uart2m0-xfer { 1428 rockchip,pins = 1429 <1 RK_PD2 2 &pcfg_pull_up>, 1430 <1 RK_PD3 2 &pcfg_pull_up>; 1431 }; 1432 }; 1433 1434 uart2-m1 { 1435 uart2m1_xfer: uart2m1-xfer { 1436 rockchip,pins = 1437 <2 RK_PB4 2 &pcfg_pull_up>, 1438 <2 RK_PB6 2 &pcfg_pull_up>; 1439 }; 1440 }; 1441 1442 uart3-m0 { 1443 uart3m0_xfer: uart3m0-xfer { 1444 rockchip,pins = 1445 <0 RK_PC0 2 &pcfg_pull_up>, 1446 <0 RK_PC1 2 &pcfg_pull_up>; 1447 }; 1448 1449 uart3m0_cts: uart3m0-cts { 1450 rockchip,pins = 1451 <0 RK_PC2 2 &pcfg_pull_none>; 1452 }; 1453 1454 uart3m0_rts: uart3m0-rts { 1455 rockchip,pins = 1456 <0 RK_PC3 2 &pcfg_pull_none>; 1457 }; 1458 }; 1459 1460 uart3-m1 { 1461 uart3m1_xfer: uart3m1-xfer { 1462 rockchip,pins = 1463 <1 RK_PB6 2 &pcfg_pull_up>, 1464 <1 RK_PB7 2 &pcfg_pull_up>; 1465 }; 1466 1467 uart3m1_cts: uart3m1-cts { 1468 rockchip,pins = 1469 <1 RK_PB4 2 &pcfg_pull_none>; 1470 }; 1471 1472 uart3m1_rts: uart3m1-rts { 1473 rockchip,pins = 1474 <1 RK_PB5 2 &pcfg_pull_none>; 1475 }; 1476 }; 1477 1478 uart4 { 1479 uart4_xfer: uart4-xfer { 1480 rockchip,pins = 1481 <1 RK_PD4 2 &pcfg_pull_up>, 1482 <1 RK_PD5 2 &pcfg_pull_up>; 1483 }; 1484 1485 uart4_cts: uart4-cts { 1486 rockchip,pins = 1487 <1 RK_PD6 2 &pcfg_pull_none>; 1488 }; 1489 1490 uart4_rts: uart4-rts { 1491 rockchip,pins = 1492 <1 RK_PD7 2 &pcfg_pull_none>; 1493 }; 1494 }; 1495 1496 uart5 { 1497 uart5_xfer: uart5-xfer { 1498 rockchip,pins = 1499 <3 RK_PA2 4 &pcfg_pull_up>, 1500 <3 RK_PA1 4 &pcfg_pull_up>; 1501 }; 1502 1503 uart5_cts: uart5-cts { 1504 rockchip,pins = 1505 <3 RK_PA3 4 &pcfg_pull_none>; 1506 }; 1507 1508 uart5_rts: uart5-rts { 1509 rockchip,pins = 1510 <3 RK_PA5 4 &pcfg_pull_none>; 1511 }; 1512 }; 1513 1514 spi0 { 1515 spi0_clk: spi0-clk { 1516 rockchip,pins = 1517 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1518 }; 1519 1520 spi0_csn: spi0-csn { 1521 rockchip,pins = 1522 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1523 }; 1524 1525 spi0_miso: spi0-miso { 1526 rockchip,pins = 1527 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1528 }; 1529 1530 spi0_mosi: spi0-mosi { 1531 rockchip,pins = 1532 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1533 }; 1534 1535 spi0_clk_hs: spi0-clk-hs { 1536 rockchip,pins = 1537 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1538 }; 1539 1540 spi0_miso_hs: spi0-miso-hs { 1541 rockchip,pins = 1542 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1543 }; 1544 1545 spi0_mosi_hs: spi0-mosi-hs { 1546 rockchip,pins = 1547 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1548 }; 1549 }; 1550 1551 spi1 { 1552 spi1_clk: spi1-clk { 1553 rockchip,pins = 1554 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1555 }; 1556 1557 spi1_csn0: spi1-csn0 { 1558 rockchip,pins = 1559 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1560 }; 1561 1562 spi1_csn1: spi1-csn1 { 1563 rockchip,pins = 1564 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1565 }; 1566 1567 spi1_miso: spi1-miso { 1568 rockchip,pins = 1569 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1570 }; 1571 1572 spi1_mosi: spi1-mosi { 1573 rockchip,pins = 1574 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1575 }; 1576 1577 spi1_clk_hs: spi1-clk-hs { 1578 rockchip,pins = 1579 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1580 }; 1581 1582 spi1_miso_hs: spi1-miso-hs { 1583 rockchip,pins = 1584 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1585 }; 1586 1587 spi1_mosi_hs: spi1-mosi-hs { 1588 rockchip,pins = 1589 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1590 }; 1591 }; 1592 1593 pdm { 1594 pdm_clk0m0: pdm-clk0m0 { 1595 rockchip,pins = 1596 <3 RK_PC6 2 &pcfg_pull_none>; 1597 }; 1598 1599 pdm_clk0m1: pdm-clk0m1 { 1600 rockchip,pins = 1601 <2 RK_PC6 1 &pcfg_pull_none>; 1602 }; 1603 1604 pdm_clk1: pdm-clk1 { 1605 rockchip,pins = 1606 <3 RK_PC7 2 &pcfg_pull_none>; 1607 }; 1608 1609 pdm_sdi0m0: pdm-sdi0m0 { 1610 rockchip,pins = 1611 <3 RK_PD3 2 &pcfg_pull_none>; 1612 }; 1613 1614 pdm_sdi0m1: pdm-sdi0m1 { 1615 rockchip,pins = 1616 <2 RK_PC5 2 &pcfg_pull_none>; 1617 }; 1618 1619 pdm_sdi1: pdm-sdi1 { 1620 rockchip,pins = 1621 <3 RK_PD0 2 &pcfg_pull_none>; 1622 }; 1623 1624 pdm_sdi2: pdm-sdi2 { 1625 rockchip,pins = 1626 <3 RK_PD1 2 &pcfg_pull_none>; 1627 }; 1628 1629 pdm_sdi3: pdm-sdi3 { 1630 rockchip,pins = 1631 <3 RK_PD2 2 &pcfg_pull_none>; 1632 }; 1633 1634 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1635 rockchip,pins = 1636 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1637 }; 1638 1639 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1640 rockchip,pins = 1641 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1642 }; 1643 1644 pdm_clk1_sleep: pdm-clk1-sleep { 1645 rockchip,pins = 1646 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1647 }; 1648 1649 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1650 rockchip,pins = 1651 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1652 }; 1653 1654 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1655 rockchip,pins = 1656 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1657 }; 1658 1659 pdm_sdi1_sleep: pdm-sdi1-sleep { 1660 rockchip,pins = 1661 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1662 }; 1663 1664 pdm_sdi2_sleep: pdm-sdi2-sleep { 1665 rockchip,pins = 1666 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1667 }; 1668 1669 pdm_sdi3_sleep: pdm-sdi3-sleep { 1670 rockchip,pins = 1671 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1672 }; 1673 }; 1674 1675 i2s0 { 1676 i2s0_8ch_mclk: i2s0-8ch-mclk { 1677 rockchip,pins = 1678 <3 RK_PC1 2 &pcfg_pull_none>; 1679 }; 1680 1681 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1682 rockchip,pins = 1683 <3 RK_PC3 2 &pcfg_pull_none>; 1684 }; 1685 1686 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1687 rockchip,pins = 1688 <3 RK_PB4 2 &pcfg_pull_none>; 1689 }; 1690 1691 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1692 rockchip,pins = 1693 <3 RK_PC2 2 &pcfg_pull_none>; 1694 }; 1695 1696 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1697 rockchip,pins = 1698 <3 RK_PB5 2 &pcfg_pull_none>; 1699 }; 1700 1701 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1702 rockchip,pins = 1703 <3 RK_PC4 2 &pcfg_pull_none>; 1704 }; 1705 1706 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1707 rockchip,pins = 1708 <3 RK_PC0 2 &pcfg_pull_none>; 1709 }; 1710 1711 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1712 rockchip,pins = 1713 <3 RK_PB7 2 &pcfg_pull_none>; 1714 }; 1715 1716 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1717 rockchip,pins = 1718 <3 RK_PB6 2 &pcfg_pull_none>; 1719 }; 1720 1721 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1722 rockchip,pins = 1723 <3 RK_PC5 2 &pcfg_pull_none>; 1724 }; 1725 1726 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1727 rockchip,pins = 1728 <3 RK_PB3 2 &pcfg_pull_none>; 1729 }; 1730 1731 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1732 rockchip,pins = 1733 <3 RK_PB1 2 &pcfg_pull_none>; 1734 }; 1735 1736 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1737 rockchip,pins = 1738 <3 RK_PB0 2 &pcfg_pull_none>; 1739 }; 1740 }; 1741 1742 i2s1 { 1743 i2s1_2ch_mclk: i2s1-2ch-mclk { 1744 rockchip,pins = 1745 <2 RK_PC3 1 &pcfg_pull_none>; 1746 }; 1747 1748 i2s1_2ch_sclk: i2s1-2ch-sclk { 1749 rockchip,pins = 1750 <2 RK_PC2 1 &pcfg_pull_none>; 1751 }; 1752 1753 i2s1_2ch_lrck: i2s1-2ch-lrck { 1754 rockchip,pins = 1755 <2 RK_PC1 1 &pcfg_pull_none>; 1756 }; 1757 1758 i2s1_2ch_sdi: i2s1-2ch-sdi { 1759 rockchip,pins = 1760 <2 RK_PC5 1 &pcfg_pull_none>; 1761 }; 1762 1763 i2s1_2ch_sdo: i2s1-2ch-sdo { 1764 rockchip,pins = 1765 <2 RK_PC4 1 &pcfg_pull_none>; 1766 }; 1767 }; 1768 1769 i2s2 { 1770 i2s2_2ch_mclk: i2s2-2ch-mclk { 1771 rockchip,pins = 1772 <3 RK_PA1 2 &pcfg_pull_none>; 1773 }; 1774 1775 i2s2_2ch_sclk: i2s2-2ch-sclk { 1776 rockchip,pins = 1777 <3 RK_PA2 2 &pcfg_pull_none>; 1778 }; 1779 1780 i2s2_2ch_lrck: i2s2-2ch-lrck { 1781 rockchip,pins = 1782 <3 RK_PA3 2 &pcfg_pull_none>; 1783 }; 1784 1785 i2s2_2ch_sdi: i2s2-2ch-sdi { 1786 rockchip,pins = 1787 <3 RK_PA5 2 &pcfg_pull_none>; 1788 }; 1789 1790 i2s2_2ch_sdo: i2s2-2ch-sdo { 1791 rockchip,pins = 1792 <3 RK_PA7 2 &pcfg_pull_none>; 1793 }; 1794 }; 1795 1796 sdmmc { 1797 sdmmc_clk: sdmmc-clk { 1798 rockchip,pins = 1799 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1800 }; 1801 1802 sdmmc_cmd: sdmmc-cmd { 1803 rockchip,pins = 1804 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1805 }; 1806 1807 sdmmc_det: sdmmc-det { 1808 rockchip,pins = 1809 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1810 }; 1811 1812 sdmmc_bus1: sdmmc-bus1 { 1813 rockchip,pins = 1814 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1815 }; 1816 1817 sdmmc_bus4: sdmmc-bus4 { 1818 rockchip,pins = 1819 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1820 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1821 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1822 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1823 }; 1824 }; 1825 1826 sdio { 1827 sdio_clk: sdio-clk { 1828 rockchip,pins = 1829 <1 RK_PC5 1 &pcfg_pull_none>; 1830 }; 1831 1832 sdio_cmd: sdio-cmd { 1833 rockchip,pins = 1834 <1 RK_PC4 1 &pcfg_pull_up>; 1835 }; 1836 1837 sdio_bus4: sdio-bus4 { 1838 rockchip,pins = 1839 <1 RK_PC6 1 &pcfg_pull_up>, 1840 <1 RK_PC7 1 &pcfg_pull_up>, 1841 <1 RK_PD0 1 &pcfg_pull_up>, 1842 <1 RK_PD1 1 &pcfg_pull_up>; 1843 }; 1844 }; 1845 1846 emmc { 1847 emmc_clk: emmc-clk { 1848 rockchip,pins = 1849 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1850 }; 1851 1852 emmc_cmd: emmc-cmd { 1853 rockchip,pins = 1854 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1855 }; 1856 1857 emmc_rstnout: emmc-rstnout { 1858 rockchip,pins = 1859 <1 RK_PB3 2 &pcfg_pull_none>; 1860 }; 1861 1862 emmc_bus1: emmc-bus1 { 1863 rockchip,pins = 1864 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1865 }; 1866 1867 emmc_bus4: emmc-bus4 { 1868 rockchip,pins = 1869 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1870 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1871 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1872 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1873 }; 1874 1875 emmc_bus8: emmc-bus8 { 1876 rockchip,pins = 1877 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1878 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1879 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1880 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1881 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1882 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1883 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1884 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1885 }; 1886 }; 1887 1888 flash { 1889 flash_cs0: flash-cs0 { 1890 rockchip,pins = 1891 <1 RK_PB0 1 &pcfg_pull_none>; 1892 }; 1893 1894 flash_rdy: flash-rdy { 1895 rockchip,pins = 1896 <1 RK_PB1 1 &pcfg_pull_none>; 1897 }; 1898 1899 flash_dqs: flash-dqs { 1900 rockchip,pins = 1901 <1 RK_PB2 1 &pcfg_pull_none>; 1902 }; 1903 1904 flash_ale: flash-ale { 1905 rockchip,pins = 1906 <1 RK_PB3 1 &pcfg_pull_none>; 1907 }; 1908 1909 flash_cle: flash-cle { 1910 rockchip,pins = 1911 <1 RK_PB4 1 &pcfg_pull_none>; 1912 }; 1913 1914 flash_wrn: flash-wrn { 1915 rockchip,pins = 1916 <1 RK_PB5 1 &pcfg_pull_none>; 1917 }; 1918 1919 flash_csl: flash-csl { 1920 rockchip,pins = 1921 <1 RK_PB6 1 &pcfg_pull_none>; 1922 }; 1923 1924 flash_rdn: flash-rdn { 1925 rockchip,pins = 1926 <1 RK_PB7 1 &pcfg_pull_none>; 1927 }; 1928 1929 flash_bus8: flash-bus8 { 1930 rockchip,pins = 1931 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1932 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1933 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1934 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1935 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1936 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1937 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1938 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1939 }; 1940 }; 1941 1942 lcdc { 1943 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1944 rockchip,pins = 1945 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1946 }; 1947 1948 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1949 rockchip,pins = 1950 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1951 }; 1952 1953 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1954 rockchip,pins = 1955 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1956 }; 1957 1958 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1959 rockchip,pins = 1960 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1961 }; 1962 1963 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1964 rockchip,pins = 1965 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1966 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1967 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1968 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1969 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1970 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1971 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1972 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1973 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1974 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1975 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1976 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1977 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1978 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1979 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1980 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1981 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1982 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1983 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1984 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1985 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1986 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1987 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1988 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1989 }; 1990 1991 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 1992 rockchip,pins = 1993 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1994 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1995 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1996 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1997 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1998 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1999 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2000 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2001 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2002 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2003 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2004 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2005 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2006 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2007 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2008 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2009 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2010 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2011 }; 2012 2013 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2014 rockchip,pins = 2015 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2016 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2017 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2018 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2019 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2020 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2021 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2022 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2023 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2024 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2025 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2026 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2027 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2028 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2029 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2030 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2031 }; 2032 2033 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2034 rockchip,pins = 2035 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2036 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2037 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2038 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2039 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2040 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2041 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2042 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2043 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2044 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2045 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2046 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2047 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2048 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2049 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2050 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2051 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2052 }; 2053 2054 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2055 rockchip,pins = 2056 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2057 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2058 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2059 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2060 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2061 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2062 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2063 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2064 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2065 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2066 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2067 }; 2068 2069 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2070 rockchip,pins = 2071 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2072 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2073 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2074 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2075 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2076 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2077 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2078 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2079 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2080 }; 2081 }; 2082 2083 pwm0 { 2084 pwm0_pin: pwm0-pin { 2085 rockchip,pins = 2086 <0 RK_PB7 1 &pcfg_pull_none>; 2087 }; 2088 }; 2089 2090 pwm1 { 2091 pwm1_pin: pwm1-pin { 2092 rockchip,pins = 2093 <0 RK_PC0 1 &pcfg_pull_none>; 2094 }; 2095 }; 2096 2097 pwm2 { 2098 pwm2_pin: pwm2-pin { 2099 rockchip,pins = 2100 <2 RK_PB5 1 &pcfg_pull_none>; 2101 }; 2102 }; 2103 2104 pwm3 { 2105 pwm3_pin: pwm3-pin { 2106 rockchip,pins = 2107 <0 RK_PC1 1 &pcfg_pull_none>; 2108 }; 2109 }; 2110 2111 pwm4 { 2112 pwm4_pin: pwm4-pin { 2113 rockchip,pins = 2114 <3 RK_PC2 3 &pcfg_pull_none>; 2115 }; 2116 }; 2117 2118 pwm5 { 2119 pwm5_pin: pwm5-pin { 2120 rockchip,pins = 2121 <3 RK_PC3 3 &pcfg_pull_none>; 2122 }; 2123 }; 2124 2125 pwm6 { 2126 pwm6_pin: pwm6-pin { 2127 rockchip,pins = 2128 <3 RK_PC4 3 &pcfg_pull_none>; 2129 }; 2130 }; 2131 2132 pwm7 { 2133 pwm7_pin: pwm7-pin { 2134 rockchip,pins = 2135 <3 RK_PC5 3 &pcfg_pull_none>; 2136 }; 2137 }; 2138 2139 gmac { 2140 rmii_pins: rmii-pins { 2141 rockchip,pins = 2142 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2143 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2144 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2145 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2146 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2147 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2148 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2149 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2150 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2151 }; 2152 2153 mac_refclk_12ma: mac-refclk-12ma { 2154 rockchip,pins = 2155 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2156 }; 2157 2158 mac_refclk: mac-refclk { 2159 rockchip,pins = 2160 <2 RK_PB2 2 &pcfg_pull_none>; 2161 }; 2162 }; 2163 2164 cif-m0 { 2165 cif_clkout_m0: cif-clkout-m0 { 2166 rockchip,pins = 2167 <2 RK_PB3 1 &pcfg_pull_none>; 2168 }; 2169 2170 dvp_d2d9_m0: dvp-d2d9-m0 { 2171 rockchip,pins = 2172 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2173 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2174 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2175 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2176 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2177 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2178 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2179 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2180 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2181 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2182 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2183 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2184 }; 2185 2186 dvp_d0d1_m0: dvp-d0d1-m0 { 2187 rockchip,pins = 2188 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2189 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2190 }; 2191 2192 dvp_d10d11_m0:d10-d11-m0 { 2193 rockchip,pins = 2194 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2195 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2196 }; 2197 }; 2198 2199 cif-m1 { 2200 cif_clkout_m1: cif-clkout-m1 { 2201 rockchip,pins = 2202 <3 RK_PD0 3 &pcfg_pull_none>; 2203 }; 2204 2205 dvp_d2d9_m1: dvp-d2d9-m1 { 2206 rockchip,pins = 2207 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2208 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2209 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2210 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2211 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2212 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2213 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2214 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2215 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2216 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2217 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2218 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2219 }; 2220 2221 dvp_d0d1_m1: dvp-d0d1-m1 { 2222 rockchip,pins = 2223 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2224 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2225 }; 2226 2227 dvp_d10d11_m1:d10-d11-m1 { 2228 rockchip,pins = 2229 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2230 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2231 }; 2232 }; 2233 2234 isp { 2235 isp_prelight: isp-prelight { 2236 rockchip,pins = 2237 <3 RK_PD1 4 &pcfg_pull_none>; 2238 }; 2239 }; 2240 }; 2241}; 2242