1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 mmc0 = &sdio0; 33 mmc1 = &sdmmc; 34 mmc2 = &sdhci; 35 serial0 = &uart0; 36 serial1 = &uart1; 37 serial2 = &uart2; 38 serial3 = &uart3; 39 serial4 = &uart4; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu_l0>; 50 }; 51 core1 { 52 cpu = <&cpu_l1>; 53 }; 54 core2 { 55 cpu = <&cpu_l2>; 56 }; 57 core3 { 58 cpu = <&cpu_l3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu_b0>; 65 }; 66 core1 { 67 cpu = <&cpu_b1>; 68 }; 69 }; 70 }; 71 72 cpu_l0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x0 0x0>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <485>; 78 clocks = <&cru ARMCLKL>; 79 #cooling-cells = <2>; /* min followed by max */ 80 dynamic-power-coefficient = <100>; 81 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 82 }; 83 84 cpu_l1: cpu@1 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x1>; 88 enable-method = "psci"; 89 capacity-dmips-mhz = <485>; 90 clocks = <&cru ARMCLKL>; 91 #cooling-cells = <2>; /* min followed by max */ 92 dynamic-power-coefficient = <100>; 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 94 }; 95 96 cpu_l2: cpu@2 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x2>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <485>; 102 clocks = <&cru ARMCLKL>; 103 #cooling-cells = <2>; /* min followed by max */ 104 dynamic-power-coefficient = <100>; 105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 106 }; 107 108 cpu_l3: cpu@3 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0 0x3>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <485>; 114 clocks = <&cru ARMCLKL>; 115 #cooling-cells = <2>; /* min followed by max */ 116 dynamic-power-coefficient = <100>; 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 118 }; 119 120 cpu_b0: cpu@100 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a72"; 123 reg = <0x0 0x100>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <1024>; 126 clocks = <&cru ARMCLKB>; 127 #cooling-cells = <2>; /* min followed by max */ 128 dynamic-power-coefficient = <436>; 129 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 130 }; 131 132 cpu_b1: cpu@101 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a72"; 135 reg = <0x0 0x101>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 clocks = <&cru ARMCLKB>; 139 #cooling-cells = <2>; /* min followed by max */ 140 dynamic-power-coefficient = <436>; 141 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 142 }; 143 144 idle-states { 145 entry-method = "psci"; 146 147 CPU_SLEEP: cpu-sleep { 148 compatible = "arm,idle-state"; 149 local-timer-stop; 150 arm,psci-suspend-param = <0x0010000>; 151 entry-latency-us = <120>; 152 exit-latency-us = <250>; 153 min-residency-us = <900>; 154 }; 155 156 CLUSTER_SLEEP: cluster-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x1010000>; 160 entry-latency-us = <400>; 161 exit-latency-us = <500>; 162 min-residency-us = <2000>; 163 }; 164 }; 165 }; 166 167 display-subsystem { 168 compatible = "rockchip,display-subsystem"; 169 ports = <&vopl_out>, <&vopb_out>; 170 }; 171 172 pmu_a53 { 173 compatible = "arm,cortex-a53-pmu"; 174 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 175 }; 176 177 pmu_a72 { 178 compatible = "arm,cortex-a72-pmu"; 179 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 180 }; 181 182 psci { 183 compatible = "arm,psci-1.0"; 184 method = "smc"; 185 }; 186 187 timer { 188 compatible = "arm,armv8-timer"; 189 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 190 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 191 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 192 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 193 arm,no-tick-in-suspend; 194 }; 195 196 xin24m: xin24m { 197 compatible = "fixed-clock"; 198 clock-frequency = <24000000>; 199 clock-output-names = "xin24m"; 200 #clock-cells = <0>; 201 }; 202 203 amba: bus { 204 compatible = "simple-bus"; 205 #address-cells = <2>; 206 #size-cells = <2>; 207 ranges; 208 209 dmac_bus: dma-controller@ff6d0000 { 210 compatible = "arm,pl330", "arm,primecell"; 211 reg = <0x0 0xff6d0000 0x0 0x4000>; 212 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 214 #dma-cells = <1>; 215 arm,pl330-periph-burst; 216 clocks = <&cru ACLK_DMAC0_PERILP>; 217 clock-names = "apb_pclk"; 218 }; 219 220 dmac_peri: dma-controller@ff6e0000 { 221 compatible = "arm,pl330", "arm,primecell"; 222 reg = <0x0 0xff6e0000 0x0 0x4000>; 223 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 224 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 225 #dma-cells = <1>; 226 arm,pl330-periph-burst; 227 clocks = <&cru ACLK_DMAC1_PERILP>; 228 clock-names = "apb_pclk"; 229 }; 230 }; 231 232 pcie0: pcie@f8000000 { 233 compatible = "rockchip,rk3399-pcie"; 234 reg = <0x0 0xf8000000 0x0 0x2000000>, 235 <0x0 0xfd000000 0x0 0x1000000>; 236 reg-names = "axi-base", "apb-base"; 237 device_type = "pci"; 238 #address-cells = <3>; 239 #size-cells = <2>; 240 #interrupt-cells = <1>; 241 aspm-no-l0s; 242 bus-range = <0x0 0x1f>; 243 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 244 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 245 clock-names = "aclk", "aclk-perf", 246 "hclk", "pm"; 247 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 248 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 249 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 250 interrupt-names = "sys", "legacy", "client"; 251 interrupt-map-mask = <0 0 0 7>; 252 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 253 <0 0 0 2 &pcie0_intc 1>, 254 <0 0 0 3 &pcie0_intc 2>, 255 <0 0 0 4 &pcie0_intc 3>; 256 max-link-speed = <1>; 257 msi-map = <0x0 &its 0x0 0x1000>; 258 phys = <&pcie_phy 0>, <&pcie_phy 1>, 259 <&pcie_phy 2>, <&pcie_phy 3>; 260 phy-names = "pcie-phy-0", "pcie-phy-1", 261 "pcie-phy-2", "pcie-phy-3"; 262 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 263 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 264 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 265 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 266 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 267 <&cru SRST_A_PCIE>; 268 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 269 "pm", "pclk", "aclk"; 270 status = "disabled"; 271 272 pcie0_intc: interrupt-controller { 273 interrupt-controller; 274 #address-cells = <0>; 275 #interrupt-cells = <1>; 276 }; 277 }; 278 279 gmac: ethernet@fe300000 { 280 compatible = "rockchip,rk3399-gmac"; 281 reg = <0x0 0xfe300000 0x0 0x10000>; 282 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 283 interrupt-names = "macirq"; 284 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 285 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 286 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 287 <&cru PCLK_GMAC>; 288 clock-names = "stmmaceth", "mac_clk_rx", 289 "mac_clk_tx", "clk_mac_ref", 290 "clk_mac_refout", "aclk_mac", 291 "pclk_mac"; 292 power-domains = <&power RK3399_PD_GMAC>; 293 resets = <&cru SRST_A_GMAC>; 294 reset-names = "stmmaceth"; 295 rockchip,grf = <&grf>; 296 snps,txpbl = <0x4>; 297 status = "disabled"; 298 }; 299 300 sdio0: mmc@fe310000 { 301 compatible = "rockchip,rk3399-dw-mshc", 302 "rockchip,rk3288-dw-mshc"; 303 reg = <0x0 0xfe310000 0x0 0x4000>; 304 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 305 max-frequency = <150000000>; 306 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 307 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 308 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 309 fifo-depth = <0x100>; 310 power-domains = <&power RK3399_PD_SDIOAUDIO>; 311 resets = <&cru SRST_SDIO0>; 312 reset-names = "reset"; 313 status = "disabled"; 314 }; 315 316 sdmmc: mmc@fe320000 { 317 compatible = "rockchip,rk3399-dw-mshc", 318 "rockchip,rk3288-dw-mshc"; 319 reg = <0x0 0xfe320000 0x0 0x4000>; 320 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 321 max-frequency = <150000000>; 322 assigned-clocks = <&cru HCLK_SD>; 323 assigned-clock-rates = <200000000>; 324 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 325 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 326 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 327 fifo-depth = <0x100>; 328 power-domains = <&power RK3399_PD_SD>; 329 resets = <&cru SRST_SDMMC>; 330 reset-names = "reset"; 331 status = "disabled"; 332 }; 333 334 sdhci: sdhci@fe330000 { 335 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 336 reg = <0x0 0xfe330000 0x0 0x10000>; 337 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 338 arasan,soc-ctl-syscon = <&grf>; 339 assigned-clocks = <&cru SCLK_EMMC>; 340 assigned-clock-rates = <200000000>; 341 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 342 clock-names = "clk_xin", "clk_ahb"; 343 clock-output-names = "emmc_cardclock"; 344 #clock-cells = <0>; 345 phys = <&emmc_phy>; 346 phy-names = "phy_arasan"; 347 power-domains = <&power RK3399_PD_EMMC>; 348 disable-cqe-dcmd; 349 status = "disabled"; 350 }; 351 352 usb_host0_ehci: usb@fe380000 { 353 compatible = "generic-ehci"; 354 reg = <0x0 0xfe380000 0x0 0x20000>; 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 357 <&u2phy0>; 358 phys = <&u2phy0_host>; 359 phy-names = "usb"; 360 status = "disabled"; 361 }; 362 363 usb_host0_ohci: usb@fe3a0000 { 364 compatible = "generic-ohci"; 365 reg = <0x0 0xfe3a0000 0x0 0x20000>; 366 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 367 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 368 <&u2phy0>; 369 phys = <&u2phy0_host>; 370 phy-names = "usb"; 371 status = "disabled"; 372 }; 373 374 usb_host1_ehci: usb@fe3c0000 { 375 compatible = "generic-ehci"; 376 reg = <0x0 0xfe3c0000 0x0 0x20000>; 377 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 378 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 379 <&u2phy1>; 380 phys = <&u2phy1_host>; 381 phy-names = "usb"; 382 status = "disabled"; 383 }; 384 385 usb_host1_ohci: usb@fe3e0000 { 386 compatible = "generic-ohci"; 387 reg = <0x0 0xfe3e0000 0x0 0x20000>; 388 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 390 <&u2phy1>; 391 phys = <&u2phy1_host>; 392 phy-names = "usb"; 393 status = "disabled"; 394 }; 395 396 usbdrd3_0: usb@fe800000 { 397 compatible = "rockchip,rk3399-dwc3"; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 402 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 403 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 404 clock-names = "ref_clk", "suspend_clk", 405 "bus_clk", "aclk_usb3_rksoc_axi_perf", 406 "aclk_usb3", "grf_clk"; 407 resets = <&cru SRST_A_USB3_OTG0>; 408 reset-names = "usb3-otg"; 409 status = "disabled"; 410 411 usbdrd_dwc3_0: usb@fe800000 { 412 compatible = "snps,dwc3"; 413 reg = <0x0 0xfe800000 0x0 0x100000>; 414 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 415 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 416 <&cru SCLK_USB3OTG0_SUSPEND>; 417 clock-names = "ref", "bus_early", "suspend"; 418 dr_mode = "otg"; 419 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 420 phy-names = "usb2-phy", "usb3-phy"; 421 phy_type = "utmi_wide"; 422 snps,dis_enblslpm_quirk; 423 snps,dis-u2-freeclk-exists-quirk; 424 snps,dis_u2_susphy_quirk; 425 snps,dis-del-phy-power-chg-quirk; 426 snps,dis-tx-ipgap-linecheck-quirk; 427 power-domains = <&power RK3399_PD_USB3>; 428 status = "disabled"; 429 }; 430 }; 431 432 usbdrd3_1: usb@fe900000 { 433 compatible = "rockchip,rk3399-dwc3"; 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges; 437 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 438 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 439 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 440 clock-names = "ref_clk", "suspend_clk", 441 "bus_clk", "aclk_usb3_rksoc_axi_perf", 442 "aclk_usb3", "grf_clk"; 443 resets = <&cru SRST_A_USB3_OTG1>; 444 reset-names = "usb3-otg"; 445 status = "disabled"; 446 447 usbdrd_dwc3_1: usb@fe900000 { 448 compatible = "snps,dwc3"; 449 reg = <0x0 0xfe900000 0x0 0x100000>; 450 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 451 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 452 <&cru SCLK_USB3OTG1_SUSPEND>; 453 clock-names = "ref", "bus_early", "suspend"; 454 dr_mode = "otg"; 455 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 456 phy-names = "usb2-phy", "usb3-phy"; 457 phy_type = "utmi_wide"; 458 snps,dis_enblslpm_quirk; 459 snps,dis-u2-freeclk-exists-quirk; 460 snps,dis_u2_susphy_quirk; 461 snps,dis-del-phy-power-chg-quirk; 462 snps,dis-tx-ipgap-linecheck-quirk; 463 power-domains = <&power RK3399_PD_USB3>; 464 status = "disabled"; 465 }; 466 }; 467 468 cdn_dp: dp@fec00000 { 469 compatible = "rockchip,rk3399-cdn-dp"; 470 reg = <0x0 0xfec00000 0x0 0x100000>; 471 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 472 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 473 assigned-clock-rates = <100000000>, <200000000>; 474 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 475 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 476 clock-names = "core-clk", "pclk", "spdif", "grf"; 477 phys = <&tcphy0_dp>, <&tcphy1_dp>; 478 power-domains = <&power RK3399_PD_HDCP>; 479 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 480 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 481 reset-names = "spdif", "dptx", "apb", "core"; 482 rockchip,grf = <&grf>; 483 #sound-dai-cells = <1>; 484 status = "disabled"; 485 486 ports { 487 dp_in: port { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 491 dp_in_vopb: endpoint@0 { 492 reg = <0>; 493 remote-endpoint = <&vopb_out_dp>; 494 }; 495 496 dp_in_vopl: endpoint@1 { 497 reg = <1>; 498 remote-endpoint = <&vopl_out_dp>; 499 }; 500 }; 501 }; 502 }; 503 504 gic: interrupt-controller@fee00000 { 505 compatible = "arm,gic-v3"; 506 #interrupt-cells = <4>; 507 #address-cells = <2>; 508 #size-cells = <2>; 509 ranges; 510 interrupt-controller; 511 512 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 513 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 514 <0x0 0xfff00000 0 0x10000>, /* GICC */ 515 <0x0 0xfff10000 0 0x10000>, /* GICH */ 516 <0x0 0xfff20000 0 0x10000>; /* GICV */ 517 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 518 its: interrupt-controller@fee20000 { 519 compatible = "arm,gic-v3-its"; 520 msi-controller; 521 #msi-cells = <1>; 522 reg = <0x0 0xfee20000 0x0 0x20000>; 523 }; 524 525 ppi-partitions { 526 ppi_cluster0: interrupt-partition-0 { 527 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 528 }; 529 530 ppi_cluster1: interrupt-partition-1 { 531 affinity = <&cpu_b0 &cpu_b1>; 532 }; 533 }; 534 }; 535 536 saradc: saradc@ff100000 { 537 compatible = "rockchip,rk3399-saradc"; 538 reg = <0x0 0xff100000 0x0 0x100>; 539 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 540 #io-channel-cells = <1>; 541 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 542 clock-names = "saradc", "apb_pclk"; 543 resets = <&cru SRST_P_SARADC>; 544 reset-names = "saradc-apb"; 545 status = "disabled"; 546 }; 547 548 i2c1: i2c@ff110000 { 549 compatible = "rockchip,rk3399-i2c"; 550 reg = <0x0 0xff110000 0x0 0x1000>; 551 assigned-clocks = <&cru SCLK_I2C1>; 552 assigned-clock-rates = <200000000>; 553 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 554 clock-names = "i2c", "pclk"; 555 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2c1_xfer>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 563 i2c2: i2c@ff120000 { 564 compatible = "rockchip,rk3399-i2c"; 565 reg = <0x0 0xff120000 0x0 0x1000>; 566 assigned-clocks = <&cru SCLK_I2C2>; 567 assigned-clock-rates = <200000000>; 568 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 569 clock-names = "i2c", "pclk"; 570 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&i2c2_xfer>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 i2c3: i2c@ff130000 { 579 compatible = "rockchip,rk3399-i2c"; 580 reg = <0x0 0xff130000 0x0 0x1000>; 581 assigned-clocks = <&cru SCLK_I2C3>; 582 assigned-clock-rates = <200000000>; 583 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 584 clock-names = "i2c", "pclk"; 585 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&i2c3_xfer>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 status = "disabled"; 591 }; 592 593 i2c5: i2c@ff140000 { 594 compatible = "rockchip,rk3399-i2c"; 595 reg = <0x0 0xff140000 0x0 0x1000>; 596 assigned-clocks = <&cru SCLK_I2C5>; 597 assigned-clock-rates = <200000000>; 598 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 599 clock-names = "i2c", "pclk"; 600 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&i2c5_xfer>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 status = "disabled"; 606 }; 607 608 i2c6: i2c@ff150000 { 609 compatible = "rockchip,rk3399-i2c"; 610 reg = <0x0 0xff150000 0x0 0x1000>; 611 assigned-clocks = <&cru SCLK_I2C6>; 612 assigned-clock-rates = <200000000>; 613 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 614 clock-names = "i2c", "pclk"; 615 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&i2c6_xfer>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 i2c7: i2c@ff160000 { 624 compatible = "rockchip,rk3399-i2c"; 625 reg = <0x0 0xff160000 0x0 0x1000>; 626 assigned-clocks = <&cru SCLK_I2C7>; 627 assigned-clock-rates = <200000000>; 628 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 629 clock-names = "i2c", "pclk"; 630 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&i2c7_xfer>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 uart0: serial@ff180000 { 639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 640 reg = <0x0 0xff180000 0x0 0x100>; 641 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 642 clock-names = "baudclk", "apb_pclk"; 643 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 644 reg-shift = <2>; 645 reg-io-width = <4>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&uart0_xfer>; 648 status = "disabled"; 649 }; 650 651 uart1: serial@ff190000 { 652 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 653 reg = <0x0 0xff190000 0x0 0x100>; 654 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 655 clock-names = "baudclk", "apb_pclk"; 656 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 657 reg-shift = <2>; 658 reg-io-width = <4>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&uart1_xfer>; 661 status = "disabled"; 662 }; 663 664 uart2: serial@ff1a0000 { 665 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 666 reg = <0x0 0xff1a0000 0x0 0x100>; 667 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 668 clock-names = "baudclk", "apb_pclk"; 669 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 670 reg-shift = <2>; 671 reg-io-width = <4>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&uart2c_xfer>; 674 status = "disabled"; 675 }; 676 677 uart3: serial@ff1b0000 { 678 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 679 reg = <0x0 0xff1b0000 0x0 0x100>; 680 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 681 clock-names = "baudclk", "apb_pclk"; 682 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 683 reg-shift = <2>; 684 reg-io-width = <4>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&uart3_xfer>; 687 status = "disabled"; 688 }; 689 690 spi0: spi@ff1c0000 { 691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 692 reg = <0x0 0xff1c0000 0x0 0x1000>; 693 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 694 clock-names = "spiclk", "apb_pclk"; 695 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 696 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 697 dma-names = "tx", "rx"; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 705 spi1: spi@ff1d0000 { 706 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 707 reg = <0x0 0xff1d0000 0x0 0x1000>; 708 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 709 clock-names = "spiclk", "apb_pclk"; 710 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 711 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 712 dma-names = "tx", "rx"; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 status = "disabled"; 718 }; 719 720 spi2: spi@ff1e0000 { 721 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 722 reg = <0x0 0xff1e0000 0x0 0x1000>; 723 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 724 clock-names = "spiclk", "apb_pclk"; 725 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 726 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 727 dma-names = "tx", "rx"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "disabled"; 733 }; 734 735 spi4: spi@ff1f0000 { 736 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 737 reg = <0x0 0xff1f0000 0x0 0x1000>; 738 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 739 clock-names = "spiclk", "apb_pclk"; 740 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 741 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 742 dma-names = "tx", "rx"; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 spi5: spi@ff200000 { 751 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 752 reg = <0x0 0xff200000 0x0 0x1000>; 753 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 754 clock-names = "spiclk", "apb_pclk"; 755 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 756 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 757 dma-names = "tx", "rx"; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 760 power-domains = <&power RK3399_PD_SDIOAUDIO>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 766 thermal_zones: thermal-zones { 767 cpu_thermal: cpu { 768 polling-delay-passive = <100>; 769 polling-delay = <1000>; 770 771 thermal-sensors = <&tsadc 0>; 772 773 trips { 774 cpu_alert0: cpu_alert0 { 775 temperature = <70000>; 776 hysteresis = <2000>; 777 type = "passive"; 778 }; 779 cpu_alert1: cpu_alert1 { 780 temperature = <75000>; 781 hysteresis = <2000>; 782 type = "passive"; 783 }; 784 cpu_crit: cpu_crit { 785 temperature = <95000>; 786 hysteresis = <2000>; 787 type = "critical"; 788 }; 789 }; 790 791 cooling-maps { 792 map0 { 793 trip = <&cpu_alert0>; 794 cooling-device = 795 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 796 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 797 }; 798 map1 { 799 trip = <&cpu_alert1>; 800 cooling-device = 801 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 802 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 803 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 804 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 805 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 806 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 807 }; 808 }; 809 }; 810 811 gpu_thermal: gpu { 812 polling-delay-passive = <100>; 813 polling-delay = <1000>; 814 815 thermal-sensors = <&tsadc 1>; 816 817 trips { 818 gpu_alert0: gpu_alert0 { 819 temperature = <75000>; 820 hysteresis = <2000>; 821 type = "passive"; 822 }; 823 gpu_crit: gpu_crit { 824 temperature = <95000>; 825 hysteresis = <2000>; 826 type = "critical"; 827 }; 828 }; 829 830 cooling-maps { 831 map0 { 832 trip = <&gpu_alert0>; 833 cooling-device = 834 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 835 }; 836 }; 837 }; 838 }; 839 840 tsadc: tsadc@ff260000 { 841 compatible = "rockchip,rk3399-tsadc"; 842 reg = <0x0 0xff260000 0x0 0x100>; 843 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 844 assigned-clocks = <&cru SCLK_TSADC>; 845 assigned-clock-rates = <750000>; 846 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 847 clock-names = "tsadc", "apb_pclk"; 848 resets = <&cru SRST_TSADC>; 849 reset-names = "tsadc-apb"; 850 rockchip,grf = <&grf>; 851 rockchip,hw-tshut-temp = <95000>; 852 pinctrl-names = "init", "default", "sleep"; 853 pinctrl-0 = <&otp_pin>; 854 pinctrl-1 = <&otp_out>; 855 pinctrl-2 = <&otp_pin>; 856 #thermal-sensor-cells = <1>; 857 status = "disabled"; 858 }; 859 860 qos_emmc: qos@ffa58000 { 861 compatible = "syscon"; 862 reg = <0x0 0xffa58000 0x0 0x20>; 863 }; 864 865 qos_gmac: qos@ffa5c000 { 866 compatible = "syscon"; 867 reg = <0x0 0xffa5c000 0x0 0x20>; 868 }; 869 870 qos_pcie: qos@ffa60080 { 871 compatible = "syscon"; 872 reg = <0x0 0xffa60080 0x0 0x20>; 873 }; 874 875 qos_usb_host0: qos@ffa60100 { 876 compatible = "syscon"; 877 reg = <0x0 0xffa60100 0x0 0x20>; 878 }; 879 880 qos_usb_host1: qos@ffa60180 { 881 compatible = "syscon"; 882 reg = <0x0 0xffa60180 0x0 0x20>; 883 }; 884 885 qos_usb_otg0: qos@ffa70000 { 886 compatible = "syscon"; 887 reg = <0x0 0xffa70000 0x0 0x20>; 888 }; 889 890 qos_usb_otg1: qos@ffa70080 { 891 compatible = "syscon"; 892 reg = <0x0 0xffa70080 0x0 0x20>; 893 }; 894 895 qos_sd: qos@ffa74000 { 896 compatible = "syscon"; 897 reg = <0x0 0xffa74000 0x0 0x20>; 898 }; 899 900 qos_sdioaudio: qos@ffa76000 { 901 compatible = "syscon"; 902 reg = <0x0 0xffa76000 0x0 0x20>; 903 }; 904 905 qos_hdcp: qos@ffa90000 { 906 compatible = "syscon"; 907 reg = <0x0 0xffa90000 0x0 0x20>; 908 }; 909 910 qos_iep: qos@ffa98000 { 911 compatible = "syscon"; 912 reg = <0x0 0xffa98000 0x0 0x20>; 913 }; 914 915 qos_isp0_m0: qos@ffaa0000 { 916 compatible = "syscon"; 917 reg = <0x0 0xffaa0000 0x0 0x20>; 918 }; 919 920 qos_isp0_m1: qos@ffaa0080 { 921 compatible = "syscon"; 922 reg = <0x0 0xffaa0080 0x0 0x20>; 923 }; 924 925 qos_isp1_m0: qos@ffaa8000 { 926 compatible = "syscon"; 927 reg = <0x0 0xffaa8000 0x0 0x20>; 928 }; 929 930 qos_isp1_m1: qos@ffaa8080 { 931 compatible = "syscon"; 932 reg = <0x0 0xffaa8080 0x0 0x20>; 933 }; 934 935 qos_rga_r: qos@ffab0000 { 936 compatible = "syscon"; 937 reg = <0x0 0xffab0000 0x0 0x20>; 938 }; 939 940 qos_rga_w: qos@ffab0080 { 941 compatible = "syscon"; 942 reg = <0x0 0xffab0080 0x0 0x20>; 943 }; 944 945 qos_video_m0: qos@ffab8000 { 946 compatible = "syscon"; 947 reg = <0x0 0xffab8000 0x0 0x20>; 948 }; 949 950 qos_video_m1_r: qos@ffac0000 { 951 compatible = "syscon"; 952 reg = <0x0 0xffac0000 0x0 0x20>; 953 }; 954 955 qos_video_m1_w: qos@ffac0080 { 956 compatible = "syscon"; 957 reg = <0x0 0xffac0080 0x0 0x20>; 958 }; 959 960 qos_vop_big_r: qos@ffac8000 { 961 compatible = "syscon"; 962 reg = <0x0 0xffac8000 0x0 0x20>; 963 }; 964 965 qos_vop_big_w: qos@ffac8080 { 966 compatible = "syscon"; 967 reg = <0x0 0xffac8080 0x0 0x20>; 968 }; 969 970 qos_vop_little: qos@ffad0000 { 971 compatible = "syscon"; 972 reg = <0x0 0xffad0000 0x0 0x20>; 973 }; 974 975 qos_perihp: qos@ffad8080 { 976 compatible = "syscon"; 977 reg = <0x0 0xffad8080 0x0 0x20>; 978 }; 979 980 qos_gpu: qos@ffae0000 { 981 compatible = "syscon"; 982 reg = <0x0 0xffae0000 0x0 0x20>; 983 }; 984 985 pmu: power-management@ff310000 { 986 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 987 reg = <0x0 0xff310000 0x0 0x1000>; 988 989 /* 990 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 991 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 992 * Some of the power domains are grouped together for every 993 * voltage domain. 994 * The detail contents as below. 995 */ 996 power: power-controller { 997 compatible = "rockchip,rk3399-power-controller"; 998 #power-domain-cells = <1>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 /* These power domains are grouped by VD_CENTER */ 1003 power-domain@RK3399_PD_IEP { 1004 reg = <RK3399_PD_IEP>; 1005 clocks = <&cru ACLK_IEP>, 1006 <&cru HCLK_IEP>; 1007 pm_qos = <&qos_iep>; 1008 }; 1009 power-domain@RK3399_PD_RGA { 1010 reg = <RK3399_PD_RGA>; 1011 clocks = <&cru ACLK_RGA>, 1012 <&cru HCLK_RGA>; 1013 pm_qos = <&qos_rga_r>, 1014 <&qos_rga_w>; 1015 }; 1016 power-domain@RK3399_PD_VCODEC { 1017 reg = <RK3399_PD_VCODEC>; 1018 clocks = <&cru ACLK_VCODEC>, 1019 <&cru HCLK_VCODEC>; 1020 pm_qos = <&qos_video_m0>; 1021 }; 1022 power-domain@RK3399_PD_VDU { 1023 reg = <RK3399_PD_VDU>; 1024 clocks = <&cru ACLK_VDU>, 1025 <&cru HCLK_VDU>, 1026 <&cru SCLK_VDU_CA>, 1027 <&cru SCLK_VDU_CORE>; 1028 pm_qos = <&qos_video_m1_r>, 1029 <&qos_video_m1_w>; 1030 }; 1031 1032 /* These power domains are grouped by VD_GPU */ 1033 power-domain@RK3399_PD_GPU { 1034 reg = <RK3399_PD_GPU>; 1035 clocks = <&cru ACLK_GPU>; 1036 pm_qos = <&qos_gpu>; 1037 }; 1038 1039 /* These power domains are grouped by VD_LOGIC */ 1040 power-domain@RK3399_PD_EDP { 1041 reg = <RK3399_PD_EDP>; 1042 clocks = <&cru PCLK_EDP_CTRL>; 1043 }; 1044 power-domain@RK3399_PD_EMMC { 1045 reg = <RK3399_PD_EMMC>; 1046 clocks = <&cru ACLK_EMMC>; 1047 pm_qos = <&qos_emmc>; 1048 }; 1049 power-domain@RK3399_PD_GMAC { 1050 reg = <RK3399_PD_GMAC>; 1051 clocks = <&cru ACLK_GMAC>, 1052 <&cru PCLK_GMAC>; 1053 pm_qos = <&qos_gmac>; 1054 }; 1055 power-domain@RK3399_PD_SD { 1056 reg = <RK3399_PD_SD>; 1057 clocks = <&cru HCLK_SDMMC>, 1058 <&cru SCLK_SDMMC>; 1059 pm_qos = <&qos_sd>; 1060 }; 1061 power-domain@RK3399_PD_SDIOAUDIO { 1062 reg = <RK3399_PD_SDIOAUDIO>; 1063 clocks = <&cru HCLK_SDIO>; 1064 pm_qos = <&qos_sdioaudio>; 1065 }; 1066 power-domain@RK3399_PD_TCPD0 { 1067 reg = <RK3399_PD_TCPD0>; 1068 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1069 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1070 }; 1071 power-domain@RK3399_PD_TCPD1 { 1072 reg = <RK3399_PD_TCPD1>; 1073 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1074 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1075 }; 1076 power-domain@RK3399_PD_USB3 { 1077 reg = <RK3399_PD_USB3>; 1078 clocks = <&cru ACLK_USB3>; 1079 pm_qos = <&qos_usb_otg0>, 1080 <&qos_usb_otg1>; 1081 }; 1082 power-domain@RK3399_PD_VIO { 1083 reg = <RK3399_PD_VIO>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 power-domain@RK3399_PD_HDCP { 1088 reg = <RK3399_PD_HDCP>; 1089 clocks = <&cru ACLK_HDCP>, 1090 <&cru HCLK_HDCP>, 1091 <&cru PCLK_HDCP>; 1092 pm_qos = <&qos_hdcp>; 1093 }; 1094 power-domain@RK3399_PD_ISP0 { 1095 reg = <RK3399_PD_ISP0>; 1096 clocks = <&cru ACLK_ISP0>, 1097 <&cru HCLK_ISP0>; 1098 pm_qos = <&qos_isp0_m0>, 1099 <&qos_isp0_m1>; 1100 }; 1101 power-domain@RK3399_PD_ISP1 { 1102 reg = <RK3399_PD_ISP1>; 1103 clocks = <&cru ACLK_ISP1>, 1104 <&cru HCLK_ISP1>; 1105 pm_qos = <&qos_isp1_m0>, 1106 <&qos_isp1_m1>; 1107 }; 1108 power-domain@RK3399_PD_VO { 1109 reg = <RK3399_PD_VO>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 power-domain@RK3399_PD_VOPB { 1114 reg = <RK3399_PD_VOPB>; 1115 clocks = <&cru ACLK_VOP0>, 1116 <&cru HCLK_VOP0>; 1117 pm_qos = <&qos_vop_big_r>, 1118 <&qos_vop_big_w>; 1119 }; 1120 power-domain@RK3399_PD_VOPL { 1121 reg = <RK3399_PD_VOPL>; 1122 clocks = <&cru ACLK_VOP1>, 1123 <&cru HCLK_VOP1>; 1124 pm_qos = <&qos_vop_little>; 1125 }; 1126 }; 1127 }; 1128 }; 1129 }; 1130 1131 pmugrf: syscon@ff320000 { 1132 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1133 reg = <0x0 0xff320000 0x0 0x1000>; 1134 1135 pmu_io_domains: io-domains { 1136 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1137 status = "disabled"; 1138 }; 1139 }; 1140 1141 spi3: spi@ff350000 { 1142 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1143 reg = <0x0 0xff350000 0x0 0x1000>; 1144 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1145 clock-names = "spiclk", "apb_pclk"; 1146 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 uart4: serial@ff370000 { 1155 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1156 reg = <0x0 0xff370000 0x0 0x100>; 1157 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1158 clock-names = "baudclk", "apb_pclk"; 1159 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1160 reg-shift = <2>; 1161 reg-io-width = <4>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&uart4_xfer>; 1164 status = "disabled"; 1165 }; 1166 1167 i2c0: i2c@ff3c0000 { 1168 compatible = "rockchip,rk3399-i2c"; 1169 reg = <0x0 0xff3c0000 0x0 0x1000>; 1170 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1171 assigned-clock-rates = <200000000>; 1172 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1173 clock-names = "i2c", "pclk"; 1174 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&i2c0_xfer>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 status = "disabled"; 1180 }; 1181 1182 i2c4: i2c@ff3d0000 { 1183 compatible = "rockchip,rk3399-i2c"; 1184 reg = <0x0 0xff3d0000 0x0 0x1000>; 1185 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1186 assigned-clock-rates = <200000000>; 1187 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1188 clock-names = "i2c", "pclk"; 1189 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&i2c4_xfer>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 i2c8: i2c@ff3e0000 { 1198 compatible = "rockchip,rk3399-i2c"; 1199 reg = <0x0 0xff3e0000 0x0 0x1000>; 1200 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1201 assigned-clock-rates = <200000000>; 1202 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1203 clock-names = "i2c", "pclk"; 1204 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&i2c8_xfer>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 status = "disabled"; 1210 }; 1211 1212 pwm0: pwm@ff420000 { 1213 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1214 reg = <0x0 0xff420000 0x0 0x10>; 1215 #pwm-cells = <3>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&pwm0_pin>; 1218 clocks = <&pmucru PCLK_RKPWM_PMU>; 1219 clock-names = "pwm"; 1220 status = "disabled"; 1221 }; 1222 1223 pwm1: pwm@ff420010 { 1224 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1225 reg = <0x0 0xff420010 0x0 0x10>; 1226 #pwm-cells = <3>; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&pwm1_pin>; 1229 clocks = <&pmucru PCLK_RKPWM_PMU>; 1230 clock-names = "pwm"; 1231 status = "disabled"; 1232 }; 1233 1234 pwm2: pwm@ff420020 { 1235 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1236 reg = <0x0 0xff420020 0x0 0x10>; 1237 #pwm-cells = <3>; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&pwm2_pin>; 1240 clocks = <&pmucru PCLK_RKPWM_PMU>; 1241 clock-names = "pwm"; 1242 status = "disabled"; 1243 }; 1244 1245 pwm3: pwm@ff420030 { 1246 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1247 reg = <0x0 0xff420030 0x0 0x10>; 1248 #pwm-cells = <3>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&pwm3a_pin>; 1251 clocks = <&pmucru PCLK_RKPWM_PMU>; 1252 clock-names = "pwm"; 1253 status = "disabled"; 1254 }; 1255 1256 vpu: video-codec@ff650000 { 1257 compatible = "rockchip,rk3399-vpu"; 1258 reg = <0x0 0xff650000 0x0 0x800>; 1259 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1260 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1261 interrupt-names = "vepu", "vdpu"; 1262 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1263 clock-names = "aclk", "hclk"; 1264 iommus = <&vpu_mmu>; 1265 power-domains = <&power RK3399_PD_VCODEC>; 1266 }; 1267 1268 vpu_mmu: iommu@ff650800 { 1269 compatible = "rockchip,iommu"; 1270 reg = <0x0 0xff650800 0x0 0x40>; 1271 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1272 interrupt-names = "vpu_mmu"; 1273 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1274 clock-names = "aclk", "iface"; 1275 #iommu-cells = <0>; 1276 power-domains = <&power RK3399_PD_VCODEC>; 1277 }; 1278 1279 vdec: video-codec@ff660000 { 1280 compatible = "rockchip,rk3399-vdec"; 1281 reg = <0x0 0xff660000 0x0 0x480>; 1282 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1283 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1284 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1285 clock-names = "axi", "ahb", "cabac", "core"; 1286 iommus = <&vdec_mmu>; 1287 power-domains = <&power RK3399_PD_VDU>; 1288 }; 1289 1290 vdec_mmu: iommu@ff660480 { 1291 compatible = "rockchip,iommu"; 1292 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1293 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1294 interrupt-names = "vdec_mmu"; 1295 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1296 clock-names = "aclk", "iface"; 1297 power-domains = <&power RK3399_PD_VDU>; 1298 #iommu-cells = <0>; 1299 }; 1300 1301 iep_mmu: iommu@ff670800 { 1302 compatible = "rockchip,iommu"; 1303 reg = <0x0 0xff670800 0x0 0x40>; 1304 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1305 interrupt-names = "iep_mmu"; 1306 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1307 clock-names = "aclk", "iface"; 1308 #iommu-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 rga: rga@ff680000 { 1313 compatible = "rockchip,rk3399-rga"; 1314 reg = <0x0 0xff680000 0x0 0x10000>; 1315 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1316 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1317 clock-names = "aclk", "hclk", "sclk"; 1318 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1319 reset-names = "core", "axi", "ahb"; 1320 power-domains = <&power RK3399_PD_RGA>; 1321 }; 1322 1323 efuse0: efuse@ff690000 { 1324 compatible = "rockchip,rk3399-efuse"; 1325 reg = <0x0 0xff690000 0x0 0x80>; 1326 #address-cells = <1>; 1327 #size-cells = <1>; 1328 clocks = <&cru PCLK_EFUSE1024NS>; 1329 clock-names = "pclk_efuse"; 1330 1331 /* Data cells */ 1332 cpu_id: cpu-id@7 { 1333 reg = <0x07 0x10>; 1334 }; 1335 cpub_leakage: cpu-leakage@17 { 1336 reg = <0x17 0x1>; 1337 }; 1338 gpu_leakage: gpu-leakage@18 { 1339 reg = <0x18 0x1>; 1340 }; 1341 center_leakage: center-leakage@19 { 1342 reg = <0x19 0x1>; 1343 }; 1344 cpul_leakage: cpu-leakage@1a { 1345 reg = <0x1a 0x1>; 1346 }; 1347 logic_leakage: logic-leakage@1b { 1348 reg = <0x1b 0x1>; 1349 }; 1350 wafer_info: wafer-info@1c { 1351 reg = <0x1c 0x1>; 1352 }; 1353 }; 1354 1355 pmucru: pmu-clock-controller@ff750000 { 1356 compatible = "rockchip,rk3399-pmucru"; 1357 reg = <0x0 0xff750000 0x0 0x1000>; 1358 rockchip,grf = <&pmugrf>; 1359 #clock-cells = <1>; 1360 #reset-cells = <1>; 1361 assigned-clocks = <&pmucru PLL_PPLL>; 1362 assigned-clock-rates = <676000000>; 1363 }; 1364 1365 cru: clock-controller@ff760000 { 1366 compatible = "rockchip,rk3399-cru"; 1367 reg = <0x0 0xff760000 0x0 0x1000>; 1368 rockchip,grf = <&grf>; 1369 #clock-cells = <1>; 1370 #reset-cells = <1>; 1371 assigned-clocks = 1372 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1373 <&cru PLL_NPLL>, 1374 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1375 <&cru PCLK_PERIHP>, 1376 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1377 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1378 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1379 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1380 <&cru ACLK_GIC_PRE>, 1381 <&cru PCLK_DDR>; 1382 assigned-clock-rates = 1383 <594000000>, <800000000>, 1384 <1000000000>, 1385 <150000000>, <75000000>, 1386 <37500000>, 1387 <100000000>, <100000000>, 1388 <50000000>, <600000000>, 1389 <100000000>, <50000000>, 1390 <400000000>, <400000000>, 1391 <200000000>, 1392 <200000000>; 1393 }; 1394 1395 grf: syscon@ff770000 { 1396 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1397 reg = <0x0 0xff770000 0x0 0x10000>; 1398 #address-cells = <1>; 1399 #size-cells = <1>; 1400 1401 io_domains: io-domains { 1402 compatible = "rockchip,rk3399-io-voltage-domain"; 1403 status = "disabled"; 1404 }; 1405 1406 mipi_dphy_rx0: mipi-dphy-rx0 { 1407 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1408 clocks = <&cru SCLK_MIPIDPHY_REF>, 1409 <&cru SCLK_DPHY_RX0_CFG>, 1410 <&cru PCLK_VIO_GRF>; 1411 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1412 power-domains = <&power RK3399_PD_VIO>; 1413 #phy-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 u2phy0: usb2-phy@e450 { 1418 compatible = "rockchip,rk3399-usb2phy"; 1419 reg = <0xe450 0x10>; 1420 clocks = <&cru SCLK_USB2PHY0_REF>; 1421 clock-names = "phyclk"; 1422 #clock-cells = <0>; 1423 clock-output-names = "clk_usbphy0_480m"; 1424 status = "disabled"; 1425 1426 u2phy0_host: host-port { 1427 #phy-cells = <0>; 1428 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1429 interrupt-names = "linestate"; 1430 status = "disabled"; 1431 }; 1432 1433 u2phy0_otg: otg-port { 1434 #phy-cells = <0>; 1435 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1436 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1437 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1438 interrupt-names = "otg-bvalid", "otg-id", 1439 "linestate"; 1440 status = "disabled"; 1441 }; 1442 }; 1443 1444 u2phy1: usb2-phy@e460 { 1445 compatible = "rockchip,rk3399-usb2phy"; 1446 reg = <0xe460 0x10>; 1447 clocks = <&cru SCLK_USB2PHY1_REF>; 1448 clock-names = "phyclk"; 1449 #clock-cells = <0>; 1450 clock-output-names = "clk_usbphy1_480m"; 1451 status = "disabled"; 1452 1453 u2phy1_host: host-port { 1454 #phy-cells = <0>; 1455 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1456 interrupt-names = "linestate"; 1457 status = "disabled"; 1458 }; 1459 1460 u2phy1_otg: otg-port { 1461 #phy-cells = <0>; 1462 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1463 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1464 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1465 interrupt-names = "otg-bvalid", "otg-id", 1466 "linestate"; 1467 status = "disabled"; 1468 }; 1469 }; 1470 1471 emmc_phy: phy@f780 { 1472 compatible = "rockchip,rk3399-emmc-phy"; 1473 reg = <0xf780 0x24>; 1474 clocks = <&sdhci>; 1475 clock-names = "emmcclk"; 1476 drive-impedance-ohm = <50>; 1477 #phy-cells = <0>; 1478 status = "disabled"; 1479 }; 1480 1481 pcie_phy: pcie-phy { 1482 compatible = "rockchip,rk3399-pcie-phy"; 1483 clocks = <&cru SCLK_PCIEPHY_REF>; 1484 clock-names = "refclk"; 1485 #phy-cells = <1>; 1486 resets = <&cru SRST_PCIEPHY>; 1487 reset-names = "phy"; 1488 status = "disabled"; 1489 }; 1490 }; 1491 1492 tcphy0: phy@ff7c0000 { 1493 compatible = "rockchip,rk3399-typec-phy"; 1494 reg = <0x0 0xff7c0000 0x0 0x40000>; 1495 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1496 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1497 clock-names = "tcpdcore", "tcpdphy-ref"; 1498 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1499 assigned-clock-rates = <50000000>; 1500 power-domains = <&power RK3399_PD_TCPD0>; 1501 resets = <&cru SRST_UPHY0>, 1502 <&cru SRST_UPHY0_PIPE_L00>, 1503 <&cru SRST_P_UPHY0_TCPHY>; 1504 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1505 rockchip,grf = <&grf>; 1506 status = "disabled"; 1507 1508 tcphy0_dp: dp-port { 1509 #phy-cells = <0>; 1510 }; 1511 1512 tcphy0_usb3: usb3-port { 1513 #phy-cells = <0>; 1514 }; 1515 }; 1516 1517 tcphy1: phy@ff800000 { 1518 compatible = "rockchip,rk3399-typec-phy"; 1519 reg = <0x0 0xff800000 0x0 0x40000>; 1520 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1521 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1522 clock-names = "tcpdcore", "tcpdphy-ref"; 1523 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1524 assigned-clock-rates = <50000000>; 1525 power-domains = <&power RK3399_PD_TCPD1>; 1526 resets = <&cru SRST_UPHY1>, 1527 <&cru SRST_UPHY1_PIPE_L00>, 1528 <&cru SRST_P_UPHY1_TCPHY>; 1529 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1530 rockchip,grf = <&grf>; 1531 status = "disabled"; 1532 1533 tcphy1_dp: dp-port { 1534 #phy-cells = <0>; 1535 }; 1536 1537 tcphy1_usb3: usb3-port { 1538 #phy-cells = <0>; 1539 }; 1540 }; 1541 1542 watchdog@ff848000 { 1543 compatible = "snps,dw-wdt"; 1544 reg = <0x0 0xff848000 0x0 0x100>; 1545 clocks = <&cru PCLK_WDT>; 1546 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1547 }; 1548 1549 rktimer: rktimer@ff850000 { 1550 compatible = "rockchip,rk3399-timer"; 1551 reg = <0x0 0xff850000 0x0 0x1000>; 1552 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1553 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1554 clock-names = "pclk", "timer"; 1555 }; 1556 1557 spdif: spdif@ff870000 { 1558 compatible = "rockchip,rk3399-spdif"; 1559 reg = <0x0 0xff870000 0x0 0x1000>; 1560 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1561 dmas = <&dmac_bus 7>; 1562 dma-names = "tx"; 1563 clock-names = "mclk", "hclk"; 1564 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&spdif_bus>; 1567 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1568 #sound-dai-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 1572 i2s0: i2s@ff880000 { 1573 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1574 reg = <0x0 0xff880000 0x0 0x1000>; 1575 rockchip,grf = <&grf>; 1576 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1577 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1578 dma-names = "tx", "rx"; 1579 clock-names = "i2s_clk", "i2s_hclk"; 1580 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&i2s0_8ch_bus>; 1583 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1584 #sound-dai-cells = <0>; 1585 status = "disabled"; 1586 }; 1587 1588 i2s1: i2s@ff890000 { 1589 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1590 reg = <0x0 0xff890000 0x0 0x1000>; 1591 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1592 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1593 dma-names = "tx", "rx"; 1594 clock-names = "i2s_clk", "i2s_hclk"; 1595 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&i2s1_2ch_bus>; 1598 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1599 #sound-dai-cells = <0>; 1600 status = "disabled"; 1601 }; 1602 1603 i2s2: i2s@ff8a0000 { 1604 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1605 reg = <0x0 0xff8a0000 0x0 0x1000>; 1606 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1607 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1608 dma-names = "tx", "rx"; 1609 clock-names = "i2s_clk", "i2s_hclk"; 1610 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1611 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1612 #sound-dai-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 vopl: vop@ff8f0000 { 1617 compatible = "rockchip,rk3399-vop-lit"; 1618 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1619 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1620 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1621 assigned-clock-rates = <400000000>, <100000000>; 1622 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1623 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1624 iommus = <&vopl_mmu>; 1625 power-domains = <&power RK3399_PD_VOPL>; 1626 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1627 reset-names = "axi", "ahb", "dclk"; 1628 status = "disabled"; 1629 1630 vopl_out: port { 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 1634 vopl_out_mipi: endpoint@0 { 1635 reg = <0>; 1636 remote-endpoint = <&mipi_in_vopl>; 1637 }; 1638 1639 vopl_out_edp: endpoint@1 { 1640 reg = <1>; 1641 remote-endpoint = <&edp_in_vopl>; 1642 }; 1643 1644 vopl_out_hdmi: endpoint@2 { 1645 reg = <2>; 1646 remote-endpoint = <&hdmi_in_vopl>; 1647 }; 1648 1649 vopl_out_mipi1: endpoint@3 { 1650 reg = <3>; 1651 remote-endpoint = <&mipi1_in_vopl>; 1652 }; 1653 1654 vopl_out_dp: endpoint@4 { 1655 reg = <4>; 1656 remote-endpoint = <&dp_in_vopl>; 1657 }; 1658 }; 1659 }; 1660 1661 vopl_mmu: iommu@ff8f3f00 { 1662 compatible = "rockchip,iommu"; 1663 reg = <0x0 0xff8f3f00 0x0 0x100>; 1664 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1665 interrupt-names = "vopl_mmu"; 1666 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1667 clock-names = "aclk", "iface"; 1668 power-domains = <&power RK3399_PD_VOPL>; 1669 #iommu-cells = <0>; 1670 status = "disabled"; 1671 }; 1672 1673 vopb: vop@ff900000 { 1674 compatible = "rockchip,rk3399-vop-big"; 1675 reg = <0x0 0xff900000 0x0 0x3efc>; 1676 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1677 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1678 assigned-clock-rates = <400000000>, <100000000>; 1679 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1680 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1681 iommus = <&vopb_mmu>; 1682 power-domains = <&power RK3399_PD_VOPB>; 1683 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1684 reset-names = "axi", "ahb", "dclk"; 1685 status = "disabled"; 1686 1687 vopb_out: port { 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 1691 vopb_out_edp: endpoint@0 { 1692 reg = <0>; 1693 remote-endpoint = <&edp_in_vopb>; 1694 }; 1695 1696 vopb_out_mipi: endpoint@1 { 1697 reg = <1>; 1698 remote-endpoint = <&mipi_in_vopb>; 1699 }; 1700 1701 vopb_out_hdmi: endpoint@2 { 1702 reg = <2>; 1703 remote-endpoint = <&hdmi_in_vopb>; 1704 }; 1705 1706 vopb_out_mipi1: endpoint@3 { 1707 reg = <3>; 1708 remote-endpoint = <&mipi1_in_vopb>; 1709 }; 1710 1711 vopb_out_dp: endpoint@4 { 1712 reg = <4>; 1713 remote-endpoint = <&dp_in_vopb>; 1714 }; 1715 }; 1716 }; 1717 1718 vopb_mmu: iommu@ff903f00 { 1719 compatible = "rockchip,iommu"; 1720 reg = <0x0 0xff903f00 0x0 0x100>; 1721 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1722 interrupt-names = "vopb_mmu"; 1723 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1724 clock-names = "aclk", "iface"; 1725 power-domains = <&power RK3399_PD_VOPB>; 1726 #iommu-cells = <0>; 1727 status = "disabled"; 1728 }; 1729 1730 isp0_mmu: iommu@ff914000 { 1731 compatible = "rockchip,iommu"; 1732 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1733 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1734 interrupt-names = "isp0_mmu"; 1735 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1736 clock-names = "aclk", "iface"; 1737 #iommu-cells = <0>; 1738 power-domains = <&power RK3399_PD_ISP0>; 1739 rockchip,disable-mmu-reset; 1740 }; 1741 1742 isp1_mmu: iommu@ff924000 { 1743 compatible = "rockchip,iommu"; 1744 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1745 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1746 interrupt-names = "isp1_mmu"; 1747 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1748 clock-names = "aclk", "iface"; 1749 #iommu-cells = <0>; 1750 power-domains = <&power RK3399_PD_ISP1>; 1751 rockchip,disable-mmu-reset; 1752 }; 1753 1754 hdmi_sound: hdmi-sound { 1755 compatible = "simple-audio-card"; 1756 simple-audio-card,format = "i2s"; 1757 simple-audio-card,mclk-fs = <256>; 1758 simple-audio-card,name = "hdmi-sound"; 1759 status = "disabled"; 1760 1761 simple-audio-card,cpu { 1762 sound-dai = <&i2s2>; 1763 }; 1764 simple-audio-card,codec { 1765 sound-dai = <&hdmi>; 1766 }; 1767 }; 1768 1769 hdmi: hdmi@ff940000 { 1770 compatible = "rockchip,rk3399-dw-hdmi"; 1771 reg = <0x0 0xff940000 0x0 0x20000>; 1772 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1773 clocks = <&cru PCLK_HDMI_CTRL>, 1774 <&cru SCLK_HDMI_SFR>, 1775 <&cru SCLK_HDMI_CEC>, 1776 <&cru PCLK_VIO_GRF>, 1777 <&cru PLL_VPLL>; 1778 clock-names = "iahb", "isfr", "cec", "grf", "vpll"; 1779 power-domains = <&power RK3399_PD_HDCP>; 1780 reg-io-width = <4>; 1781 rockchip,grf = <&grf>; 1782 #sound-dai-cells = <0>; 1783 status = "disabled"; 1784 1785 ports { 1786 hdmi_in: port { 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 1790 hdmi_in_vopb: endpoint@0 { 1791 reg = <0>; 1792 remote-endpoint = <&vopb_out_hdmi>; 1793 }; 1794 hdmi_in_vopl: endpoint@1 { 1795 reg = <1>; 1796 remote-endpoint = <&vopl_out_hdmi>; 1797 }; 1798 }; 1799 }; 1800 }; 1801 1802 mipi_dsi: mipi@ff960000 { 1803 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1804 reg = <0x0 0xff960000 0x0 0x8000>; 1805 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1806 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1807 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1808 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1809 power-domains = <&power RK3399_PD_VIO>; 1810 resets = <&cru SRST_P_MIPI_DSI0>; 1811 reset-names = "apb"; 1812 rockchip,grf = <&grf>; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 status = "disabled"; 1816 1817 ports { 1818 #address-cells = <1>; 1819 #size-cells = <0>; 1820 1821 mipi_in: port@0 { 1822 reg = <0>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 1826 mipi_in_vopb: endpoint@0 { 1827 reg = <0>; 1828 remote-endpoint = <&vopb_out_mipi>; 1829 }; 1830 mipi_in_vopl: endpoint@1 { 1831 reg = <1>; 1832 remote-endpoint = <&vopl_out_mipi>; 1833 }; 1834 }; 1835 }; 1836 }; 1837 1838 mipi_dsi1: mipi@ff968000 { 1839 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1840 reg = <0x0 0xff968000 0x0 0x8000>; 1841 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1842 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1843 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1844 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1845 power-domains = <&power RK3399_PD_VIO>; 1846 resets = <&cru SRST_P_MIPI_DSI1>; 1847 reset-names = "apb"; 1848 rockchip,grf = <&grf>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 status = "disabled"; 1852 1853 ports { 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 1857 mipi1_in: port@0 { 1858 reg = <0>; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 1862 mipi1_in_vopb: endpoint@0 { 1863 reg = <0>; 1864 remote-endpoint = <&vopb_out_mipi1>; 1865 }; 1866 1867 mipi1_in_vopl: endpoint@1 { 1868 reg = <1>; 1869 remote-endpoint = <&vopl_out_mipi1>; 1870 }; 1871 }; 1872 }; 1873 }; 1874 1875 edp: edp@ff970000 { 1876 compatible = "rockchip,rk3399-edp"; 1877 reg = <0x0 0xff970000 0x0 0x8000>; 1878 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1879 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1880 clock-names = "dp", "pclk", "grf"; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&edp_hpd>; 1883 power-domains = <&power RK3399_PD_EDP>; 1884 resets = <&cru SRST_P_EDP_CTRL>; 1885 reset-names = "dp"; 1886 rockchip,grf = <&grf>; 1887 status = "disabled"; 1888 1889 ports { 1890 #address-cells = <1>; 1891 #size-cells = <0>; 1892 edp_in: port@0 { 1893 reg = <0>; 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 1897 edp_in_vopb: endpoint@0 { 1898 reg = <0>; 1899 remote-endpoint = <&vopb_out_edp>; 1900 }; 1901 1902 edp_in_vopl: endpoint@1 { 1903 reg = <1>; 1904 remote-endpoint = <&vopl_out_edp>; 1905 }; 1906 }; 1907 }; 1908 }; 1909 1910 gpu: gpu@ff9a0000 { 1911 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1912 reg = <0x0 0xff9a0000 0x0 0x10000>; 1913 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1914 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1915 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1916 interrupt-names = "job", "mmu", "gpu"; 1917 clocks = <&cru ACLK_GPU>; 1918 #cooling-cells = <2>; 1919 power-domains = <&power RK3399_PD_GPU>; 1920 status = "disabled"; 1921 }; 1922 1923 pinctrl: pinctrl { 1924 compatible = "rockchip,rk3399-pinctrl"; 1925 rockchip,grf = <&grf>; 1926 rockchip,pmu = <&pmugrf>; 1927 #address-cells = <2>; 1928 #size-cells = <2>; 1929 ranges; 1930 1931 gpio0: gpio0@ff720000 { 1932 compatible = "rockchip,gpio-bank"; 1933 reg = <0x0 0xff720000 0x0 0x100>; 1934 clocks = <&pmucru PCLK_GPIO0_PMU>; 1935 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1936 1937 gpio-controller; 1938 #gpio-cells = <0x2>; 1939 1940 interrupt-controller; 1941 #interrupt-cells = <0x2>; 1942 }; 1943 1944 gpio1: gpio1@ff730000 { 1945 compatible = "rockchip,gpio-bank"; 1946 reg = <0x0 0xff730000 0x0 0x100>; 1947 clocks = <&pmucru PCLK_GPIO1_PMU>; 1948 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1949 1950 gpio-controller; 1951 #gpio-cells = <0x2>; 1952 1953 interrupt-controller; 1954 #interrupt-cells = <0x2>; 1955 }; 1956 1957 gpio2: gpio2@ff780000 { 1958 compatible = "rockchip,gpio-bank"; 1959 reg = <0x0 0xff780000 0x0 0x100>; 1960 clocks = <&cru PCLK_GPIO2>; 1961 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1962 1963 gpio-controller; 1964 #gpio-cells = <0x2>; 1965 1966 interrupt-controller; 1967 #interrupt-cells = <0x2>; 1968 }; 1969 1970 gpio3: gpio3@ff788000 { 1971 compatible = "rockchip,gpio-bank"; 1972 reg = <0x0 0xff788000 0x0 0x100>; 1973 clocks = <&cru PCLK_GPIO3>; 1974 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1975 1976 gpio-controller; 1977 #gpio-cells = <0x2>; 1978 1979 interrupt-controller; 1980 #interrupt-cells = <0x2>; 1981 }; 1982 1983 gpio4: gpio4@ff790000 { 1984 compatible = "rockchip,gpio-bank"; 1985 reg = <0x0 0xff790000 0x0 0x100>; 1986 clocks = <&cru PCLK_GPIO4>; 1987 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1988 1989 gpio-controller; 1990 #gpio-cells = <0x2>; 1991 1992 interrupt-controller; 1993 #interrupt-cells = <0x2>; 1994 }; 1995 1996 pcfg_pull_up: pcfg-pull-up { 1997 bias-pull-up; 1998 }; 1999 2000 pcfg_pull_down: pcfg-pull-down { 2001 bias-pull-down; 2002 }; 2003 2004 pcfg_pull_none: pcfg-pull-none { 2005 bias-disable; 2006 }; 2007 2008 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2009 bias-disable; 2010 drive-strength = <12>; 2011 }; 2012 2013 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2014 bias-disable; 2015 drive-strength = <13>; 2016 }; 2017 2018 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2019 bias-disable; 2020 drive-strength = <18>; 2021 }; 2022 2023 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2024 bias-disable; 2025 drive-strength = <20>; 2026 }; 2027 2028 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2029 bias-pull-up; 2030 drive-strength = <2>; 2031 }; 2032 2033 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2034 bias-pull-up; 2035 drive-strength = <8>; 2036 }; 2037 2038 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2039 bias-pull-up; 2040 drive-strength = <18>; 2041 }; 2042 2043 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2044 bias-pull-up; 2045 drive-strength = <20>; 2046 }; 2047 2048 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2049 bias-pull-down; 2050 drive-strength = <4>; 2051 }; 2052 2053 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2054 bias-pull-down; 2055 drive-strength = <8>; 2056 }; 2057 2058 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2059 bias-pull-down; 2060 drive-strength = <12>; 2061 }; 2062 2063 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2064 bias-pull-down; 2065 drive-strength = <18>; 2066 }; 2067 2068 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2069 bias-pull-down; 2070 drive-strength = <20>; 2071 }; 2072 2073 pcfg_output_high: pcfg-output-high { 2074 output-high; 2075 }; 2076 2077 pcfg_output_low: pcfg-output-low { 2078 output-low; 2079 }; 2080 2081 clock { 2082 clk_32k: clk-32k { 2083 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2084 }; 2085 }; 2086 2087 edp { 2088 edp_hpd: edp-hpd { 2089 rockchip,pins = 2090 <4 RK_PC7 2 &pcfg_pull_none>; 2091 }; 2092 }; 2093 2094 gmac { 2095 rgmii_pins: rgmii-pins { 2096 rockchip,pins = 2097 /* mac_txclk */ 2098 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2099 /* mac_rxclk */ 2100 <3 RK_PB6 1 &pcfg_pull_none>, 2101 /* mac_mdio */ 2102 <3 RK_PB5 1 &pcfg_pull_none>, 2103 /* mac_txen */ 2104 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2105 /* mac_clk */ 2106 <3 RK_PB3 1 &pcfg_pull_none>, 2107 /* mac_rxdv */ 2108 <3 RK_PB1 1 &pcfg_pull_none>, 2109 /* mac_mdc */ 2110 <3 RK_PB0 1 &pcfg_pull_none>, 2111 /* mac_rxd1 */ 2112 <3 RK_PA7 1 &pcfg_pull_none>, 2113 /* mac_rxd0 */ 2114 <3 RK_PA6 1 &pcfg_pull_none>, 2115 /* mac_txd1 */ 2116 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2117 /* mac_txd0 */ 2118 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2119 /* mac_rxd3 */ 2120 <3 RK_PA3 1 &pcfg_pull_none>, 2121 /* mac_rxd2 */ 2122 <3 RK_PA2 1 &pcfg_pull_none>, 2123 /* mac_txd3 */ 2124 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2125 /* mac_txd2 */ 2126 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2127 }; 2128 2129 rmii_pins: rmii-pins { 2130 rockchip,pins = 2131 /* mac_mdio */ 2132 <3 RK_PB5 1 &pcfg_pull_none>, 2133 /* mac_txen */ 2134 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2135 /* mac_clk */ 2136 <3 RK_PB3 1 &pcfg_pull_none>, 2137 /* mac_rxer */ 2138 <3 RK_PB2 1 &pcfg_pull_none>, 2139 /* mac_rxdv */ 2140 <3 RK_PB1 1 &pcfg_pull_none>, 2141 /* mac_mdc */ 2142 <3 RK_PB0 1 &pcfg_pull_none>, 2143 /* mac_rxd1 */ 2144 <3 RK_PA7 1 &pcfg_pull_none>, 2145 /* mac_rxd0 */ 2146 <3 RK_PA6 1 &pcfg_pull_none>, 2147 /* mac_txd1 */ 2148 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2149 /* mac_txd0 */ 2150 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2151 }; 2152 }; 2153 2154 i2c0 { 2155 i2c0_xfer: i2c0-xfer { 2156 rockchip,pins = 2157 <1 RK_PB7 2 &pcfg_pull_none>, 2158 <1 RK_PC0 2 &pcfg_pull_none>; 2159 }; 2160 }; 2161 2162 i2c1 { 2163 i2c1_xfer: i2c1-xfer { 2164 rockchip,pins = 2165 <4 RK_PA2 1 &pcfg_pull_none>, 2166 <4 RK_PA1 1 &pcfg_pull_none>; 2167 }; 2168 }; 2169 2170 i2c2 { 2171 i2c2_xfer: i2c2-xfer { 2172 rockchip,pins = 2173 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2174 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2175 }; 2176 }; 2177 2178 i2c3 { 2179 i2c3_xfer: i2c3-xfer { 2180 rockchip,pins = 2181 <4 RK_PC1 1 &pcfg_pull_none>, 2182 <4 RK_PC0 1 &pcfg_pull_none>; 2183 }; 2184 }; 2185 2186 i2c4 { 2187 i2c4_xfer: i2c4-xfer { 2188 rockchip,pins = 2189 <1 RK_PB4 1 &pcfg_pull_none>, 2190 <1 RK_PB3 1 &pcfg_pull_none>; 2191 }; 2192 }; 2193 2194 i2c5 { 2195 i2c5_xfer: i2c5-xfer { 2196 rockchip,pins = 2197 <3 RK_PB3 2 &pcfg_pull_none>, 2198 <3 RK_PB2 2 &pcfg_pull_none>; 2199 }; 2200 }; 2201 2202 i2c6 { 2203 i2c6_xfer: i2c6-xfer { 2204 rockchip,pins = 2205 <2 RK_PB2 2 &pcfg_pull_none>, 2206 <2 RK_PB1 2 &pcfg_pull_none>; 2207 }; 2208 }; 2209 2210 i2c7 { 2211 i2c7_xfer: i2c7-xfer { 2212 rockchip,pins = 2213 <2 RK_PB0 2 &pcfg_pull_none>, 2214 <2 RK_PA7 2 &pcfg_pull_none>; 2215 }; 2216 }; 2217 2218 i2c8 { 2219 i2c8_xfer: i2c8-xfer { 2220 rockchip,pins = 2221 <1 RK_PC5 1 &pcfg_pull_none>, 2222 <1 RK_PC4 1 &pcfg_pull_none>; 2223 }; 2224 }; 2225 2226 i2s0 { 2227 i2s0_2ch_bus: i2s0-2ch-bus { 2228 rockchip,pins = 2229 <3 RK_PD0 1 &pcfg_pull_none>, 2230 <3 RK_PD1 1 &pcfg_pull_none>, 2231 <3 RK_PD2 1 &pcfg_pull_none>, 2232 <3 RK_PD3 1 &pcfg_pull_none>, 2233 <3 RK_PD7 1 &pcfg_pull_none>, 2234 <4 RK_PA0 1 &pcfg_pull_none>; 2235 }; 2236 2237 i2s0_8ch_bus: i2s0-8ch-bus { 2238 rockchip,pins = 2239 <3 RK_PD0 1 &pcfg_pull_none>, 2240 <3 RK_PD1 1 &pcfg_pull_none>, 2241 <3 RK_PD2 1 &pcfg_pull_none>, 2242 <3 RK_PD3 1 &pcfg_pull_none>, 2243 <3 RK_PD4 1 &pcfg_pull_none>, 2244 <3 RK_PD5 1 &pcfg_pull_none>, 2245 <3 RK_PD6 1 &pcfg_pull_none>, 2246 <3 RK_PD7 1 &pcfg_pull_none>, 2247 <4 RK_PA0 1 &pcfg_pull_none>; 2248 }; 2249 }; 2250 2251 i2s1 { 2252 i2s1_2ch_bus: i2s1-2ch-bus { 2253 rockchip,pins = 2254 <4 RK_PA3 1 &pcfg_pull_none>, 2255 <4 RK_PA4 1 &pcfg_pull_none>, 2256 <4 RK_PA5 1 &pcfg_pull_none>, 2257 <4 RK_PA6 1 &pcfg_pull_none>, 2258 <4 RK_PA7 1 &pcfg_pull_none>; 2259 }; 2260 }; 2261 2262 sdio0 { 2263 sdio0_bus1: sdio0-bus1 { 2264 rockchip,pins = 2265 <2 RK_PC4 1 &pcfg_pull_up>; 2266 }; 2267 2268 sdio0_bus4: sdio0-bus4 { 2269 rockchip,pins = 2270 <2 RK_PC4 1 &pcfg_pull_up>, 2271 <2 RK_PC5 1 &pcfg_pull_up>, 2272 <2 RK_PC6 1 &pcfg_pull_up>, 2273 <2 RK_PC7 1 &pcfg_pull_up>; 2274 }; 2275 2276 sdio0_cmd: sdio0-cmd { 2277 rockchip,pins = 2278 <2 RK_PD0 1 &pcfg_pull_up>; 2279 }; 2280 2281 sdio0_clk: sdio0-clk { 2282 rockchip,pins = 2283 <2 RK_PD1 1 &pcfg_pull_none>; 2284 }; 2285 2286 sdio0_cd: sdio0-cd { 2287 rockchip,pins = 2288 <2 RK_PD2 1 &pcfg_pull_up>; 2289 }; 2290 2291 sdio0_pwr: sdio0-pwr { 2292 rockchip,pins = 2293 <2 RK_PD3 1 &pcfg_pull_up>; 2294 }; 2295 2296 sdio0_bkpwr: sdio0-bkpwr { 2297 rockchip,pins = 2298 <2 RK_PD4 1 &pcfg_pull_up>; 2299 }; 2300 2301 sdio0_wp: sdio0-wp { 2302 rockchip,pins = 2303 <0 RK_PA3 1 &pcfg_pull_up>; 2304 }; 2305 2306 sdio0_int: sdio0-int { 2307 rockchip,pins = 2308 <0 RK_PA4 1 &pcfg_pull_up>; 2309 }; 2310 }; 2311 2312 sdmmc { 2313 sdmmc_bus1: sdmmc-bus1 { 2314 rockchip,pins = 2315 <4 RK_PB0 1 &pcfg_pull_up>; 2316 }; 2317 2318 sdmmc_bus4: sdmmc-bus4 { 2319 rockchip,pins = 2320 <4 RK_PB0 1 &pcfg_pull_up>, 2321 <4 RK_PB1 1 &pcfg_pull_up>, 2322 <4 RK_PB2 1 &pcfg_pull_up>, 2323 <4 RK_PB3 1 &pcfg_pull_up>; 2324 }; 2325 2326 sdmmc_clk: sdmmc-clk { 2327 rockchip,pins = 2328 <4 RK_PB4 1 &pcfg_pull_none>; 2329 }; 2330 2331 sdmmc_cmd: sdmmc-cmd { 2332 rockchip,pins = 2333 <4 RK_PB5 1 &pcfg_pull_up>; 2334 }; 2335 2336 sdmmc_cd: sdmmc-cd { 2337 rockchip,pins = 2338 <0 RK_PA7 1 &pcfg_pull_up>; 2339 }; 2340 2341 sdmmc_wp: sdmmc-wp { 2342 rockchip,pins = 2343 <0 RK_PB0 1 &pcfg_pull_up>; 2344 }; 2345 }; 2346 2347 suspend { 2348 ap_pwroff: ap-pwroff { 2349 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2350 }; 2351 2352 ddrio_pwroff: ddrio-pwroff { 2353 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2354 }; 2355 }; 2356 2357 spdif { 2358 spdif_bus: spdif-bus { 2359 rockchip,pins = 2360 <4 RK_PC5 1 &pcfg_pull_none>; 2361 }; 2362 2363 spdif_bus_1: spdif-bus-1 { 2364 rockchip,pins = 2365 <3 RK_PC0 3 &pcfg_pull_none>; 2366 }; 2367 }; 2368 2369 spi0 { 2370 spi0_clk: spi0-clk { 2371 rockchip,pins = 2372 <3 RK_PA6 2 &pcfg_pull_up>; 2373 }; 2374 spi0_cs0: spi0-cs0 { 2375 rockchip,pins = 2376 <3 RK_PA7 2 &pcfg_pull_up>; 2377 }; 2378 spi0_cs1: spi0-cs1 { 2379 rockchip,pins = 2380 <3 RK_PB0 2 &pcfg_pull_up>; 2381 }; 2382 spi0_tx: spi0-tx { 2383 rockchip,pins = 2384 <3 RK_PA5 2 &pcfg_pull_up>; 2385 }; 2386 spi0_rx: spi0-rx { 2387 rockchip,pins = 2388 <3 RK_PA4 2 &pcfg_pull_up>; 2389 }; 2390 }; 2391 2392 spi1 { 2393 spi1_clk: spi1-clk { 2394 rockchip,pins = 2395 <1 RK_PB1 2 &pcfg_pull_up>; 2396 }; 2397 spi1_cs0: spi1-cs0 { 2398 rockchip,pins = 2399 <1 RK_PB2 2 &pcfg_pull_up>; 2400 }; 2401 spi1_rx: spi1-rx { 2402 rockchip,pins = 2403 <1 RK_PA7 2 &pcfg_pull_up>; 2404 }; 2405 spi1_tx: spi1-tx { 2406 rockchip,pins = 2407 <1 RK_PB0 2 &pcfg_pull_up>; 2408 }; 2409 }; 2410 2411 spi2 { 2412 spi2_clk: spi2-clk { 2413 rockchip,pins = 2414 <2 RK_PB3 1 &pcfg_pull_up>; 2415 }; 2416 spi2_cs0: spi2-cs0 { 2417 rockchip,pins = 2418 <2 RK_PB4 1 &pcfg_pull_up>; 2419 }; 2420 spi2_rx: spi2-rx { 2421 rockchip,pins = 2422 <2 RK_PB1 1 &pcfg_pull_up>; 2423 }; 2424 spi2_tx: spi2-tx { 2425 rockchip,pins = 2426 <2 RK_PB2 1 &pcfg_pull_up>; 2427 }; 2428 }; 2429 2430 spi3 { 2431 spi3_clk: spi3-clk { 2432 rockchip,pins = 2433 <1 RK_PC1 1 &pcfg_pull_up>; 2434 }; 2435 spi3_cs0: spi3-cs0 { 2436 rockchip,pins = 2437 <1 RK_PC2 1 &pcfg_pull_up>; 2438 }; 2439 spi3_rx: spi3-rx { 2440 rockchip,pins = 2441 <1 RK_PB7 1 &pcfg_pull_up>; 2442 }; 2443 spi3_tx: spi3-tx { 2444 rockchip,pins = 2445 <1 RK_PC0 1 &pcfg_pull_up>; 2446 }; 2447 }; 2448 2449 spi4 { 2450 spi4_clk: spi4-clk { 2451 rockchip,pins = 2452 <3 RK_PA2 2 &pcfg_pull_up>; 2453 }; 2454 spi4_cs0: spi4-cs0 { 2455 rockchip,pins = 2456 <3 RK_PA3 2 &pcfg_pull_up>; 2457 }; 2458 spi4_rx: spi4-rx { 2459 rockchip,pins = 2460 <3 RK_PA0 2 &pcfg_pull_up>; 2461 }; 2462 spi4_tx: spi4-tx { 2463 rockchip,pins = 2464 <3 RK_PA1 2 &pcfg_pull_up>; 2465 }; 2466 }; 2467 2468 spi5 { 2469 spi5_clk: spi5-clk { 2470 rockchip,pins = 2471 <2 RK_PC6 2 &pcfg_pull_up>; 2472 }; 2473 spi5_cs0: spi5-cs0 { 2474 rockchip,pins = 2475 <2 RK_PC7 2 &pcfg_pull_up>; 2476 }; 2477 spi5_rx: spi5-rx { 2478 rockchip,pins = 2479 <2 RK_PC4 2 &pcfg_pull_up>; 2480 }; 2481 spi5_tx: spi5-tx { 2482 rockchip,pins = 2483 <2 RK_PC5 2 &pcfg_pull_up>; 2484 }; 2485 }; 2486 2487 testclk { 2488 test_clkout0: test-clkout0 { 2489 rockchip,pins = 2490 <0 RK_PA0 1 &pcfg_pull_none>; 2491 }; 2492 2493 test_clkout1: test-clkout1 { 2494 rockchip,pins = 2495 <2 RK_PD1 2 &pcfg_pull_none>; 2496 }; 2497 2498 test_clkout2: test-clkout2 { 2499 rockchip,pins = 2500 <0 RK_PB0 3 &pcfg_pull_none>; 2501 }; 2502 }; 2503 2504 tsadc { 2505 otp_pin: otp-pin { 2506 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2507 }; 2508 2509 otp_out: otp-out { 2510 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2511 }; 2512 }; 2513 2514 uart0 { 2515 uart0_xfer: uart0-xfer { 2516 rockchip,pins = 2517 <2 RK_PC0 1 &pcfg_pull_up>, 2518 <2 RK_PC1 1 &pcfg_pull_none>; 2519 }; 2520 2521 uart0_cts: uart0-cts { 2522 rockchip,pins = 2523 <2 RK_PC2 1 &pcfg_pull_none>; 2524 }; 2525 2526 uart0_rts: uart0-rts { 2527 rockchip,pins = 2528 <2 RK_PC3 1 &pcfg_pull_none>; 2529 }; 2530 }; 2531 2532 uart1 { 2533 uart1_xfer: uart1-xfer { 2534 rockchip,pins = 2535 <3 RK_PB4 2 &pcfg_pull_up>, 2536 <3 RK_PB5 2 &pcfg_pull_none>; 2537 }; 2538 }; 2539 2540 uart2a { 2541 uart2a_xfer: uart2a-xfer { 2542 rockchip,pins = 2543 <4 RK_PB0 2 &pcfg_pull_up>, 2544 <4 RK_PB1 2 &pcfg_pull_none>; 2545 }; 2546 }; 2547 2548 uart2b { 2549 uart2b_xfer: uart2b-xfer { 2550 rockchip,pins = 2551 <4 RK_PC0 2 &pcfg_pull_up>, 2552 <4 RK_PC1 2 &pcfg_pull_none>; 2553 }; 2554 }; 2555 2556 uart2c { 2557 uart2c_xfer: uart2c-xfer { 2558 rockchip,pins = 2559 <4 RK_PC3 1 &pcfg_pull_up>, 2560 <4 RK_PC4 1 &pcfg_pull_none>; 2561 }; 2562 }; 2563 2564 uart3 { 2565 uart3_xfer: uart3-xfer { 2566 rockchip,pins = 2567 <3 RK_PB6 2 &pcfg_pull_up>, 2568 <3 RK_PB7 2 &pcfg_pull_none>; 2569 }; 2570 2571 uart3_cts: uart3-cts { 2572 rockchip,pins = 2573 <3 RK_PC0 2 &pcfg_pull_none>; 2574 }; 2575 2576 uart3_rts: uart3-rts { 2577 rockchip,pins = 2578 <3 RK_PC1 2 &pcfg_pull_none>; 2579 }; 2580 }; 2581 2582 uart4 { 2583 uart4_xfer: uart4-xfer { 2584 rockchip,pins = 2585 <1 RK_PA7 1 &pcfg_pull_up>, 2586 <1 RK_PB0 1 &pcfg_pull_none>; 2587 }; 2588 }; 2589 2590 uarthdcp { 2591 uarthdcp_xfer: uarthdcp-xfer { 2592 rockchip,pins = 2593 <4 RK_PC5 2 &pcfg_pull_up>, 2594 <4 RK_PC6 2 &pcfg_pull_none>; 2595 }; 2596 }; 2597 2598 pwm0 { 2599 pwm0_pin: pwm0-pin { 2600 rockchip,pins = 2601 <4 RK_PC2 1 &pcfg_pull_none>; 2602 }; 2603 2604 pwm0_pin_pull_down: pwm0-pin-pull-down { 2605 rockchip,pins = 2606 <4 RK_PC2 1 &pcfg_pull_down>; 2607 }; 2608 2609 vop0_pwm_pin: vop0-pwm-pin { 2610 rockchip,pins = 2611 <4 RK_PC2 2 &pcfg_pull_none>; 2612 }; 2613 2614 vop1_pwm_pin: vop1-pwm-pin { 2615 rockchip,pins = 2616 <4 RK_PC2 3 &pcfg_pull_none>; 2617 }; 2618 }; 2619 2620 pwm1 { 2621 pwm1_pin: pwm1-pin { 2622 rockchip,pins = 2623 <4 RK_PC6 1 &pcfg_pull_none>; 2624 }; 2625 2626 pwm1_pin_pull_down: pwm1-pin-pull-down { 2627 rockchip,pins = 2628 <4 RK_PC6 1 &pcfg_pull_down>; 2629 }; 2630 }; 2631 2632 pwm2 { 2633 pwm2_pin: pwm2-pin { 2634 rockchip,pins = 2635 <1 RK_PC3 1 &pcfg_pull_none>; 2636 }; 2637 2638 pwm2_pin_pull_down: pwm2-pin-pull-down { 2639 rockchip,pins = 2640 <1 RK_PC3 1 &pcfg_pull_down>; 2641 }; 2642 }; 2643 2644 pwm3a { 2645 pwm3a_pin: pwm3a-pin { 2646 rockchip,pins = 2647 <0 RK_PA6 1 &pcfg_pull_none>; 2648 }; 2649 }; 2650 2651 pwm3b { 2652 pwm3b_pin: pwm3b-pin { 2653 rockchip,pins = 2654 <1 RK_PB6 1 &pcfg_pull_none>; 2655 }; 2656 }; 2657 2658 hdmi { 2659 hdmi_i2c_xfer: hdmi-i2c-xfer { 2660 rockchip,pins = 2661 <4 RK_PC1 3 &pcfg_pull_none>, 2662 <4 RK_PC0 3 &pcfg_pull_none>; 2663 }; 2664 2665 hdmi_cec: hdmi-cec { 2666 rockchip,pins = 2667 <4 RK_PC7 1 &pcfg_pull_none>; 2668 }; 2669 }; 2670 2671 pcie { 2672 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2673 rockchip,pins = 2674 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2675 }; 2676 2677 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2678 rockchip,pins = 2679 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2680 }; 2681 }; 2682 2683 }; 2684}; 2685