1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11/ { 12 cmn_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17 18 cmn_refclk1: clock-cmnrefclk1 { 19 #clock-cells = <0>; 20 compatible = "fixed-clock"; 21 clock-frequency = <0>; 22 }; 23}; 24 25&cbass_main { 26 msmc_ram: sram@70000000 { 27 compatible = "mmio-sram"; 28 reg = <0x0 0x70000000 0x0 0x800000>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x0 0x0 0x70000000 0x800000>; 32 33 atf-sram@0 { 34 reg = <0x0 0x20000>; 35 }; 36 }; 37 38 scm_conf: scm-conf@100000 { 39 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0x0 0x0 0x00100000 0x1c000>; 44 45 pcie0_ctrl: syscon@4070 { 46 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 47 reg = <0x00004070 0x4>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x4070 0x4070 0x4>; 51 }; 52 53 pcie1_ctrl: syscon@4074 { 54 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 55 reg = <0x00004074 0x4>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges = <0x4074 0x4074 0x4>; 59 }; 60 61 pcie2_ctrl: syscon@4078 { 62 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 63 reg = <0x00004078 0x4>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges = <0x4078 0x4078 0x4>; 67 }; 68 69 pcie3_ctrl: syscon@407c { 70 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 71 reg = <0x0000407c 0x4>; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges = <0x407c 0x407c 0x4>; 75 }; 76 77 serdes_ln_ctrl: mux@4080 { 78 compatible = "mmio-mux"; 79 reg = <0x00004080 0x50>; 80 #mux-control-cells = <1>; 81 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 82 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 83 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 84 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 85 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 86 /* SERDES4 lane0/1/2/3 select */ 87 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 88 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 89 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 90 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 91 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 92 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 93 }; 94 95 usb_serdes_mux: mux-controller@4000 { 96 compatible = "mmio-mux"; 97 #mux-control-cells = <1>; 98 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 99 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 100 }; 101 }; 102 103 gic500: interrupt-controller@1800000 { 104 compatible = "arm,gic-v3"; 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 #interrupt-cells = <3>; 109 interrupt-controller; 110 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 111 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 112 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 113 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 114 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 115 116 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 117 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 118 119 gic_its: msi-controller@1820000 { 120 compatible = "arm,gic-v3-its"; 121 reg = <0x00 0x01820000 0x00 0x10000>; 122 socionext,synquacer-pre-its = <0x1000000 0x400000>; 123 msi-controller; 124 #msi-cells = <1>; 125 }; 126 }; 127 128 main_gpio_intr: interrupt-controller0 { 129 compatible = "ti,sci-intr"; 130 ti,intr-trigger-type = <1>; 131 interrupt-controller; 132 interrupt-parent = <&gic500>; 133 #interrupt-cells = <1>; 134 ti,sci = <&dmsc>; 135 ti,sci-dev-id = <131>; 136 ti,interrupt-ranges = <8 392 56>; 137 }; 138 139 main-navss { 140 compatible = "simple-mfd"; 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 dma-coherent; 145 dma-ranges; 146 147 ti,sci-dev-id = <199>; 148 149 main_navss_intr: interrupt-controller1 { 150 compatible = "ti,sci-intr"; 151 ti,intr-trigger-type = <4>; 152 interrupt-controller; 153 interrupt-parent = <&gic500>; 154 #interrupt-cells = <1>; 155 ti,sci = <&dmsc>; 156 ti,sci-dev-id = <213>; 157 ti,interrupt-ranges = <0 64 64>, 158 <64 448 64>, 159 <128 672 64>; 160 }; 161 162 main_udmass_inta: interrupt-controller@33d00000 { 163 compatible = "ti,sci-inta"; 164 reg = <0x0 0x33d00000 0x0 0x100000>; 165 interrupt-controller; 166 interrupt-parent = <&main_navss_intr>; 167 msi-controller; 168 ti,sci = <&dmsc>; 169 ti,sci-dev-id = <209>; 170 ti,interrupt-ranges = <0 0 256>; 171 }; 172 173 secure_proxy_main: mailbox@32c00000 { 174 compatible = "ti,am654-secure-proxy"; 175 #mbox-cells = <1>; 176 reg-names = "target_data", "rt", "scfg"; 177 reg = <0x00 0x32c00000 0x00 0x100000>, 178 <0x00 0x32400000 0x00 0x100000>, 179 <0x00 0x32800000 0x00 0x100000>; 180 interrupt-names = "rx_011"; 181 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 182 }; 183 184 smmu0: iommu@36600000 { 185 compatible = "arm,smmu-v3"; 186 reg = <0x0 0x36600000 0x0 0x100000>; 187 interrupt-parent = <&gic500>; 188 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 189 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 190 interrupt-names = "eventq", "gerror"; 191 #iommu-cells = <1>; 192 }; 193 194 hwspinlock: spinlock@30e00000 { 195 compatible = "ti,am654-hwspinlock"; 196 reg = <0x00 0x30e00000 0x00 0x1000>; 197 #hwlock-cells = <1>; 198 }; 199 200 mailbox0_cluster0: mailbox@31f80000 { 201 compatible = "ti,am654-mailbox"; 202 reg = <0x00 0x31f80000 0x00 0x200>; 203 #mbox-cells = <1>; 204 ti,mbox-num-users = <4>; 205 ti,mbox-num-fifos = <16>; 206 interrupt-parent = <&main_navss_intr>; 207 }; 208 209 mailbox0_cluster1: mailbox@31f81000 { 210 compatible = "ti,am654-mailbox"; 211 reg = <0x00 0x31f81000 0x00 0x200>; 212 #mbox-cells = <1>; 213 ti,mbox-num-users = <4>; 214 ti,mbox-num-fifos = <16>; 215 interrupt-parent = <&main_navss_intr>; 216 }; 217 218 mailbox0_cluster2: mailbox@31f82000 { 219 compatible = "ti,am654-mailbox"; 220 reg = <0x00 0x31f82000 0x00 0x200>; 221 #mbox-cells = <1>; 222 ti,mbox-num-users = <4>; 223 ti,mbox-num-fifos = <16>; 224 interrupt-parent = <&main_navss_intr>; 225 }; 226 227 mailbox0_cluster3: mailbox@31f83000 { 228 compatible = "ti,am654-mailbox"; 229 reg = <0x00 0x31f83000 0x00 0x200>; 230 #mbox-cells = <1>; 231 ti,mbox-num-users = <4>; 232 ti,mbox-num-fifos = <16>; 233 interrupt-parent = <&main_navss_intr>; 234 }; 235 236 mailbox0_cluster4: mailbox@31f84000 { 237 compatible = "ti,am654-mailbox"; 238 reg = <0x00 0x31f84000 0x00 0x200>; 239 #mbox-cells = <1>; 240 ti,mbox-num-users = <4>; 241 ti,mbox-num-fifos = <16>; 242 interrupt-parent = <&main_navss_intr>; 243 }; 244 245 mailbox0_cluster5: mailbox@31f85000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f85000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 }; 253 254 mailbox0_cluster6: mailbox@31f86000 { 255 compatible = "ti,am654-mailbox"; 256 reg = <0x00 0x31f86000 0x00 0x200>; 257 #mbox-cells = <1>; 258 ti,mbox-num-users = <4>; 259 ti,mbox-num-fifos = <16>; 260 interrupt-parent = <&main_navss_intr>; 261 }; 262 263 mailbox0_cluster7: mailbox@31f87000 { 264 compatible = "ti,am654-mailbox"; 265 reg = <0x00 0x31f87000 0x00 0x200>; 266 #mbox-cells = <1>; 267 ti,mbox-num-users = <4>; 268 ti,mbox-num-fifos = <16>; 269 interrupt-parent = <&main_navss_intr>; 270 }; 271 272 mailbox0_cluster8: mailbox@31f88000 { 273 compatible = "ti,am654-mailbox"; 274 reg = <0x00 0x31f88000 0x00 0x200>; 275 #mbox-cells = <1>; 276 ti,mbox-num-users = <4>; 277 ti,mbox-num-fifos = <16>; 278 interrupt-parent = <&main_navss_intr>; 279 }; 280 281 mailbox0_cluster9: mailbox@31f89000 { 282 compatible = "ti,am654-mailbox"; 283 reg = <0x00 0x31f89000 0x00 0x200>; 284 #mbox-cells = <1>; 285 ti,mbox-num-users = <4>; 286 ti,mbox-num-fifos = <16>; 287 interrupt-parent = <&main_navss_intr>; 288 }; 289 290 mailbox0_cluster10: mailbox@31f8a000 { 291 compatible = "ti,am654-mailbox"; 292 reg = <0x00 0x31f8a000 0x00 0x200>; 293 #mbox-cells = <1>; 294 ti,mbox-num-users = <4>; 295 ti,mbox-num-fifos = <16>; 296 interrupt-parent = <&main_navss_intr>; 297 }; 298 299 mailbox0_cluster11: mailbox@31f8b000 { 300 compatible = "ti,am654-mailbox"; 301 reg = <0x00 0x31f8b000 0x00 0x200>; 302 #mbox-cells = <1>; 303 ti,mbox-num-users = <4>; 304 ti,mbox-num-fifos = <16>; 305 interrupt-parent = <&main_navss_intr>; 306 }; 307 308 main_ringacc: ringacc@3c000000 { 309 compatible = "ti,am654-navss-ringacc"; 310 reg = <0x0 0x3c000000 0x0 0x400000>, 311 <0x0 0x38000000 0x0 0x400000>, 312 <0x0 0x31120000 0x0 0x100>, 313 <0x0 0x33000000 0x0 0x40000>; 314 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 315 ti,num-rings = <1024>; 316 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 317 ti,sci = <&dmsc>; 318 ti,sci-dev-id = <211>; 319 msi-parent = <&main_udmass_inta>; 320 }; 321 322 main_udmap: dma-controller@31150000 { 323 compatible = "ti,j721e-navss-main-udmap"; 324 reg = <0x0 0x31150000 0x0 0x100>, 325 <0x0 0x34000000 0x0 0x100000>, 326 <0x0 0x35000000 0x0 0x100000>; 327 reg-names = "gcfg", "rchanrt", "tchanrt"; 328 msi-parent = <&main_udmass_inta>; 329 #dma-cells = <1>; 330 331 ti,sci = <&dmsc>; 332 ti,sci-dev-id = <212>; 333 ti,ringacc = <&main_ringacc>; 334 335 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 336 <0x0f>, /* TX_HCHAN */ 337 <0x10>; /* TX_UHCHAN */ 338 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 339 <0x0b>, /* RX_HCHAN */ 340 <0x0c>; /* RX_UHCHAN */ 341 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 342 }; 343 344 cpts@310d0000 { 345 compatible = "ti,j721e-cpts"; 346 reg = <0x0 0x310d0000 0x0 0x400>; 347 reg-names = "cpts"; 348 clocks = <&k3_clks 201 1>; 349 clock-names = "cpts"; 350 interrupts-extended = <&main_navss_intr 391>; 351 interrupt-names = "cpts"; 352 ti,cpts-periodic-outputs = <6>; 353 ti,cpts-ext-ts-inputs = <8>; 354 }; 355 }; 356 357 main_crypto: crypto@4e00000 { 358 compatible = "ti,j721e-sa2ul"; 359 reg = <0x0 0x4e00000 0x0 0x1200>; 360 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 361 #address-cells = <2>; 362 #size-cells = <2>; 363 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 364 365 status = "okay"; 366 367 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 368 <&main_udmap 0x4001>; 369 dma-names = "tx", "rx1", "rx2"; 370 371 rng: rng@4e10000 { 372 compatible = "inside-secure,safexcel-eip76"; 373 reg = <0x0 0x4e10000 0x0 0x7d>; 374 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&k3_clks 264 1>; 376 }; 377 }; 378 379 main_pmx0: pinctrl@11c000 { 380 compatible = "pinctrl-single"; 381 /* Proxy 0 addressing */ 382 reg = <0x0 0x11c000 0x0 0x2b4>; 383 #pinctrl-cells = <1>; 384 pinctrl-single,register-width = <32>; 385 pinctrl-single,function-mask = <0xffffffff>; 386 }; 387 388 serdes_wiz0: wiz@5000000 { 389 compatible = "ti,j721e-wiz-16g"; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 393 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 394 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 395 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 396 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 397 num-lanes = <2>; 398 #reset-cells = <1>; 399 ranges = <0x5000000 0x0 0x5000000 0x10000>; 400 401 wiz0_pll0_refclk: pll0-refclk { 402 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 403 #clock-cells = <0>; 404 assigned-clocks = <&wiz0_pll0_refclk>; 405 assigned-clock-parents = <&k3_clks 292 11>; 406 }; 407 408 wiz0_pll1_refclk: pll1-refclk { 409 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 410 #clock-cells = <0>; 411 assigned-clocks = <&wiz0_pll1_refclk>; 412 assigned-clock-parents = <&k3_clks 292 0>; 413 }; 414 415 wiz0_refclk_dig: refclk-dig { 416 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 417 #clock-cells = <0>; 418 assigned-clocks = <&wiz0_refclk_dig>; 419 assigned-clock-parents = <&k3_clks 292 11>; 420 }; 421 422 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 423 clocks = <&wiz0_refclk_dig>; 424 #clock-cells = <0>; 425 }; 426 427 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 428 clocks = <&wiz0_pll1_refclk>; 429 #clock-cells = <0>; 430 }; 431 432 serdes0: serdes@5000000 { 433 compatible = "ti,sierra-phy-t0"; 434 reg-names = "serdes"; 435 reg = <0x5000000 0x10000>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 resets = <&serdes_wiz0 0>; 439 reset-names = "sierra_reset"; 440 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 441 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 442 }; 443 }; 444 445 serdes_wiz1: wiz@5010000 { 446 compatible = "ti,j721e-wiz-16g"; 447 #address-cells = <1>; 448 #size-cells = <1>; 449 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 450 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 451 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 452 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 453 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 454 num-lanes = <2>; 455 #reset-cells = <1>; 456 ranges = <0x5010000 0x0 0x5010000 0x10000>; 457 458 wiz1_pll0_refclk: pll0-refclk { 459 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 460 #clock-cells = <0>; 461 assigned-clocks = <&wiz1_pll0_refclk>; 462 assigned-clock-parents = <&k3_clks 293 13>; 463 }; 464 465 wiz1_pll1_refclk: pll1-refclk { 466 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 467 #clock-cells = <0>; 468 assigned-clocks = <&wiz1_pll1_refclk>; 469 assigned-clock-parents = <&k3_clks 293 0>; 470 }; 471 472 wiz1_refclk_dig: refclk-dig { 473 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 474 #clock-cells = <0>; 475 assigned-clocks = <&wiz1_refclk_dig>; 476 assigned-clock-parents = <&k3_clks 293 13>; 477 }; 478 479 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 480 clocks = <&wiz1_refclk_dig>; 481 #clock-cells = <0>; 482 }; 483 484 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 485 clocks = <&wiz1_pll1_refclk>; 486 #clock-cells = <0>; 487 }; 488 489 serdes1: serdes@5010000 { 490 compatible = "ti,sierra-phy-t0"; 491 reg-names = "serdes"; 492 reg = <0x5010000 0x10000>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 resets = <&serdes_wiz1 0>; 496 reset-names = "sierra_reset"; 497 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 498 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 499 }; 500 }; 501 502 serdes_wiz2: wiz@5020000 { 503 compatible = "ti,j721e-wiz-16g"; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 507 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 508 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 509 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 510 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 511 num-lanes = <2>; 512 #reset-cells = <1>; 513 ranges = <0x5020000 0x0 0x5020000 0x10000>; 514 515 wiz2_pll0_refclk: pll0-refclk { 516 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 517 #clock-cells = <0>; 518 assigned-clocks = <&wiz2_pll0_refclk>; 519 assigned-clock-parents = <&k3_clks 294 11>; 520 }; 521 522 wiz2_pll1_refclk: pll1-refclk { 523 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 524 #clock-cells = <0>; 525 assigned-clocks = <&wiz2_pll1_refclk>; 526 assigned-clock-parents = <&k3_clks 294 0>; 527 }; 528 529 wiz2_refclk_dig: refclk-dig { 530 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 531 #clock-cells = <0>; 532 assigned-clocks = <&wiz2_refclk_dig>; 533 assigned-clock-parents = <&k3_clks 294 11>; 534 }; 535 536 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 537 clocks = <&wiz2_refclk_dig>; 538 #clock-cells = <0>; 539 }; 540 541 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 542 clocks = <&wiz2_pll1_refclk>; 543 #clock-cells = <0>; 544 }; 545 546 serdes2: serdes@5020000 { 547 compatible = "ti,sierra-phy-t0"; 548 reg-names = "serdes"; 549 reg = <0x5020000 0x10000>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 resets = <&serdes_wiz2 0>; 553 reset-names = "sierra_reset"; 554 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 555 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 556 }; 557 }; 558 559 serdes_wiz3: wiz@5030000 { 560 compatible = "ti,j721e-wiz-16g"; 561 #address-cells = <1>; 562 #size-cells = <1>; 563 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 564 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 565 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 566 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 567 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 568 num-lanes = <2>; 569 #reset-cells = <1>; 570 ranges = <0x5030000 0x0 0x5030000 0x10000>; 571 572 wiz3_pll0_refclk: pll0-refclk { 573 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 574 #clock-cells = <0>; 575 assigned-clocks = <&wiz3_pll0_refclk>; 576 assigned-clock-parents = <&k3_clks 295 9>; 577 }; 578 579 wiz3_pll1_refclk: pll1-refclk { 580 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 581 #clock-cells = <0>; 582 assigned-clocks = <&wiz3_pll1_refclk>; 583 assigned-clock-parents = <&k3_clks 295 0>; 584 }; 585 586 wiz3_refclk_dig: refclk-dig { 587 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 588 #clock-cells = <0>; 589 assigned-clocks = <&wiz3_refclk_dig>; 590 assigned-clock-parents = <&k3_clks 295 9>; 591 }; 592 593 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 594 clocks = <&wiz3_refclk_dig>; 595 #clock-cells = <0>; 596 }; 597 598 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 599 clocks = <&wiz3_pll1_refclk>; 600 #clock-cells = <0>; 601 }; 602 603 serdes3: serdes@5030000 { 604 compatible = "ti,sierra-phy-t0"; 605 reg-names = "serdes"; 606 reg = <0x5030000 0x10000>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 resets = <&serdes_wiz3 0>; 610 reset-names = "sierra_reset"; 611 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 612 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 613 }; 614 }; 615 616 pcie0_rc: pcie@2900000 { 617 compatible = "ti,j721e-pcie-host"; 618 reg = <0x00 0x02900000 0x00 0x1000>, 619 <0x00 0x02907000 0x00 0x400>, 620 <0x00 0x0d000000 0x00 0x00800000>, 621 <0x00 0x10000000 0x00 0x00001000>; 622 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 623 interrupt-names = "link_state"; 624 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 625 device_type = "pci"; 626 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 627 max-link-speed = <3>; 628 num-lanes = <2>; 629 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 630 clocks = <&k3_clks 239 1>; 631 clock-names = "fck"; 632 #address-cells = <3>; 633 #size-cells = <2>; 634 bus-range = <0x0 0xff>; 635 vendor-id = <0x104c>; 636 device-id = <0xb00d>; 637 msi-map = <0x0 &gic_its 0x0 0x10000>; 638 dma-coherent; 639 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 640 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 641 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 642 }; 643 644 pcie0_ep: pcie-ep@2900000 { 645 compatible = "ti,j721e-pcie-ep"; 646 reg = <0x00 0x02900000 0x00 0x1000>, 647 <0x00 0x02907000 0x00 0x400>, 648 <0x00 0x0d000000 0x00 0x00800000>, 649 <0x00 0x10000000 0x00 0x08000000>; 650 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 651 interrupt-names = "link_state"; 652 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 653 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 654 max-link-speed = <3>; 655 num-lanes = <2>; 656 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 657 clocks = <&k3_clks 239 1>; 658 clock-names = "fck"; 659 cdns,max-outbound-regions = <16>; 660 max-functions = /bits/ 8 <6>; 661 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 662 dma-coherent; 663 }; 664 665 pcie1_rc: pcie@2910000 { 666 compatible = "ti,j721e-pcie-host"; 667 reg = <0x00 0x02910000 0x00 0x1000>, 668 <0x00 0x02917000 0x00 0x400>, 669 <0x00 0x0d800000 0x00 0x00800000>, 670 <0x00 0x18000000 0x00 0x00001000>; 671 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 672 interrupt-names = "link_state"; 673 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 674 device_type = "pci"; 675 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 676 max-link-speed = <3>; 677 num-lanes = <2>; 678 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 679 clocks = <&k3_clks 240 1>; 680 clock-names = "fck"; 681 #address-cells = <3>; 682 #size-cells = <2>; 683 bus-range = <0x0 0xff>; 684 vendor-id = <0x104c>; 685 device-id = <0xb00d>; 686 msi-map = <0x0 &gic_its 0x10000 0x10000>; 687 dma-coherent; 688 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 689 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 690 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 691 }; 692 693 pcie1_ep: pcie-ep@2910000 { 694 compatible = "ti,j721e-pcie-ep"; 695 reg = <0x00 0x02910000 0x00 0x1000>, 696 <0x00 0x02917000 0x00 0x400>, 697 <0x00 0x0d800000 0x00 0x00800000>, 698 <0x00 0x18000000 0x00 0x08000000>; 699 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 700 interrupt-names = "link_state"; 701 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 702 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 703 max-link-speed = <3>; 704 num-lanes = <2>; 705 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 706 clocks = <&k3_clks 240 1>; 707 clock-names = "fck"; 708 cdns,max-outbound-regions = <16>; 709 max-functions = /bits/ 8 <6>; 710 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 711 dma-coherent; 712 }; 713 714 pcie2_rc: pcie@2920000 { 715 compatible = "ti,j721e-pcie-host"; 716 reg = <0x00 0x02920000 0x00 0x1000>, 717 <0x00 0x02927000 0x00 0x400>, 718 <0x00 0x0e000000 0x00 0x00800000>, 719 <0x44 0x00000000 0x00 0x00001000>; 720 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 721 interrupt-names = "link_state"; 722 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 723 device_type = "pci"; 724 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 725 max-link-speed = <3>; 726 num-lanes = <2>; 727 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 728 clocks = <&k3_clks 241 1>; 729 clock-names = "fck"; 730 #address-cells = <3>; 731 #size-cells = <2>; 732 bus-range = <0x0 0xff>; 733 vendor-id = <0x104c>; 734 device-id = <0xb00d>; 735 msi-map = <0x0 &gic_its 0x20000 0x10000>; 736 dma-coherent; 737 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 738 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 739 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 740 }; 741 742 pcie2_ep: pcie-ep@2920000 { 743 compatible = "ti,j721e-pcie-ep"; 744 reg = <0x00 0x02920000 0x00 0x1000>, 745 <0x00 0x02927000 0x00 0x400>, 746 <0x00 0x0e000000 0x00 0x00800000>, 747 <0x44 0x00000000 0x00 0x08000000>; 748 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 749 interrupt-names = "link_state"; 750 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 751 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 752 max-link-speed = <3>; 753 num-lanes = <2>; 754 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 755 clocks = <&k3_clks 241 1>; 756 clock-names = "fck"; 757 cdns,max-outbound-regions = <16>; 758 max-functions = /bits/ 8 <6>; 759 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 760 dma-coherent; 761 }; 762 763 pcie3_rc: pcie@2930000 { 764 compatible = "ti,j721e-pcie-host"; 765 reg = <0x00 0x02930000 0x00 0x1000>, 766 <0x00 0x02937000 0x00 0x400>, 767 <0x00 0x0e800000 0x00 0x00800000>, 768 <0x44 0x10000000 0x00 0x00001000>; 769 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 770 interrupt-names = "link_state"; 771 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 772 device_type = "pci"; 773 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 774 max-link-speed = <3>; 775 num-lanes = <2>; 776 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 777 clocks = <&k3_clks 242 1>; 778 clock-names = "fck"; 779 #address-cells = <3>; 780 #size-cells = <2>; 781 bus-range = <0x0 0xff>; 782 vendor-id = <0x104c>; 783 device-id = <0xb00d>; 784 msi-map = <0x0 &gic_its 0x30000 0x10000>; 785 dma-coherent; 786 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 787 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 788 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 789 }; 790 791 pcie3_ep: pcie-ep@2930000 { 792 compatible = "ti,j721e-pcie-ep"; 793 reg = <0x00 0x02930000 0x00 0x1000>, 794 <0x00 0x02937000 0x00 0x400>, 795 <0x00 0x0e800000 0x00 0x00800000>, 796 <0x44 0x10000000 0x00 0x08000000>; 797 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 798 interrupt-names = "link_state"; 799 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 800 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 801 max-link-speed = <3>; 802 num-lanes = <2>; 803 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 804 clocks = <&k3_clks 242 1>; 805 clock-names = "fck"; 806 cdns,max-outbound-regions = <16>; 807 max-functions = /bits/ 8 <6>; 808 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 809 dma-coherent; 810 #address-cells = <2>; 811 #size-cells = <2>; 812 }; 813 814 main_uart0: serial@2800000 { 815 compatible = "ti,j721e-uart", "ti,am654-uart"; 816 reg = <0x00 0x02800000 0x00 0x100>; 817 reg-shift = <2>; 818 reg-io-width = <4>; 819 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 820 clock-frequency = <48000000>; 821 current-speed = <115200>; 822 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 823 clocks = <&k3_clks 146 0>; 824 clock-names = "fclk"; 825 }; 826 827 main_uart1: serial@2810000 { 828 compatible = "ti,j721e-uart", "ti,am654-uart"; 829 reg = <0x00 0x02810000 0x00 0x100>; 830 reg-shift = <2>; 831 reg-io-width = <4>; 832 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 833 clock-frequency = <48000000>; 834 current-speed = <115200>; 835 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 836 clocks = <&k3_clks 278 0>; 837 clock-names = "fclk"; 838 }; 839 840 main_uart2: serial@2820000 { 841 compatible = "ti,j721e-uart", "ti,am654-uart"; 842 reg = <0x00 0x02820000 0x00 0x100>; 843 reg-shift = <2>; 844 reg-io-width = <4>; 845 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 846 clock-frequency = <48000000>; 847 current-speed = <115200>; 848 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 849 clocks = <&k3_clks 279 0>; 850 clock-names = "fclk"; 851 }; 852 853 main_uart3: serial@2830000 { 854 compatible = "ti,j721e-uart", "ti,am654-uart"; 855 reg = <0x00 0x02830000 0x00 0x100>; 856 reg-shift = <2>; 857 reg-io-width = <4>; 858 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 859 clock-frequency = <48000000>; 860 current-speed = <115200>; 861 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 862 clocks = <&k3_clks 280 0>; 863 clock-names = "fclk"; 864 }; 865 866 main_uart4: serial@2840000 { 867 compatible = "ti,j721e-uart", "ti,am654-uart"; 868 reg = <0x00 0x02840000 0x00 0x100>; 869 reg-shift = <2>; 870 reg-io-width = <4>; 871 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 872 clock-frequency = <48000000>; 873 current-speed = <115200>; 874 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 875 clocks = <&k3_clks 281 0>; 876 clock-names = "fclk"; 877 }; 878 879 main_uart5: serial@2850000 { 880 compatible = "ti,j721e-uart", "ti,am654-uart"; 881 reg = <0x00 0x02850000 0x00 0x100>; 882 reg-shift = <2>; 883 reg-io-width = <4>; 884 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 885 clock-frequency = <48000000>; 886 current-speed = <115200>; 887 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 888 clocks = <&k3_clks 282 0>; 889 clock-names = "fclk"; 890 }; 891 892 main_uart6: serial@2860000 { 893 compatible = "ti,j721e-uart", "ti,am654-uart"; 894 reg = <0x00 0x02860000 0x00 0x100>; 895 reg-shift = <2>; 896 reg-io-width = <4>; 897 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 898 clock-frequency = <48000000>; 899 current-speed = <115200>; 900 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 901 clocks = <&k3_clks 283 0>; 902 clock-names = "fclk"; 903 }; 904 905 main_uart7: serial@2870000 { 906 compatible = "ti,j721e-uart", "ti,am654-uart"; 907 reg = <0x00 0x02870000 0x00 0x100>; 908 reg-shift = <2>; 909 reg-io-width = <4>; 910 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 911 clock-frequency = <48000000>; 912 current-speed = <115200>; 913 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 914 clocks = <&k3_clks 284 0>; 915 clock-names = "fclk"; 916 }; 917 918 main_uart8: serial@2880000 { 919 compatible = "ti,j721e-uart", "ti,am654-uart"; 920 reg = <0x00 0x02880000 0x00 0x100>; 921 reg-shift = <2>; 922 reg-io-width = <4>; 923 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 924 clock-frequency = <48000000>; 925 current-speed = <115200>; 926 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 927 clocks = <&k3_clks 285 0>; 928 clock-names = "fclk"; 929 }; 930 931 main_uart9: serial@2890000 { 932 compatible = "ti,j721e-uart", "ti,am654-uart"; 933 reg = <0x00 0x02890000 0x00 0x100>; 934 reg-shift = <2>; 935 reg-io-width = <4>; 936 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 937 clock-frequency = <48000000>; 938 current-speed = <115200>; 939 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 940 clocks = <&k3_clks 286 0>; 941 clock-names = "fclk"; 942 }; 943 944 main_gpio0: gpio@600000 { 945 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 946 reg = <0x0 0x00600000 0x0 0x100>; 947 gpio-controller; 948 #gpio-cells = <2>; 949 interrupt-parent = <&main_gpio_intr>; 950 interrupts = <256>, <257>, <258>, <259>, 951 <260>, <261>, <262>, <263>; 952 interrupt-controller; 953 #interrupt-cells = <2>; 954 ti,ngpio = <128>; 955 ti,davinci-gpio-unbanked = <0>; 956 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 957 clocks = <&k3_clks 105 0>; 958 clock-names = "gpio"; 959 }; 960 961 main_gpio1: gpio@601000 { 962 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 963 reg = <0x0 0x00601000 0x0 0x100>; 964 gpio-controller; 965 #gpio-cells = <2>; 966 interrupt-parent = <&main_gpio_intr>; 967 interrupts = <288>, <289>, <290>; 968 interrupt-controller; 969 #interrupt-cells = <2>; 970 ti,ngpio = <36>; 971 ti,davinci-gpio-unbanked = <0>; 972 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 973 clocks = <&k3_clks 106 0>; 974 clock-names = "gpio"; 975 }; 976 977 main_gpio2: gpio@610000 { 978 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 979 reg = <0x0 0x00610000 0x0 0x100>; 980 gpio-controller; 981 #gpio-cells = <2>; 982 interrupt-parent = <&main_gpio_intr>; 983 interrupts = <264>, <265>, <266>, <267>, 984 <268>, <269>, <270>, <271>; 985 interrupt-controller; 986 #interrupt-cells = <2>; 987 ti,ngpio = <128>; 988 ti,davinci-gpio-unbanked = <0>; 989 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 990 clocks = <&k3_clks 107 0>; 991 clock-names = "gpio"; 992 }; 993 994 main_gpio3: gpio@611000 { 995 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 996 reg = <0x0 0x00611000 0x0 0x100>; 997 gpio-controller; 998 #gpio-cells = <2>; 999 interrupt-parent = <&main_gpio_intr>; 1000 interrupts = <292>, <293>, <294>; 1001 interrupt-controller; 1002 #interrupt-cells = <2>; 1003 ti,ngpio = <36>; 1004 ti,davinci-gpio-unbanked = <0>; 1005 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1006 clocks = <&k3_clks 108 0>; 1007 clock-names = "gpio"; 1008 }; 1009 1010 main_gpio4: gpio@620000 { 1011 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1012 reg = <0x0 0x00620000 0x0 0x100>; 1013 gpio-controller; 1014 #gpio-cells = <2>; 1015 interrupt-parent = <&main_gpio_intr>; 1016 interrupts = <272>, <273>, <274>, <275>, 1017 <276>, <277>, <278>, <279>; 1018 interrupt-controller; 1019 #interrupt-cells = <2>; 1020 ti,ngpio = <128>; 1021 ti,davinci-gpio-unbanked = <0>; 1022 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1023 clocks = <&k3_clks 109 0>; 1024 clock-names = "gpio"; 1025 }; 1026 1027 main_gpio5: gpio@621000 { 1028 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1029 reg = <0x0 0x00621000 0x0 0x100>; 1030 gpio-controller; 1031 #gpio-cells = <2>; 1032 interrupt-parent = <&main_gpio_intr>; 1033 interrupts = <296>, <297>, <298>; 1034 interrupt-controller; 1035 #interrupt-cells = <2>; 1036 ti,ngpio = <36>; 1037 ti,davinci-gpio-unbanked = <0>; 1038 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1039 clocks = <&k3_clks 110 0>; 1040 clock-names = "gpio"; 1041 }; 1042 1043 main_gpio6: gpio@630000 { 1044 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1045 reg = <0x0 0x00630000 0x0 0x100>; 1046 gpio-controller; 1047 #gpio-cells = <2>; 1048 interrupt-parent = <&main_gpio_intr>; 1049 interrupts = <280>, <281>, <282>, <283>, 1050 <284>, <285>, <286>, <287>; 1051 interrupt-controller; 1052 #interrupt-cells = <2>; 1053 ti,ngpio = <128>; 1054 ti,davinci-gpio-unbanked = <0>; 1055 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1056 clocks = <&k3_clks 111 0>; 1057 clock-names = "gpio"; 1058 }; 1059 1060 main_gpio7: gpio@631000 { 1061 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1062 reg = <0x0 0x00631000 0x0 0x100>; 1063 gpio-controller; 1064 #gpio-cells = <2>; 1065 interrupt-parent = <&main_gpio_intr>; 1066 interrupts = <300>, <301>, <302>; 1067 interrupt-controller; 1068 #interrupt-cells = <2>; 1069 ti,ngpio = <36>; 1070 ti,davinci-gpio-unbanked = <0>; 1071 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1072 clocks = <&k3_clks 112 0>; 1073 clock-names = "gpio"; 1074 }; 1075 1076 main_sdhci0: sdhci@4f80000 { 1077 compatible = "ti,j721e-sdhci-8bit"; 1078 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1079 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1080 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1081 clock-names = "clk_xin", "clk_ahb"; 1082 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 1083 assigned-clocks = <&k3_clks 91 1>; 1084 assigned-clock-parents = <&k3_clks 91 2>; 1085 bus-width = <8>; 1086 mmc-hs400-1_8v; 1087 mmc-ddr-1_8v; 1088 ti,otap-del-sel = <0x2>; 1089 ti,trm-icp = <0x8>; 1090 ti,strobe-sel = <0x77>; 1091 dma-coherent; 1092 }; 1093 1094 main_sdhci1: sdhci@4fb0000 { 1095 compatible = "ti,j721e-sdhci-4bit"; 1096 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1097 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1098 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1099 clock-names = "clk_xin", "clk_ahb"; 1100 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 1101 assigned-clocks = <&k3_clks 92 0>; 1102 assigned-clock-parents = <&k3_clks 92 1>; 1103 ti,otap-del-sel = <0x2>; 1104 ti,trm-icp = <0x8>; 1105 ti,clkbuf-sel = <0x7>; 1106 dma-coherent; 1107 no-1-8-v; 1108 }; 1109 1110 main_sdhci2: sdhci@4f98000 { 1111 compatible = "ti,j721e-sdhci-4bit"; 1112 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1113 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1114 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1115 clock-names = "clk_xin", "clk_ahb"; 1116 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 1117 assigned-clocks = <&k3_clks 93 0>; 1118 assigned-clock-parents = <&k3_clks 93 1>; 1119 ti,otap-del-sel = <0x2>; 1120 ti,trm-icp = <0x8>; 1121 ti,clkbuf-sel = <0x7>; 1122 dma-coherent; 1123 no-1-8-v; 1124 }; 1125 1126 usbss0: cdns-usb@4104000 { 1127 compatible = "ti,j721e-usb"; 1128 reg = <0x00 0x4104000 0x00 0x100>; 1129 dma-coherent; 1130 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1131 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1132 clock-names = "ref", "lpm"; 1133 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1134 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1135 #address-cells = <2>; 1136 #size-cells = <2>; 1137 ranges; 1138 1139 usb0: usb@6000000 { 1140 compatible = "cdns,usb3"; 1141 reg = <0x00 0x6000000 0x00 0x10000>, 1142 <0x00 0x6010000 0x00 0x10000>, 1143 <0x00 0x6020000 0x00 0x10000>; 1144 reg-names = "otg", "xhci", "dev"; 1145 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1147 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1148 interrupt-names = "host", 1149 "peripheral", 1150 "otg"; 1151 maximum-speed = "super-speed"; 1152 dr_mode = "otg"; 1153 }; 1154 }; 1155 1156 usbss1: cdns-usb@4114000 { 1157 compatible = "ti,j721e-usb"; 1158 reg = <0x00 0x4114000 0x00 0x100>; 1159 dma-coherent; 1160 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1161 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1162 clock-names = "ref", "lpm"; 1163 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1164 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1165 #address-cells = <2>; 1166 #size-cells = <2>; 1167 ranges; 1168 1169 usb1: usb@6400000 { 1170 compatible = "cdns,usb3"; 1171 reg = <0x00 0x6400000 0x00 0x10000>, 1172 <0x00 0x6410000 0x00 0x10000>, 1173 <0x00 0x6420000 0x00 0x10000>; 1174 reg-names = "otg", "xhci", "dev"; 1175 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1176 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1178 interrupt-names = "host", 1179 "peripheral", 1180 "otg"; 1181 maximum-speed = "super-speed"; 1182 dr_mode = "otg"; 1183 }; 1184 }; 1185 1186 main_i2c0: i2c@2000000 { 1187 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1188 reg = <0x0 0x2000000 0x0 0x100>; 1189 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 clock-names = "fck"; 1193 clocks = <&k3_clks 187 0>; 1194 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1195 }; 1196 1197 main_i2c1: i2c@2010000 { 1198 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1199 reg = <0x0 0x2010000 0x0 0x100>; 1200 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 clock-names = "fck"; 1204 clocks = <&k3_clks 188 0>; 1205 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1206 }; 1207 1208 main_i2c2: i2c@2020000 { 1209 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1210 reg = <0x0 0x2020000 0x0 0x100>; 1211 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 clock-names = "fck"; 1215 clocks = <&k3_clks 189 0>; 1216 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1217 }; 1218 1219 main_i2c3: i2c@2030000 { 1220 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1221 reg = <0x0 0x2030000 0x0 0x100>; 1222 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 clock-names = "fck"; 1226 clocks = <&k3_clks 190 0>; 1227 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1228 }; 1229 1230 main_i2c4: i2c@2040000 { 1231 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1232 reg = <0x0 0x2040000 0x0 0x100>; 1233 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 clock-names = "fck"; 1237 clocks = <&k3_clks 191 0>; 1238 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1239 }; 1240 1241 main_i2c5: i2c@2050000 { 1242 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1243 reg = <0x0 0x2050000 0x0 0x100>; 1244 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 clock-names = "fck"; 1248 clocks = <&k3_clks 192 0>; 1249 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1250 }; 1251 1252 main_i2c6: i2c@2060000 { 1253 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1254 reg = <0x0 0x2060000 0x0 0x100>; 1255 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 clock-names = "fck"; 1259 clocks = <&k3_clks 193 0>; 1260 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1261 }; 1262 1263 ufs_wrapper: ufs-wrapper@4e80000 { 1264 compatible = "ti,j721e-ufs"; 1265 reg = <0x0 0x4e80000 0x0 0x100>; 1266 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1267 clocks = <&k3_clks 277 1>; 1268 assigned-clocks = <&k3_clks 277 1>; 1269 assigned-clock-parents = <&k3_clks 277 4>; 1270 ranges; 1271 #address-cells = <2>; 1272 #size-cells = <2>; 1273 1274 ufs@4e84000 { 1275 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1276 reg = <0x0 0x4e84000 0x0 0x10000>; 1277 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1278 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1279 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1280 clock-names = "core_clk", "phy_clk", "ref_clk"; 1281 dma-coherent; 1282 }; 1283 }; 1284 1285 dss: dss@4a00000 { 1286 compatible = "ti,j721e-dss"; 1287 reg = 1288 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1289 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1290 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1291 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1292 1293 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1294 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1295 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1296 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1297 1298 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1299 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1300 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1301 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1302 1303 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1304 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1305 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1306 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1307 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1308 1309 reg-names = "common_m", "common_s0", 1310 "common_s1", "common_s2", 1311 "vidl1", "vidl2","vid1","vid2", 1312 "ovr1", "ovr2", "ovr3", "ovr4", 1313 "vp1", "vp2", "vp3", "vp4", 1314 "wb"; 1315 1316 clocks = <&k3_clks 152 0>, 1317 <&k3_clks 152 1>, 1318 <&k3_clks 152 4>, 1319 <&k3_clks 152 9>, 1320 <&k3_clks 152 13>; 1321 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1322 1323 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1324 1325 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1329 interrupt-names = "common_m", 1330 "common_s0", 1331 "common_s1", 1332 "common_s2"; 1333 1334 status = "disabled"; 1335 1336 dss_ports: ports { 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 }; 1340 }; 1341 1342 mcasp0: mcasp@2b00000 { 1343 compatible = "ti,am33xx-mcasp-audio"; 1344 reg = <0x0 0x02b00000 0x0 0x2000>, 1345 <0x0 0x02b08000 0x0 0x1000>; 1346 reg-names = "mpu","dat"; 1347 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1349 interrupt-names = "tx", "rx"; 1350 1351 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1352 dma-names = "tx", "rx"; 1353 1354 clocks = <&k3_clks 174 1>; 1355 clock-names = "fck"; 1356 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1357 1358 status = "disabled"; 1359 }; 1360 1361 mcasp1: mcasp@2b10000 { 1362 compatible = "ti,am33xx-mcasp-audio"; 1363 reg = <0x0 0x02b10000 0x0 0x2000>, 1364 <0x0 0x02b18000 0x0 0x1000>; 1365 reg-names = "mpu","dat"; 1366 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1368 interrupt-names = "tx", "rx"; 1369 1370 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1371 dma-names = "tx", "rx"; 1372 1373 clocks = <&k3_clks 175 1>; 1374 clock-names = "fck"; 1375 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1376 1377 status = "disabled"; 1378 }; 1379 1380 mcasp2: mcasp@2b20000 { 1381 compatible = "ti,am33xx-mcasp-audio"; 1382 reg = <0x0 0x02b20000 0x0 0x2000>, 1383 <0x0 0x02b28000 0x0 0x1000>; 1384 reg-names = "mpu","dat"; 1385 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1387 interrupt-names = "tx", "rx"; 1388 1389 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1390 dma-names = "tx", "rx"; 1391 1392 clocks = <&k3_clks 176 1>; 1393 clock-names = "fck"; 1394 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1395 1396 status = "disabled"; 1397 }; 1398 1399 mcasp3: mcasp@2b30000 { 1400 compatible = "ti,am33xx-mcasp-audio"; 1401 reg = <0x0 0x02b30000 0x0 0x2000>, 1402 <0x0 0x02b38000 0x0 0x1000>; 1403 reg-names = "mpu","dat"; 1404 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1406 interrupt-names = "tx", "rx"; 1407 1408 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1409 dma-names = "tx", "rx"; 1410 1411 clocks = <&k3_clks 177 1>; 1412 clock-names = "fck"; 1413 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1414 1415 status = "disabled"; 1416 }; 1417 1418 mcasp4: mcasp@2b40000 { 1419 compatible = "ti,am33xx-mcasp-audio"; 1420 reg = <0x0 0x02b40000 0x0 0x2000>, 1421 <0x0 0x02b48000 0x0 0x1000>; 1422 reg-names = "mpu","dat"; 1423 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1425 interrupt-names = "tx", "rx"; 1426 1427 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1428 dma-names = "tx", "rx"; 1429 1430 clocks = <&k3_clks 178 1>; 1431 clock-names = "fck"; 1432 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1433 1434 status = "disabled"; 1435 }; 1436 1437 mcasp5: mcasp@2b50000 { 1438 compatible = "ti,am33xx-mcasp-audio"; 1439 reg = <0x0 0x02b50000 0x0 0x2000>, 1440 <0x0 0x02b58000 0x0 0x1000>; 1441 reg-names = "mpu","dat"; 1442 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1444 interrupt-names = "tx", "rx"; 1445 1446 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1447 dma-names = "tx", "rx"; 1448 1449 clocks = <&k3_clks 179 1>; 1450 clock-names = "fck"; 1451 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1452 1453 status = "disabled"; 1454 }; 1455 1456 mcasp6: mcasp@2b60000 { 1457 compatible = "ti,am33xx-mcasp-audio"; 1458 reg = <0x0 0x02b60000 0x0 0x2000>, 1459 <0x0 0x02b68000 0x0 0x1000>; 1460 reg-names = "mpu","dat"; 1461 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1463 interrupt-names = "tx", "rx"; 1464 1465 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1466 dma-names = "tx", "rx"; 1467 1468 clocks = <&k3_clks 180 1>; 1469 clock-names = "fck"; 1470 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1471 1472 status = "disabled"; 1473 }; 1474 1475 mcasp7: mcasp@2b70000 { 1476 compatible = "ti,am33xx-mcasp-audio"; 1477 reg = <0x0 0x02b70000 0x0 0x2000>, 1478 <0x0 0x02b78000 0x0 0x1000>; 1479 reg-names = "mpu","dat"; 1480 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1482 interrupt-names = "tx", "rx"; 1483 1484 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1485 dma-names = "tx", "rx"; 1486 1487 clocks = <&k3_clks 181 1>; 1488 clock-names = "fck"; 1489 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1490 1491 status = "disabled"; 1492 }; 1493 1494 mcasp8: mcasp@2b80000 { 1495 compatible = "ti,am33xx-mcasp-audio"; 1496 reg = <0x0 0x02b80000 0x0 0x2000>, 1497 <0x0 0x02b88000 0x0 0x1000>; 1498 reg-names = "mpu","dat"; 1499 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1501 interrupt-names = "tx", "rx"; 1502 1503 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1504 dma-names = "tx", "rx"; 1505 1506 clocks = <&k3_clks 182 1>; 1507 clock-names = "fck"; 1508 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1509 1510 status = "disabled"; 1511 }; 1512 1513 mcasp9: mcasp@2b90000 { 1514 compatible = "ti,am33xx-mcasp-audio"; 1515 reg = <0x0 0x02b90000 0x0 0x2000>, 1516 <0x0 0x02b98000 0x0 0x1000>; 1517 reg-names = "mpu","dat"; 1518 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1520 interrupt-names = "tx", "rx"; 1521 1522 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1523 dma-names = "tx", "rx"; 1524 1525 clocks = <&k3_clks 183 1>; 1526 clock-names = "fck"; 1527 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1528 1529 status = "disabled"; 1530 }; 1531 1532 mcasp10: mcasp@2ba0000 { 1533 compatible = "ti,am33xx-mcasp-audio"; 1534 reg = <0x0 0x02ba0000 0x0 0x2000>, 1535 <0x0 0x02ba8000 0x0 0x1000>; 1536 reg-names = "mpu","dat"; 1537 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1539 interrupt-names = "tx", "rx"; 1540 1541 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1542 dma-names = "tx", "rx"; 1543 1544 clocks = <&k3_clks 184 1>; 1545 clock-names = "fck"; 1546 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1547 1548 status = "disabled"; 1549 }; 1550 1551 mcasp11: mcasp@2bb0000 { 1552 compatible = "ti,am33xx-mcasp-audio"; 1553 reg = <0x0 0x02bb0000 0x0 0x2000>, 1554 <0x0 0x02bb8000 0x0 0x1000>; 1555 reg-names = "mpu","dat"; 1556 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1558 interrupt-names = "tx", "rx"; 1559 1560 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1561 dma-names = "tx", "rx"; 1562 1563 clocks = <&k3_clks 185 1>; 1564 clock-names = "fck"; 1565 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1566 1567 status = "disabled"; 1568 }; 1569 1570 watchdog0: watchdog@2200000 { 1571 compatible = "ti,j7-rti-wdt"; 1572 reg = <0x0 0x2200000 0x0 0x100>; 1573 clocks = <&k3_clks 252 1>; 1574 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1575 assigned-clocks = <&k3_clks 252 1>; 1576 assigned-clock-parents = <&k3_clks 252 5>; 1577 }; 1578 1579 watchdog1: watchdog@2210000 { 1580 compatible = "ti,j7-rti-wdt"; 1581 reg = <0x0 0x2210000 0x0 0x100>; 1582 clocks = <&k3_clks 253 1>; 1583 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1584 assigned-clocks = <&k3_clks 253 1>; 1585 assigned-clock-parents = <&k3_clks 253 5>; 1586 }; 1587 1588 c66_0: dsp@4d80800000 { 1589 compatible = "ti,j721e-c66-dsp"; 1590 reg = <0x4d 0x80800000 0x00 0x00048000>, 1591 <0x4d 0x80e00000 0x00 0x00008000>, 1592 <0x4d 0x80f00000 0x00 0x00008000>; 1593 reg-names = "l2sram", "l1pram", "l1dram"; 1594 ti,sci = <&dmsc>; 1595 ti,sci-dev-id = <142>; 1596 ti,sci-proc-ids = <0x03 0xff>; 1597 resets = <&k3_reset 142 1>; 1598 firmware-name = "j7-c66_0-fw"; 1599 }; 1600 1601 c66_1: dsp@4d81800000 { 1602 compatible = "ti,j721e-c66-dsp"; 1603 reg = <0x4d 0x81800000 0x00 0x00048000>, 1604 <0x4d 0x81e00000 0x00 0x00008000>, 1605 <0x4d 0x81f00000 0x00 0x00008000>; 1606 reg-names = "l2sram", "l1pram", "l1dram"; 1607 ti,sci = <&dmsc>; 1608 ti,sci-dev-id = <143>; 1609 ti,sci-proc-ids = <0x04 0xff>; 1610 resets = <&k3_reset 143 1>; 1611 firmware-name = "j7-c66_1-fw"; 1612 }; 1613 1614 c71_0: dsp@64800000 { 1615 compatible = "ti,j721e-c71-dsp"; 1616 reg = <0x00 0x64800000 0x00 0x00080000>, 1617 <0x00 0x64e00000 0x00 0x0000c000>; 1618 reg-names = "l2sram", "l1dram"; 1619 ti,sci = <&dmsc>; 1620 ti,sci-dev-id = <15>; 1621 ti,sci-proc-ids = <0x30 0xff>; 1622 resets = <&k3_reset 15 1>; 1623 firmware-name = "j7-c71_0-fw"; 1624 }; 1625}; 1626