1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Based on arch/arm/include/asm/io.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8 #ifndef __ASM_IO_H
9 #define __ASM_IO_H
10
11 #include <linux/types.h>
12 #include <linux/log_mmiorw.h>
13 #include <linux/pgtable.h>
14
15 #include <asm/byteorder.h>
16 #include <asm/barrier.h>
17 #include <asm/memory.h>
18 #include <asm/early_ioremap.h>
19 #include <asm/alternative.h>
20 #include <asm/cpufeature.h>
21
22 /*
23 * Generic IO read/write. These perform native-endian accesses.
24 */
25 #define __raw_writeb __raw_writeb
__raw_writeb(u8 val,volatile void __iomem * addr)26 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
27 {
28 log_write_mmio(val, 8, addr);
29 asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
30 }
31
32 #define __raw_writew __raw_writew
__raw_writew(u16 val,volatile void __iomem * addr)33 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
34 {
35 log_write_mmio(val, 16, addr);
36 asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
37 }
38
39 #define __raw_writel __raw_writel
__raw_writel(u32 val,volatile void __iomem * addr)40 static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr)
41 {
42 log_write_mmio(val, 32, addr);
43 asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
44 }
45
46 #define __raw_writeq __raw_writeq
__raw_writeq(u64 val,volatile void __iomem * addr)47 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
48 {
49 log_write_mmio(val, 64, addr);
50 asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
51 }
52
53 #define __raw_readb __raw_readb
__raw_readb(const volatile void __iomem * addr)54 static inline u8 __raw_readb(const volatile void __iomem *addr)
55 {
56 u8 val;
57
58 log_read_mmio(8, addr);
59 asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
60 "ldarb %w0, [%1]",
61 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
62 : "=r" (val) : "r" (addr));
63 log_post_read_mmio(val, 8, addr);
64 return val;
65 }
66
67 #define __raw_readw __raw_readw
__raw_readw(const volatile void __iomem * addr)68 static inline u16 __raw_readw(const volatile void __iomem *addr)
69 {
70 u16 val;
71
72 log_read_mmio(16, addr);
73 asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
74 "ldarh %w0, [%1]",
75 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
76 : "=r" (val) : "r" (addr));
77 log_post_read_mmio(val, 16, addr);
78 return val;
79 }
80
81 #define __raw_readl __raw_readl
__raw_readl(const volatile void __iomem * addr)82 static __always_inline u32 __raw_readl(const volatile void __iomem *addr)
83 {
84 u32 val;
85
86 log_read_mmio(32, addr);
87 asm volatile(ALTERNATIVE("ldr %w0, [%1]",
88 "ldar %w0, [%1]",
89 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
90 : "=r" (val) : "r" (addr));
91 log_post_read_mmio(val, 32, addr);
92 return val;
93 }
94
95 #define __raw_readq __raw_readq
__raw_readq(const volatile void __iomem * addr)96 static inline u64 __raw_readq(const volatile void __iomem *addr)
97 {
98 u64 val;
99
100 log_read_mmio(64, addr);
101 asm volatile(ALTERNATIVE("ldr %0, [%1]",
102 "ldar %0, [%1]",
103 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
104 : "=r" (val) : "r" (addr));
105 log_post_read_mmio(val, 64, addr);
106 return val;
107 }
108
109 /* IO barriers */
110 #define __iormb(v) \
111 ({ \
112 unsigned long tmp; \
113 \
114 dma_rmb(); \
115 \
116 /* \
117 * Create a dummy control dependency from the IO read to any \
118 * later instructions. This ensures that a subsequent call to \
119 * udelay() will be ordered due to the ISB in get_cycles(). \
120 */ \
121 asm volatile("eor %0, %1, %1\n" \
122 "cbnz %0, ." \
123 : "=r" (tmp) : "r" ((unsigned long)(v)) \
124 : "memory"); \
125 })
126
127 #define __io_par(v) __iormb(v)
128 #define __iowmb() dma_wmb()
129 #define __iomb() dma_mb()
130
131 /*
132 * Relaxed I/O memory access primitives. These follow the Device memory
133 * ordering rules but do not guarantee any ordering relative to Normal memory
134 * accesses.
135 */
136 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
137 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
138 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
139 #define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
140
141 #define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
142 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
143 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
144 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
145
146 /*
147 * I/O memory access primitives. Reads are ordered relative to any
148 * following Normal memory access. Writes are ordered relative to any prior
149 * Normal memory access.
150 */
151 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; })
152 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
153 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
154 #define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })
155
156 #define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
157 #define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
158 #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
159 #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
160
161 /*
162 * I/O port access primitives.
163 */
164 #define arch_has_dev_port() (1)
165 #define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
166 #define PCI_IOBASE ((void __iomem *)PCI_IO_START)
167
168 /*
169 * String version of I/O memory access operations.
170 */
171 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
172 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
173 extern void __memset_io(volatile void __iomem *, int, size_t);
174
175 #define memset_io(c,v,l) __memset_io((c),(v),(l))
176 #define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l))
177 #define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l))
178
179 /*
180 * I/O memory mapping functions.
181 */
182 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
183 extern void iounmap(volatile void __iomem *addr);
184 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
185
186 #define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
187 #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
188
189 /*
190 * PCI configuration space mapping function.
191 *
192 * The PCI specification disallows posted write configuration transactions.
193 * Add an arch specific pci_remap_cfgspace() definition that is implemented
194 * through nGnRnE device memory attribute as recommended by the ARM v8
195 * Architecture reference manual Issue A.k B2.8.2 "Device memory".
196 */
197 #define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))
198
199 /*
200 * io{read,write}{16,32,64}be() macros
201 */
202 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
203 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
204 #define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })
205
206 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
207 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
208 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
209
210 #include <asm-generic/io.h>
211
212 /*
213 * More restrictive address range checking than the default implementation
214 * (PHYS_OFFSET and PHYS_MASK taken into account).
215 */
216 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
217 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
218 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
219
220 extern int devmem_is_allowed(unsigned long pfn);
221
222 extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
223 unsigned long flags);
224 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
225
226 #endif /* __ASM_IO_H */
227