1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level CPU initialisation 4 * Based on arch/arm/kernel/head.S 5 * 6 * Copyright (C) 1994-2002 Russell King 7 * Copyright (C) 2003-2012 ARM Ltd. 8 * Authors: Catalin Marinas <catalin.marinas@arm.com> 9 * Will Deacon <will.deacon@arm.com> 10 */ 11 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/pgtable.h> 15 16#include <asm/asm_pointer_auth.h> 17#include <asm/assembler.h> 18#include <asm/boot.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/cache.h> 22#include <asm/cputype.h> 23#include <asm/el2_setup.h> 24#include <asm/elf.h> 25#include <asm/image.h> 26#include <asm/kernel-pgtable.h> 27#include <asm/kvm_arm.h> 28#include <asm/memory.h> 29#include <asm/pgtable-hwdef.h> 30#include <asm/page.h> 31#include <asm/scs.h> 32#include <asm/smp.h> 33#include <asm/sysreg.h> 34#include <asm/thread_info.h> 35#include <asm/virt.h> 36 37#include "efi-header.S" 38 39#define __PHYS_OFFSET KERNEL_START 40 41#if (PAGE_OFFSET & 0x1fffff) != 0 42#error PAGE_OFFSET must be at least 2MB aligned 43#endif 44 45/* 46 * Kernel startup entry point. 47 * --------------------------- 48 * 49 * The requirements are: 50 * MMU = off, D-cache = off, I-cache = on or off, 51 * x0 = physical address to the FDT blob. 52 * 53 * This code is mostly position independent so you call this at 54 * __pa(PAGE_OFFSET). 55 * 56 * Note that the callee-saved registers are used for storing variables 57 * that are useful before the MMU is enabled. The allocations are described 58 * in the entry routines. 59 */ 60 __HEAD 61_head: 62 /* 63 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 64 */ 65#ifdef CONFIG_EFI 66 /* 67 * This add instruction has no meaningful effect except that 68 * its opcode forms the magic "MZ" signature required by UEFI. 69 */ 70 add x13, x18, #0x16 71 b primary_entry 72#else 73 b primary_entry // branch to kernel start, magic 74 .long 0 // reserved 75#endif 76 .quad 0 // Image load offset from start of RAM, little-endian 77 le64sym _kernel_size_le // Effective size of kernel image, little-endian 78 le64sym _kernel_flags_le // Informative flags, little-endian 79 .quad 0 // reserved 80 .quad 0 // reserved 81 .quad 0 // reserved 82 .ascii ARM64_IMAGE_MAGIC // Magic number 83#ifdef CONFIG_EFI 84 .long pe_header - _head // Offset to the PE header. 85 86pe_header: 87 __EFI_PE_HEADER 88#else 89 .long 0 // reserved 90#endif 91 92 __INIT 93 94 /* 95 * The following callee saved general purpose registers are used on the 96 * primary lowlevel boot path: 97 * 98 * Register Scope Purpose 99 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0 100 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset 101 * x28 __create_page_tables() callee preserved temp register 102 * x19/x20 __primary_switch() callee preserved temp registers 103 * x24 __primary_switch() .. relocate_kernel() current RELR displacement 104 */ 105SYM_CODE_START(primary_entry) 106 bl preserve_boot_args 107 bl init_kernel_el // w0=cpu_boot_mode 108 adrp x23, __PHYS_OFFSET 109 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 110 bl set_cpu_boot_mode_flag 111 bl __create_page_tables 112 /* 113 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 114 * details. 115 * On return, the CPU will be ready for the MMU to be turned on and 116 * the TCR will have been set. 117 */ 118 bl __cpu_setup // initialise processor 119 b __primary_switch 120SYM_CODE_END(primary_entry) 121 122/* 123 * Preserve the arguments passed by the bootloader in x0 .. x3 124 */ 125SYM_CODE_START_LOCAL(preserve_boot_args) 126 mov x21, x0 // x21=FDT 127 128 adr_l x0, boot_args // record the contents of 129 stp x21, x1, [x0] // x0 .. x3 at kernel entry 130 stp x2, x3, [x0, #16] 131 132 dmb sy // needed before dc ivac with 133 // MMU off 134 135 mov x1, #0x20 // 4 x 8 bytes 136 b __inval_dcache_area // tail call 137SYM_CODE_END(preserve_boot_args) 138 139/* 140 * Macro to create a table entry to the next page. 141 * 142 * tbl: page table address 143 * virt: virtual address 144 * shift: #imm page table shift 145 * ptrs: #imm pointers per table page 146 * 147 * Preserves: virt 148 * Corrupts: ptrs, tmp1, tmp2 149 * Returns: tbl -> next level table page address 150 */ 151 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 152 add \tmp1, \tbl, #PAGE_SIZE 153 phys_to_pte \tmp2, \tmp1 154 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 155 lsr \tmp1, \virt, #\shift 156 sub \ptrs, \ptrs, #1 157 and \tmp1, \tmp1, \ptrs // table index 158 str \tmp2, [\tbl, \tmp1, lsl #3] 159 add \tbl, \tbl, #PAGE_SIZE // next level table page 160 .endm 161 162/* 163 * Macro to populate page table entries, these entries can be pointers to the next level 164 * or last level entries pointing to physical memory. 165 * 166 * tbl: page table address 167 * rtbl: pointer to page table or physical memory 168 * index: start index to write 169 * eindex: end index to write - [index, eindex] written to 170 * flags: flags for pagetable entry to or in 171 * inc: increment to rtbl between each entry 172 * tmp1: temporary variable 173 * 174 * Preserves: tbl, eindex, flags, inc 175 * Corrupts: index, tmp1 176 * Returns: rtbl 177 */ 178 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 179.Lpe\@: phys_to_pte \tmp1, \rtbl 180 orr \tmp1, \tmp1, \flags // tmp1 = table entry 181 str \tmp1, [\tbl, \index, lsl #3] 182 add \rtbl, \rtbl, \inc // rtbl = pa next level 183 add \index, \index, #1 184 cmp \index, \eindex 185 b.ls .Lpe\@ 186 .endm 187 188/* 189 * Compute indices of table entries from virtual address range. If multiple entries 190 * were needed in the previous page table level then the next page table level is assumed 191 * to be composed of multiple pages. (This effectively scales the end index). 192 * 193 * vstart: virtual address of start of range 194 * vend: virtual address of end of range - we map [vstart, vend] 195 * shift: shift used to transform virtual address into index 196 * ptrs: number of entries in page table 197 * istart: index in table corresponding to vstart 198 * iend: index in table corresponding to vend 199 * count: On entry: how many extra entries were required in previous level, scales 200 * our end index. 201 * On exit: returns how many extra entries required for next page table level 202 * 203 * Preserves: vstart, vend, shift, ptrs 204 * Returns: istart, iend, count 205 */ 206 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count 207 lsr \iend, \vend, \shift 208 mov \istart, \ptrs 209 sub \istart, \istart, #1 210 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) 211 mov \istart, \ptrs 212 mul \istart, \istart, \count 213 add \iend, \iend, \istart // iend += (count - 1) * ptrs 214 // our entries span multiple tables 215 216 lsr \istart, \vstart, \shift 217 mov \count, \ptrs 218 sub \count, \count, #1 219 and \istart, \istart, \count 220 221 sub \count, \iend, \istart 222 .endm 223 224/* 225 * Map memory for specified virtual address range. Each level of page table needed supports 226 * multiple entries. If a level requires n entries the next page table level is assumed to be 227 * formed from n pages. 228 * 229 * tbl: location of page table 230 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 231 * vstart: virtual address of start of range 232 * vend: virtual address of end of range - we map [vstart, vend - 1] 233 * flags: flags to use to map last level entries 234 * phys: physical address corresponding to vstart - physical memory is contiguous 235 * pgds: the number of pgd entries 236 * 237 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 238 * Preserves: vstart, flags 239 * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv 240 */ 241 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv 242 sub \vend, \vend, #1 243 add \rtbl, \tbl, #PAGE_SIZE 244 mov \sv, \rtbl 245 mov \count, #0 246 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count 247 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 248 mov \tbl, \sv 249 mov \sv, \rtbl 250 251#if SWAPPER_PGTABLE_LEVELS > 3 252 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count 253 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 254 mov \tbl, \sv 255 mov \sv, \rtbl 256#endif 257 258#if SWAPPER_PGTABLE_LEVELS > 2 259 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count 260 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 261 mov \tbl, \sv 262#endif 263 264 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count 265 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 266 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 267 .endm 268 269/* 270 * Setup the initial page tables. We only setup the barest amount which is 271 * required to get the kernel running. The following sections are required: 272 * - identity mapping to enable the MMU (low address, TTBR0) 273 * - first few MB of the kernel linear mapping to jump to once the MMU has 274 * been enabled 275 */ 276SYM_FUNC_START_LOCAL(__create_page_tables) 277 mov x28, lr 278 279 /* 280 * Invalidate the init page tables to avoid potential dirty cache lines 281 * being evicted. Other page tables are allocated in rodata as part of 282 * the kernel image, and thus are clean to the PoC per the boot 283 * protocol. 284 */ 285 adrp x0, init_pg_dir 286 adrp x1, init_pg_end 287 sub x1, x1, x0 288 bl __inval_dcache_area 289 290 /* 291 * Clear the init page tables. 292 */ 293 adrp x0, init_pg_dir 294 adrp x1, init_pg_end 295 sub x1, x1, x0 2961: stp xzr, xzr, [x0], #16 297 stp xzr, xzr, [x0], #16 298 stp xzr, xzr, [x0], #16 299 stp xzr, xzr, [x0], #16 300 subs x1, x1, #64 301 b.ne 1b 302 303 mov x7, SWAPPER_MM_MMUFLAGS 304 305 /* 306 * Create the identity mapping. 307 */ 308 adrp x0, idmap_pg_dir 309 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 310 311#ifdef CONFIG_ARM64_VA_BITS_52 312 mrs_s x6, SYS_ID_AA64MMFR2_EL1 313 and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 314 mov x5, #52 315 cbnz x6, 1f 316#endif 317 mov x5, #VA_BITS_MIN 3181: 319 adr_l x6, vabits_actual 320 str x5, [x6] 321 dmb sy 322 dc ivac, x6 // Invalidate potentially stale cache line 323 324 /* 325 * VA_BITS may be too small to allow for an ID mapping to be created 326 * that covers system RAM if that is located sufficiently high in the 327 * physical address space. So for the ID map, use an extended virtual 328 * range in that case, and configure an additional translation level 329 * if needed. 330 * 331 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 332 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 333 * this number conveniently equals the number of leading zeroes in 334 * the physical address of __idmap_text_end. 335 */ 336 adrp x5, __idmap_text_end 337 clz x5, x5 338 cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough? 339 b.ge 1f // .. then skip VA range extension 340 341 adr_l x6, idmap_t0sz 342 str x5, [x6] 343 dmb sy 344 dc ivac, x6 // Invalidate potentially stale cache line 345 346#if (VA_BITS < 48) 347#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 348#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) 349 350 /* 351 * If VA_BITS < 48, we have to configure an additional table level. 352 * First, we have to verify our assumption that the current value of 353 * VA_BITS was chosen such that all translation levels are fully 354 * utilised, and that lowering T0SZ will always result in an additional 355 * translation level to be configured. 356 */ 357#if VA_BITS != EXTRA_SHIFT 358#error "Mismatch between VA_BITS and page size/number of translation levels" 359#endif 360 361 mov x4, EXTRA_PTRS 362 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 363#else 364 /* 365 * If VA_BITS == 48, we don't have to configure an additional 366 * translation level, but the top-level table has more entries. 367 */ 368 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) 369 str_l x4, idmap_ptrs_per_pgd, x5 370#endif 3711: 372 ldr_l x4, idmap_ptrs_per_pgd 373 mov x5, x3 // __pa(__idmap_text_start) 374 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 375 376 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 377 378 /* 379 * Map the kernel image (starting with PHYS_OFFSET). 380 */ 381 adrp x0, init_pg_dir 382 mov_q x5, KIMAGE_VADDR // compile time __va(_text) 383 add x5, x5, x23 // add KASLR displacement 384 mov x4, PTRS_PER_PGD 385 adrp x6, _end // runtime __pa(_end) 386 adrp x3, _text // runtime __pa(_text) 387 sub x6, x6, x3 // _end - _text 388 add x6, x6, x5 // runtime __va(_end) 389 390 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14 391 392 /* 393 * Since the page tables have been populated with non-cacheable 394 * accesses (MMU disabled), invalidate those tables again to 395 * remove any speculatively loaded cache lines. 396 */ 397 dmb sy 398 399 adrp x0, idmap_pg_dir 400 adrp x1, idmap_pg_end 401 sub x1, x1, x0 402 bl __inval_dcache_area 403 404 adrp x0, init_pg_dir 405 adrp x1, init_pg_end 406 sub x1, x1, x0 407 bl __inval_dcache_area 408 409 ret x28 410SYM_FUNC_END(__create_page_tables) 411 412/* 413 * The following fragment of code is executed with the MMU enabled. 414 * 415 * x0 = __PHYS_OFFSET 416 */ 417SYM_FUNC_START_LOCAL(__primary_switched) 418 adrp x4, init_thread_union 419 add sp, x4, #THREAD_SIZE 420 adr_l x5, init_task 421 msr sp_el0, x5 // Save thread_info 422 423 adr_l x8, vectors // load VBAR_EL1 with virtual 424 msr vbar_el1, x8 // vector table address 425 isb 426 427 stp xzr, x30, [sp, #-16]! 428 mov x29, sp 429 430#ifdef CONFIG_SHADOW_CALL_STACK 431 adr_l scs_sp, init_shadow_call_stack // Set shadow call stack 432#endif 433 434 str_l x21, __fdt_pointer, x5 // Save FDT pointer 435 436 ldr_l x4, kimage_vaddr // Save the offset between 437 sub x4, x4, x0 // the kernel virtual and 438 str_l x4, kimage_voffset, x5 // physical mappings 439 440 // Clear BSS 441 adr_l x0, __bss_start 442 mov x1, xzr 443 adr_l x2, __bss_stop 444 sub x2, x2, x0 445 bl __pi_memset 446 dsb ishst // Make zero page visible to PTW 447 448#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 449 bl kasan_early_init 450#endif 451 mov x0, x21 // pass FDT address in x0 452 bl early_fdt_map // Try mapping the FDT early 453 bl init_feature_override // Parse cpu feature overrides 454#ifdef CONFIG_RANDOMIZE_BASE 455 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 456 b.ne 0f 457 bl kaslr_early_init // parse FDT for KASLR options 458 cbz x0, 0f // KASLR disabled? just proceed 459 orr x23, x23, x0 // record KASLR offset 460 ldp x29, x30, [sp], #16 // we must enable KASLR, return 461 ret // to __primary_switch() 4620: 463#endif 464 bl switch_to_vhe // Prefer VHE if possible 465 add sp, sp, #16 466 mov x29, #0 467 mov x30, #0 468 b start_kernel 469SYM_FUNC_END(__primary_switched) 470 471 .pushsection ".rodata", "a" 472SYM_DATA_START(kimage_vaddr) 473 .quad _text 474SYM_DATA_END(kimage_vaddr) 475EXPORT_SYMBOL(kimage_vaddr) 476 .popsection 477 478/* 479 * end early head section, begin head code that is also used for 480 * hotplug and needs to have the same protections as the text region 481 */ 482 .section ".idmap.text","awx" 483 484/* 485 * Starting from EL2 or EL1, configure the CPU to execute at the highest 486 * reachable EL supported by the kernel in a chosen default state. If dropping 487 * from EL2 to EL1, configure EL2 before configuring EL1. 488 * 489 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if 490 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET. 491 * 492 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 493 * booted in EL1 or EL2 respectively. 494 */ 495SYM_FUNC_START(init_kernel_el) 496 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 497 msr sctlr_el1, x0 498 499 mrs x0, CurrentEL 500 cmp x0, #CurrentEL_EL2 501 b.eq init_el2 502 503SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) 504 isb 505 mov_q x0, INIT_PSTATE_EL1 506 msr spsr_el1, x0 507 msr elr_el1, lr 508 mov w0, #BOOT_CPU_MODE_EL1 509 eret 510 511SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) 512 mov_q x0, HCR_HOST_NVHE_FLAGS 513 msr hcr_el2, x0 514 isb 515 516 init_el2_state 517 518 /* Hypervisor stub */ 519 adr_l x0, __hyp_stub_vectors 520 msr vbar_el2, x0 521 isb 522 523 msr elr_el2, lr 524 mov w0, #BOOT_CPU_MODE_EL2 525 eret 526SYM_FUNC_END(init_kernel_el) 527 528/* 529 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 530 * in w0. See arch/arm64/include/asm/virt.h for more info. 531 */ 532SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag) 533 adr_l x1, __boot_cpu_mode 534 cmp w0, #BOOT_CPU_MODE_EL2 535 b.ne 1f 536 add x1, x1, #4 5371: str w0, [x1] // This CPU has booted in EL1 538 dmb sy 539 dc ivac, x1 // Invalidate potentially stale cache line 540 ret 541SYM_FUNC_END(set_cpu_boot_mode_flag) 542 543/* 544 * These values are written with the MMU off, but read with the MMU on. 545 * Writers will invalidate the corresponding address, discarding up to a 546 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 547 * sufficient alignment that the CWG doesn't overlap another section. 548 */ 549 .pushsection ".mmuoff.data.write", "aw" 550/* 551 * We need to find out the CPU boot mode long after boot, so we need to 552 * store it in a writable variable. 553 * 554 * This is not in .bss, because we set it sufficiently early that the boot-time 555 * zeroing of .bss would clobber it. 556 */ 557SYM_DATA_START(__boot_cpu_mode) 558 .long BOOT_CPU_MODE_EL2 559 .long BOOT_CPU_MODE_EL1 560SYM_DATA_END(__boot_cpu_mode) 561/* 562 * The booting CPU updates the failed status @__early_cpu_boot_status, 563 * with MMU turned off. 564 */ 565SYM_DATA_START(__early_cpu_boot_status) 566 .quad 0 567SYM_DATA_END(__early_cpu_boot_status) 568 569 .popsection 570 571 /* 572 * This provides a "holding pen" for platforms to hold all secondary 573 * cores are held until we're ready for them to initialise. 574 */ 575SYM_FUNC_START(secondary_holding_pen) 576 bl init_kernel_el // w0=cpu_boot_mode 577 bl set_cpu_boot_mode_flag 578 mrs x0, mpidr_el1 579 mov_q x1, MPIDR_HWID_BITMASK 580 and x0, x0, x1 581 adr_l x3, secondary_holding_pen_release 582pen: ldr x4, [x3] 583 cmp x4, x0 584 b.eq secondary_startup 585 wfe 586 b pen 587SYM_FUNC_END(secondary_holding_pen) 588 589 /* 590 * Secondary entry point that jumps straight into the kernel. Only to 591 * be used where CPUs are brought online dynamically by the kernel. 592 */ 593SYM_FUNC_START(secondary_entry) 594 bl init_kernel_el // w0=cpu_boot_mode 595 bl set_cpu_boot_mode_flag 596 b secondary_startup 597SYM_FUNC_END(secondary_entry) 598 599SYM_FUNC_START_LOCAL(secondary_startup) 600 /* 601 * Common entry point for secondary CPUs. 602 */ 603 bl switch_to_vhe 604 bl __cpu_secondary_check52bitva 605 bl __cpu_setup // initialise processor 606 adrp x1, swapper_pg_dir 607 bl __enable_mmu 608 ldr x8, =__secondary_switched 609 br x8 610SYM_FUNC_END(secondary_startup) 611 612SYM_FUNC_START_LOCAL(__secondary_switched) 613 adr_l x5, vectors 614 msr vbar_el1, x5 615 isb 616 617 adr_l x0, secondary_data 618 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 619 cbz x1, __secondary_too_slow 620 mov sp, x1 621 ldr x2, [x0, #CPU_BOOT_TASK] 622 cbz x2, __secondary_too_slow 623 msr sp_el0, x2 624 scs_load_current 625 mov x29, #0 626 mov x30, #0 627 628#ifdef CONFIG_ARM64_PTR_AUTH 629 ptrauth_keys_init_cpu x2, x3, x4, x5 630#endif 631 632 b secondary_start_kernel 633SYM_FUNC_END(__secondary_switched) 634 635SYM_FUNC_START_LOCAL(__secondary_too_slow) 636 wfe 637 wfi 638 b __secondary_too_slow 639SYM_FUNC_END(__secondary_too_slow) 640 641/* 642 * The booting CPU updates the failed status @__early_cpu_boot_status, 643 * with MMU turned off. 644 * 645 * update_early_cpu_boot_status tmp, status 646 * - Corrupts tmp1, tmp2 647 * - Writes 'status' to __early_cpu_boot_status and makes sure 648 * it is committed to memory. 649 */ 650 651 .macro update_early_cpu_boot_status status, tmp1, tmp2 652 mov \tmp2, #\status 653 adr_l \tmp1, __early_cpu_boot_status 654 str \tmp2, [\tmp1] 655 dmb sy 656 dc ivac, \tmp1 // Invalidate potentially stale cache line 657 .endm 658 659/* 660 * Enable the MMU. 661 * 662 * x0 = SCTLR_EL1 value for turning on the MMU. 663 * x1 = TTBR1_EL1 value 664 * 665 * Returns to the caller via x30/lr. This requires the caller to be covered 666 * by the .idmap.text section. 667 * 668 * Checks if the selected granule size is supported by the CPU. 669 * If it isn't, park the CPU 670 */ 671SYM_FUNC_START(__enable_mmu) 672 mrs x2, ID_AA64MMFR0_EL1 673 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 674 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN 675 b.lt __no_granule_support 676 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 677 b.gt __no_granule_support 678 update_early_cpu_boot_status 0, x2, x3 679 adrp x2, idmap_pg_dir 680 phys_to_ttbr x1, x1 681 phys_to_ttbr x2, x2 682 msr ttbr0_el1, x2 // load TTBR0 683 offset_ttbr1 x1, x3 684 msr ttbr1_el1, x1 // load TTBR1 685 isb 686 687 set_sctlr_el1 x0 688 689 ret 690SYM_FUNC_END(__enable_mmu) 691 692SYM_FUNC_START(__cpu_secondary_check52bitva) 693#ifdef CONFIG_ARM64_VA_BITS_52 694 ldr_l x0, vabits_actual 695 cmp x0, #52 696 b.ne 2f 697 698 mrs_s x0, SYS_ID_AA64MMFR2_EL1 699 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 700 cbnz x0, 2f 701 702 update_early_cpu_boot_status \ 703 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 7041: wfe 705 wfi 706 b 1b 707 708#endif 7092: ret 710SYM_FUNC_END(__cpu_secondary_check52bitva) 711 712SYM_FUNC_START_LOCAL(__no_granule_support) 713 /* Indicate that this CPU can't boot and is stuck in the kernel */ 714 update_early_cpu_boot_status \ 715 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 7161: 717 wfe 718 wfi 719 b 1b 720SYM_FUNC_END(__no_granule_support) 721 722#ifdef CONFIG_RELOCATABLE 723SYM_FUNC_START_LOCAL(__relocate_kernel) 724 /* 725 * Iterate over each entry in the relocation table, and apply the 726 * relocations in place. 727 */ 728 ldr w9, =__rela_offset // offset to reloc table 729 ldr w10, =__rela_size // size of reloc table 730 731 mov_q x11, KIMAGE_VADDR // default virtual offset 732 add x11, x11, x23 // actual virtual offset 733 add x9, x9, x11 // __va(.rela) 734 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 735 7360: cmp x9, x10 737 b.hs 1f 738 ldp x12, x13, [x9], #24 739 ldr x14, [x9, #-8] 740 cmp w13, #R_AARCH64_RELATIVE 741 b.ne 0b 742 add x14, x14, x23 // relocate 743 str x14, [x12, x23] 744 b 0b 745 7461: 747#ifdef CONFIG_RELR 748 /* 749 * Apply RELR relocations. 750 * 751 * RELR is a compressed format for storing relative relocations. The 752 * encoded sequence of entries looks like: 753 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] 754 * 755 * i.e. start with an address, followed by any number of bitmaps. The 756 * address entry encodes 1 relocation. The subsequent bitmap entries 757 * encode up to 63 relocations each, at subsequent offsets following 758 * the last address entry. 759 * 760 * The bitmap entries must have 1 in the least significant bit. The 761 * assumption here is that an address cannot have 1 in lsb. Odd 762 * addresses are not supported. Any odd addresses are stored in the RELA 763 * section, which is handled above. 764 * 765 * Excluding the least significant bit in the bitmap, each non-zero 766 * bit in the bitmap represents a relocation to be applied to 767 * a corresponding machine word that follows the base address 768 * word. The second least significant bit represents the machine 769 * word immediately following the initial address, and each bit 770 * that follows represents the next word, in linear order. As such, 771 * a single bitmap can encode up to 63 relocations in a 64-bit object. 772 * 773 * In this implementation we store the address of the next RELR table 774 * entry in x9, the address being relocated by the current address or 775 * bitmap entry in x13 and the address being relocated by the current 776 * bit in x14. 777 * 778 * Because addends are stored in place in the binary, RELR relocations 779 * cannot be applied idempotently. We use x24 to keep track of the 780 * currently applied displacement so that we can correctly relocate if 781 * __relocate_kernel is called twice with non-zero displacements (i.e. 782 * if there is both a physical misalignment and a KASLR displacement). 783 */ 784 ldr w9, =__relr_offset // offset to reloc table 785 ldr w10, =__relr_size // size of reloc table 786 add x9, x9, x11 // __va(.relr) 787 add x10, x9, x10 // __va(.relr) + sizeof(.relr) 788 789 sub x15, x23, x24 // delta from previous offset 790 cbz x15, 7f // nothing to do if unchanged 791 mov x24, x23 // save new offset 792 7932: cmp x9, x10 794 b.hs 7f 795 ldr x11, [x9], #8 796 tbnz x11, #0, 3f // branch to handle bitmaps 797 add x13, x11, x23 798 ldr x12, [x13] // relocate address entry 799 add x12, x12, x15 800 str x12, [x13], #8 // adjust to start of bitmap 801 b 2b 802 8033: mov x14, x13 8044: lsr x11, x11, #1 805 cbz x11, 6f 806 tbz x11, #0, 5f // skip bit if not set 807 ldr x12, [x14] // relocate bit 808 add x12, x12, x15 809 str x12, [x14] 810 8115: add x14, x14, #8 // move to next bit's address 812 b 4b 813 8146: /* 815 * Move to the next bitmap's address. 8 is the word size, and 63 is the 816 * number of significant bits in a bitmap entry. 817 */ 818 add x13, x13, #(8 * 63) 819 b 2b 820 8217: 822#endif 823 ret 824 825SYM_FUNC_END(__relocate_kernel) 826#endif 827 828SYM_FUNC_START_LOCAL(__primary_switch) 829#ifdef CONFIG_RANDOMIZE_BASE 830 mov x19, x0 // preserve new SCTLR_EL1 value 831 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 832#endif 833 834 adrp x1, init_pg_dir 835 bl __enable_mmu 836#ifdef CONFIG_RELOCATABLE 837#ifdef CONFIG_RELR 838 mov x24, #0 // no RELR displacement yet 839#endif 840 bl __relocate_kernel 841#ifdef CONFIG_RANDOMIZE_BASE 842 ldr x8, =__primary_switched 843 adrp x0, __PHYS_OFFSET 844 blr x8 845 846 /* 847 * If we return here, we have a KASLR displacement in x23 which we need 848 * to take into account by discarding the current kernel mapping and 849 * creating a new one. 850 */ 851 pre_disable_mmu_workaround 852 msr sctlr_el1, x20 // disable the MMU 853 isb 854 bl __create_page_tables // recreate kernel mapping 855 856 tlbi vmalle1 // Remove any stale TLB entries 857 dsb nsh 858 isb 859 860 set_sctlr_el1 x19 // re-enable the MMU 861 862 bl __relocate_kernel 863#endif 864#endif 865 ldr x8, =__primary_switched 866 adrp x0, __PHYS_OFFSET 867 br x8 868SYM_FUNC_END(__primary_switch) 869