1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <hyp/adjust_pc.h>
8 #include <hyp/switch.h>
9 #include <hyp/sysreg-sr.h>
10
11 #include <linux/arm-smccc.h>
12 #include <linux/kvm_host.h>
13 #include <linux/types.h>
14 #include <linux/jump_label.h>
15 #include <uapi/linux/psci.h>
16
17 #include <kvm/arm_psci.h>
18
19 #include <asm/barrier.h>
20 #include <asm/cpufeature.h>
21 #include <asm/kprobes.h>
22 #include <asm/kvm_asm.h>
23 #include <asm/kvm_emulate.h>
24 #include <asm/kvm_hyp.h>
25 #include <asm/kvm_mmu.h>
26 #include <asm/fpsimd.h>
27 #include <asm/debug-monitors.h>
28 #include <asm/processor.h>
29 #include <asm/thread_info.h>
30
31 #include <nvhe/mem_protect.h>
32
33 /* Non-VHE specific context */
34 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
35 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
36 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
37
__activate_traps(struct kvm_vcpu * vcpu)38 static void __activate_traps(struct kvm_vcpu *vcpu)
39 {
40 u64 val;
41
42 ___activate_traps(vcpu);
43 __activate_traps_common(vcpu);
44
45 val = CPTR_EL2_DEFAULT;
46 val |= CPTR_EL2_TTA | CPTR_EL2_TAM;
47 if (!update_fp_enabled(vcpu)) {
48 val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
49 __activate_traps_fpsimd32(vcpu);
50 }
51
52 write_sysreg(val, cptr_el2);
53 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);
54
55 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
56 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
57
58 isb();
59 /*
60 * At this stage, and thanks to the above isb(), S2 is
61 * configured and enabled. We can now restore the guest's S1
62 * configuration: SCTLR, and only then TCR.
63 */
64 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
65 isb();
66 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
67 }
68 }
69
__deactivate_traps(struct kvm_vcpu * vcpu)70 static void __deactivate_traps(struct kvm_vcpu *vcpu)
71 {
72 extern char __kvm_hyp_host_vector[];
73 u64 mdcr_el2, cptr;
74
75 ___deactivate_traps(vcpu);
76
77 mdcr_el2 = read_sysreg(mdcr_el2);
78
79 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
80 u64 val;
81
82 /*
83 * Set the TCR and SCTLR registers in the exact opposite
84 * sequence as __activate_traps (first prevent walks,
85 * then force the MMU on). A generous sprinkling of isb()
86 * ensure that things happen in this exact order.
87 */
88 val = read_sysreg_el1(SYS_TCR);
89 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR);
90 isb();
91 val = read_sysreg_el1(SYS_SCTLR);
92 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
93 isb();
94 }
95
96 __deactivate_traps_common();
97
98 mdcr_el2 &= MDCR_EL2_HPMN_MASK;
99 mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
100 mdcr_el2 |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;
101
102 write_sysreg(mdcr_el2, mdcr_el2);
103 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2);
104
105 cptr = CPTR_EL2_DEFAULT;
106 if (vcpu_has_sve(vcpu) && (vcpu->arch.flags & KVM_ARM64_FP_ENABLED))
107 cptr |= CPTR_EL2_TZ;
108
109 write_sysreg(cptr, cptr_el2);
110 write_sysreg(__kvm_hyp_host_vector, vbar_el2);
111 }
112
113 /* Save VGICv3 state on non-VHE systems */
__hyp_vgic_save_state(struct kvm_vcpu * vcpu)114 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
115 {
116 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
117 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3);
118 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
119 }
120 }
121
122 /* Restore VGICv3 state on non_VEH systems */
__hyp_vgic_restore_state(struct kvm_vcpu * vcpu)123 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
124 {
125 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
126 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
127 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3);
128 }
129 }
130
131 /**
132 * Disable host events, enable guest events
133 */
__pmu_switch_to_guest(struct kvm_cpu_context * host_ctxt)134 static bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
135 {
136 struct kvm_host_data *host;
137 struct kvm_pmu_events *pmu;
138
139 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
140 pmu = &host->pmu_events;
141
142 if (pmu->events_host)
143 write_sysreg(pmu->events_host, pmcntenclr_el0);
144
145 if (pmu->events_guest)
146 write_sysreg(pmu->events_guest, pmcntenset_el0);
147
148 return (pmu->events_host || pmu->events_guest);
149 }
150
151 /**
152 * Disable guest events, enable host events
153 */
__pmu_switch_to_host(struct kvm_cpu_context * host_ctxt)154 static void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
155 {
156 struct kvm_host_data *host;
157 struct kvm_pmu_events *pmu;
158
159 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
160 pmu = &host->pmu_events;
161
162 if (pmu->events_guest)
163 write_sysreg(pmu->events_guest, pmcntenclr_el0);
164
165 if (pmu->events_host)
166 write_sysreg(pmu->events_host, pmcntenset_el0);
167 }
168
169 /* Switch to the guest for legacy non-VHE systems */
__kvm_vcpu_run(struct kvm_vcpu * vcpu)170 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
171 {
172 struct kvm_cpu_context *host_ctxt;
173 struct kvm_cpu_context *guest_ctxt;
174 bool pmu_switch_needed;
175 u64 exit_code;
176
177 /*
178 * Having IRQs masked via PMR when entering the guest means the GIC
179 * will not signal the CPU of interrupts of lower priority, and the
180 * only way to get out will be via guest exceptions.
181 * Naturally, we want to avoid this.
182 */
183 if (system_uses_irq_prio_masking()) {
184 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
185 pmr_sync();
186 }
187
188 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
189 host_ctxt->__hyp_running_vcpu = vcpu;
190 guest_ctxt = &vcpu->arch.ctxt;
191
192 pmu_switch_needed = __pmu_switch_to_guest(host_ctxt);
193
194 __sysreg_save_state_nvhe(host_ctxt);
195 /*
196 * We must flush and disable the SPE buffer for nVHE, as
197 * the translation regime(EL1&0) is going to be loaded with
198 * that of the guest. And we must do this before we change the
199 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and
200 * before we load guest Stage1.
201 */
202 __debug_save_host_buffers_nvhe(vcpu);
203
204 __adjust_pc(vcpu);
205
206 /*
207 * We must restore the 32-bit state before the sysregs, thanks
208 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
209 *
210 * Also, and in order to be able to deal with erratum #1319537 (A57)
211 * and #1319367 (A72), we must ensure that all VM-related sysreg are
212 * restored before we enable S2 translation.
213 */
214 __sysreg32_restore_state(vcpu);
215 __sysreg_restore_state_nvhe(guest_ctxt);
216
217 __load_guest_stage2(kern_hyp_va(vcpu->arch.hw_mmu));
218 __activate_traps(vcpu);
219
220 __hyp_vgic_restore_state(vcpu);
221 __timer_enable_traps(vcpu);
222
223 __debug_switch_to_guest(vcpu);
224
225 do {
226 /* Jump in the fire! */
227 exit_code = __guest_enter(vcpu);
228
229 /* And we're baaack! */
230 } while (fixup_guest_exit(vcpu, &exit_code));
231
232 __sysreg_save_state_nvhe(guest_ctxt);
233 __sysreg32_save_state(vcpu);
234 __timer_disable_traps(vcpu);
235 __hyp_vgic_save_state(vcpu);
236
237 __deactivate_traps(vcpu);
238 __load_host_stage2();
239
240 __sysreg_restore_state_nvhe(host_ctxt);
241
242 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
243 __fpsimd_save_fpexc32(vcpu);
244
245 __debug_switch_to_host(vcpu);
246 /*
247 * This must come after restoring the host sysregs, since a non-VHE
248 * system may enable SPE here and make use of the TTBRs.
249 */
250 __debug_restore_host_buffers_nvhe(vcpu);
251
252 if (pmu_switch_needed)
253 __pmu_switch_to_host(host_ctxt);
254
255 /* Returning to host will clear PSR.I, remask PMR if needed */
256 if (system_uses_irq_prio_masking())
257 gic_write_pmr(GIC_PRIO_IRQOFF);
258
259 host_ctxt->__hyp_running_vcpu = NULL;
260
261 return exit_code;
262 }
263
hyp_panic(void)264 void __noreturn hyp_panic(void)
265 {
266 u64 spsr = read_sysreg_el2(SYS_SPSR);
267 u64 elr = read_sysreg_el2(SYS_ELR);
268 u64 par = read_sysreg_par();
269 struct kvm_cpu_context *host_ctxt;
270 struct kvm_vcpu *vcpu;
271
272 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
273 vcpu = host_ctxt->__hyp_running_vcpu;
274
275 if (vcpu) {
276 __timer_disable_traps(vcpu);
277 __deactivate_traps(vcpu);
278 __load_host_stage2();
279 __sysreg_restore_state_nvhe(host_ctxt);
280 }
281
282 __hyp_do_panic(host_ctxt, spsr, elr, par);
283 unreachable();
284 }
285
kvm_unexpected_el2_exception(void)286 asmlinkage void kvm_unexpected_el2_exception(void)
287 {
288 __kvm_unexpected_el2_exception();
289 }
290