1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7 #include <linux/cpu.h>
8 #include <linux/delay.h>
9 #include <linux/io.h>
10 #include <linux/sched/task_stack.h>
11 #include <linux/sched/hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/smp.h>
14 #include <linux/types.h>
15
16 #include <asm/bcache.h>
17 #include <asm/mips-cps.h>
18 #include <asm/mips_mt.h>
19 #include <asm/mipsregs.h>
20 #include <asm/pm-cps.h>
21 #include <asm/r4kcache.h>
22 #include <asm/smp-cps.h>
23 #include <asm/time.h>
24 #include <asm/uasm.h>
25
26 static bool threads_disabled;
27 static DECLARE_BITMAP(core_power, NR_CPUS);
28
29 struct core_boot_config *mips_cps_core_bootcfg;
30
setup_nothreads(char * s)31 static int __init setup_nothreads(char *s)
32 {
33 threads_disabled = true;
34 return 0;
35 }
36 early_param("nothreads", setup_nothreads);
37
core_vpe_count(unsigned int cluster,unsigned core)38 static unsigned core_vpe_count(unsigned int cluster, unsigned core)
39 {
40 if (threads_disabled)
41 return 1;
42
43 return mips_cps_numvps(cluster, core);
44 }
45
cps_smp_setup(void)46 static void __init cps_smp_setup(void)
47 {
48 unsigned int nclusters, ncores, nvpes, core_vpes;
49 unsigned long core_entry;
50 int cl, c, v;
51
52 /* Detect & record VPE topology */
53 nvpes = 0;
54 nclusters = mips_cps_numclusters();
55 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
56 for (cl = 0; cl < nclusters; cl++) {
57 if (cl > 0)
58 pr_cont(",");
59 pr_cont("{");
60
61 ncores = mips_cps_numcores(cl);
62 for (c = 0; c < ncores; c++) {
63 core_vpes = core_vpe_count(cl, c);
64
65 if (c > 0)
66 pr_cont(",");
67 pr_cont("%u", core_vpes);
68
69 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
70 if (!cl && !c)
71 smp_num_siblings = core_vpes;
72
73 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
74 cpu_set_cluster(&cpu_data[nvpes + v], cl);
75 cpu_set_core(&cpu_data[nvpes + v], c);
76 cpu_set_vpe_id(&cpu_data[nvpes + v], v);
77 }
78
79 nvpes += core_vpes;
80 }
81
82 pr_cont("}");
83 }
84 pr_cont(" total %u\n", nvpes);
85
86 /* Indicate present CPUs (CPU being synonymous with VPE) */
87 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
88 set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
89 set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
90 __cpu_number_map[v] = v;
91 __cpu_logical_map[v] = v;
92 }
93
94 /* Set a coherent default CCA (CWB) */
95 change_c0_config(CONF_CM_CMASK, 0x5);
96
97 /* Core 0 is powered up (we're running on it) */
98 bitmap_set(core_power, 0, 1);
99
100 /* Initialise core 0 */
101 mips_cps_core_init();
102
103 /* Make core 0 coherent with everything */
104 write_gcr_cl_coherence(0xff);
105
106 if (mips_cm_revision() >= CM_REV_CM3) {
107 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
108 write_gcr_bev_base(core_entry);
109 }
110
111 #ifdef CONFIG_MIPS_MT_FPAFF
112 /* If we have an FPU, enroll ourselves in the FPU-full mask */
113 if (cpu_has_fpu)
114 cpumask_set_cpu(0, &mt_fpu_cpumask);
115 #endif /* CONFIG_MIPS_MT_FPAFF */
116 }
117
cps_prepare_cpus(unsigned int max_cpus)118 static void __init cps_prepare_cpus(unsigned int max_cpus)
119 {
120 unsigned ncores, core_vpes, c, cca;
121 bool cca_unsuitable, cores_limited;
122 u32 *entry_code;
123
124 mips_mt_set_cpuoptions();
125
126 /* Detect whether the CCA is unsuited to multi-core SMP */
127 cca = read_c0_config() & CONF_CM_CMASK;
128 switch (cca) {
129 case 0x4: /* CWBE */
130 case 0x5: /* CWB */
131 /* The CCA is coherent, multi-core is fine */
132 cca_unsuitable = false;
133 break;
134
135 default:
136 /* CCA is not coherent, multi-core is not usable */
137 cca_unsuitable = true;
138 }
139
140 /* Warn the user if the CCA prevents multi-core */
141 cores_limited = false;
142 if (cca_unsuitable || cpu_has_dc_aliases) {
143 for_each_present_cpu(c) {
144 if (cpus_are_siblings(smp_processor_id(), c))
145 continue;
146
147 set_cpu_present(c, false);
148 cores_limited = true;
149 }
150 }
151 if (cores_limited)
152 pr_warn("Using only one core due to %s%s%s\n",
153 cca_unsuitable ? "unsuitable CCA" : "",
154 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
155 cpu_has_dc_aliases ? "dcache aliasing" : "");
156
157 /*
158 * Patch the start of mips_cps_core_entry to provide:
159 *
160 * s0 = kseg0 CCA
161 */
162 entry_code = (u32 *)&mips_cps_core_entry;
163 uasm_i_addiu(&entry_code, 16, 0, cca);
164 blast_dcache_range((unsigned long)&mips_cps_core_entry,
165 (unsigned long)entry_code);
166 bc_wback_inv((unsigned long)&mips_cps_core_entry,
167 (void *)entry_code - (void *)&mips_cps_core_entry);
168 __sync();
169
170 /* Allocate core boot configuration structs */
171 ncores = mips_cps_numcores(0);
172 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
173 GFP_KERNEL);
174 if (!mips_cps_core_bootcfg) {
175 pr_err("Failed to allocate boot config for %u cores\n", ncores);
176 goto err_out;
177 }
178
179 /* Allocate VPE boot configuration structs */
180 for (c = 0; c < ncores; c++) {
181 core_vpes = core_vpe_count(0, c);
182 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
183 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
184 GFP_KERNEL);
185 if (!mips_cps_core_bootcfg[c].vpe_config) {
186 pr_err("Failed to allocate %u VPE boot configs\n",
187 core_vpes);
188 goto err_out;
189 }
190 }
191
192 /* Mark this CPU as booted */
193 atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask,
194 1 << cpu_vpe_id(¤t_cpu_data));
195
196 return;
197 err_out:
198 /* Clean up allocations */
199 if (mips_cps_core_bootcfg) {
200 for (c = 0; c < ncores; c++)
201 kfree(mips_cps_core_bootcfg[c].vpe_config);
202 kfree(mips_cps_core_bootcfg);
203 mips_cps_core_bootcfg = NULL;
204 }
205
206 /* Effectively disable SMP by declaring CPUs not present */
207 for_each_possible_cpu(c) {
208 if (c == 0)
209 continue;
210 set_cpu_present(c, false);
211 }
212 }
213
boot_core(unsigned int core,unsigned int vpe_id)214 static void boot_core(unsigned int core, unsigned int vpe_id)
215 {
216 u32 stat, seq_state;
217 unsigned timeout;
218
219 /* Select the appropriate core */
220 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
221
222 /* Set its reset vector */
223 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
224
225 /* Ensure its coherency is disabled */
226 write_gcr_co_coherence(0);
227
228 /* Start it with the legacy memory map and exception base */
229 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
230
231 /* Ensure the core can access the GCRs */
232 set_gcr_access(1 << core);
233
234 if (mips_cpc_present()) {
235 /* Reset the core */
236 mips_cpc_lock_other(core);
237
238 if (mips_cm_revision() >= CM_REV_CM3) {
239 /* Run only the requested VP following the reset */
240 write_cpc_co_vp_stop(0xf);
241 write_cpc_co_vp_run(1 << vpe_id);
242
243 /*
244 * Ensure that the VP_RUN register is written before the
245 * core leaves reset.
246 */
247 wmb();
248 }
249
250 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
251
252 timeout = 100;
253 while (true) {
254 stat = read_cpc_co_stat_conf();
255 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
256 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
257
258 /* U6 == coherent execution, ie. the core is up */
259 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
260 break;
261
262 /* Delay a little while before we start warning */
263 if (timeout) {
264 timeout--;
265 mdelay(10);
266 continue;
267 }
268
269 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
270 core, stat);
271 mdelay(1000);
272 }
273
274 mips_cpc_unlock_other();
275 } else {
276 /* Take the core out of reset */
277 write_gcr_co_reset_release(0);
278 }
279
280 mips_cm_unlock_other();
281
282 /* The core is now powered up */
283 bitmap_set(core_power, core, 1);
284 }
285
remote_vpe_boot(void * dummy)286 static void remote_vpe_boot(void *dummy)
287 {
288 unsigned core = cpu_core(¤t_cpu_data);
289 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
290
291 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
292 }
293
cps_boot_secondary(int cpu,struct task_struct * idle)294 static int cps_boot_secondary(int cpu, struct task_struct *idle)
295 {
296 unsigned core = cpu_core(&cpu_data[cpu]);
297 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
298 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
299 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
300 unsigned long core_entry;
301 unsigned int remote;
302 int err;
303
304 /* We don't yet support booting CPUs in other clusters */
305 if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
306 return -ENOSYS;
307
308 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
309 vpe_cfg->sp = __KSTK_TOS(idle);
310 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
311
312 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
313
314 preempt_disable();
315
316 if (!test_bit(core, core_power)) {
317 /* Boot a VPE on a powered down core */
318 boot_core(core, vpe_id);
319 goto out;
320 }
321
322 if (cpu_has_vp) {
323 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
324 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
325 write_gcr_co_reset_base(core_entry);
326 mips_cm_unlock_other();
327 }
328
329 if (!cpus_are_siblings(cpu, smp_processor_id())) {
330 /* Boot a VPE on another powered up core */
331 for (remote = 0; remote < NR_CPUS; remote++) {
332 if (!cpus_are_siblings(cpu, remote))
333 continue;
334 if (cpu_online(remote))
335 break;
336 }
337 if (remote >= NR_CPUS) {
338 pr_crit("No online CPU in core %u to start CPU%d\n",
339 core, cpu);
340 goto out;
341 }
342
343 err = smp_call_function_single(remote, remote_vpe_boot,
344 NULL, 1);
345 if (err)
346 panic("Failed to call remote CPU\n");
347 goto out;
348 }
349
350 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
351
352 /* Boot a VPE on this core */
353 mips_cps_boot_vpes(core_cfg, vpe_id);
354 out:
355 preempt_enable();
356 return 0;
357 }
358
cps_init_secondary(void)359 static void cps_init_secondary(void)
360 {
361 /* Disable MT - we only want to run 1 TC per VPE */
362 if (cpu_has_mipsmt)
363 dmt();
364
365 if (mips_cm_revision() >= CM_REV_CM3) {
366 unsigned int ident = read_gic_vl_ident();
367
368 /*
369 * Ensure that our calculation of the VP ID matches up with
370 * what the GIC reports, otherwise we'll have configured
371 * interrupts incorrectly.
372 */
373 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
374 }
375
376 if (cpu_has_veic)
377 clear_c0_status(ST0_IM);
378 else
379 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
380 STATUSF_IP4 | STATUSF_IP5 |
381 STATUSF_IP6 | STATUSF_IP7);
382 }
383
cps_smp_finish(void)384 static void cps_smp_finish(void)
385 {
386 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
387
388 #ifdef CONFIG_MIPS_MT_FPAFF
389 /* If we have an FPU, enroll ourselves in the FPU-full mask */
390 if (cpu_has_fpu)
391 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
392 #endif /* CONFIG_MIPS_MT_FPAFF */
393
394 local_irq_enable();
395 }
396
397 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
398
399 enum cpu_death {
400 CPU_DEATH_HALT,
401 CPU_DEATH_POWER,
402 };
403
cps_shutdown_this_cpu(enum cpu_death death)404 static void cps_shutdown_this_cpu(enum cpu_death death)
405 {
406 unsigned int cpu, core, vpe_id;
407
408 cpu = smp_processor_id();
409 core = cpu_core(&cpu_data[cpu]);
410
411 if (death == CPU_DEATH_HALT) {
412 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
413
414 pr_debug("Halting core %d VP%d\n", core, vpe_id);
415 if (cpu_has_mipsmt) {
416 /* Halt this TC */
417 write_c0_tchalt(TCHALT_H);
418 instruction_hazard();
419 } else if (cpu_has_vp) {
420 write_cpc_cl_vp_stop(1 << vpe_id);
421
422 /* Ensure that the VP_STOP register is written */
423 wmb();
424 }
425 } else {
426 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
427 pr_debug("Gating power to core %d\n", core);
428 /* Power down the core */
429 cps_pm_enter_state(CPS_PM_POWER_GATED);
430 }
431 }
432 }
433
434 #ifdef CONFIG_KEXEC
435
cps_kexec_nonboot_cpu(void)436 static void cps_kexec_nonboot_cpu(void)
437 {
438 if (cpu_has_mipsmt || cpu_has_vp)
439 cps_shutdown_this_cpu(CPU_DEATH_HALT);
440 else
441 cps_shutdown_this_cpu(CPU_DEATH_POWER);
442 }
443
444 #endif /* CONFIG_KEXEC */
445
446 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
447
448 #ifdef CONFIG_HOTPLUG_CPU
449
cps_cpu_disable(void)450 static int cps_cpu_disable(void)
451 {
452 unsigned cpu = smp_processor_id();
453 struct core_boot_config *core_cfg;
454
455 if (!cpu)
456 return -EBUSY;
457
458 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
459 return -EINVAL;
460
461 core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)];
462 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
463 smp_mb__after_atomic();
464 set_cpu_online(cpu, false);
465 calculate_cpu_foreign_map();
466
467 return 0;
468 }
469
470 static unsigned cpu_death_sibling;
471 static enum cpu_death cpu_death;
472
play_dead(void)473 void play_dead(void)
474 {
475 unsigned int cpu;
476
477 local_irq_disable();
478 idle_task_exit();
479 cpu = smp_processor_id();
480 cpu_death = CPU_DEATH_POWER;
481
482 pr_debug("CPU%d going offline\n", cpu);
483
484 if (cpu_has_mipsmt || cpu_has_vp) {
485 /* Look for another online VPE within the core */
486 for_each_online_cpu(cpu_death_sibling) {
487 if (!cpus_are_siblings(cpu, cpu_death_sibling))
488 continue;
489
490 /*
491 * There is an online VPE within the core. Just halt
492 * this TC and leave the core alone.
493 */
494 cpu_death = CPU_DEATH_HALT;
495 break;
496 }
497 }
498
499 /* This CPU has chosen its way out */
500 (void)cpu_report_death();
501
502 cps_shutdown_this_cpu(cpu_death);
503
504 /* This should never be reached */
505 panic("Failed to offline CPU %u", cpu);
506 }
507
wait_for_sibling_halt(void * ptr_cpu)508 static void wait_for_sibling_halt(void *ptr_cpu)
509 {
510 unsigned cpu = (unsigned long)ptr_cpu;
511 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
512 unsigned halted;
513 unsigned long flags;
514
515 do {
516 local_irq_save(flags);
517 settc(vpe_id);
518 halted = read_tc_c0_tchalt();
519 local_irq_restore(flags);
520 } while (!(halted & TCHALT_H));
521 }
522
cps_cpu_die(unsigned int cpu)523 static void cps_cpu_die(unsigned int cpu)
524 {
525 unsigned core = cpu_core(&cpu_data[cpu]);
526 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
527 ktime_t fail_time;
528 unsigned stat;
529 int err;
530
531 /* Wait for the cpu to choose its way out */
532 if (!cpu_wait_death(cpu, 5)) {
533 pr_err("CPU%u: didn't offline\n", cpu);
534 return;
535 }
536
537 /*
538 * Now wait for the CPU to actually offline. Without doing this that
539 * offlining may race with one or more of:
540 *
541 * - Onlining the CPU again.
542 * - Powering down the core if another VPE within it is offlined.
543 * - A sibling VPE entering a non-coherent state.
544 *
545 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
546 * with which we could race, so do nothing.
547 */
548 if (cpu_death == CPU_DEATH_POWER) {
549 /*
550 * Wait for the core to enter a powered down or clock gated
551 * state, the latter happening when a JTAG probe is connected
552 * in which case the CPC will refuse to power down the core.
553 */
554 fail_time = ktime_add_ms(ktime_get(), 2000);
555 do {
556 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
557 mips_cpc_lock_other(core);
558 stat = read_cpc_co_stat_conf();
559 stat &= CPC_Cx_STAT_CONF_SEQSTATE;
560 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
561 mips_cpc_unlock_other();
562 mips_cm_unlock_other();
563
564 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
565 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
566 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
567 break;
568
569 /*
570 * The core ought to have powered down, but didn't &
571 * now we don't really know what state it's in. It's
572 * likely that its _pwr_up pin has been wired to logic
573 * 1 & it powered back up as soon as we powered it
574 * down...
575 *
576 * The best we can do is warn the user & continue in
577 * the hope that the core is doing nothing harmful &
578 * might behave properly if we online it later.
579 */
580 if (WARN(ktime_after(ktime_get(), fail_time),
581 "CPU%u hasn't powered down, seq. state %u\n",
582 cpu, stat))
583 break;
584 } while (1);
585
586 /* Indicate the core is powered off */
587 bitmap_clear(core_power, core, 1);
588 } else if (cpu_has_mipsmt) {
589 /*
590 * Have a CPU with access to the offlined CPUs registers wait
591 * for its TC to halt.
592 */
593 err = smp_call_function_single(cpu_death_sibling,
594 wait_for_sibling_halt,
595 (void *)(unsigned long)cpu, 1);
596 if (err)
597 panic("Failed to call remote sibling CPU\n");
598 } else if (cpu_has_vp) {
599 do {
600 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
601 stat = read_cpc_co_vp_running();
602 mips_cm_unlock_other();
603 } while (stat & (1 << vpe_id));
604 }
605 }
606
607 #endif /* CONFIG_HOTPLUG_CPU */
608
609 static const struct plat_smp_ops cps_smp_ops = {
610 .smp_setup = cps_smp_setup,
611 .prepare_cpus = cps_prepare_cpus,
612 .boot_secondary = cps_boot_secondary,
613 .init_secondary = cps_init_secondary,
614 .smp_finish = cps_smp_finish,
615 .send_ipi_single = mips_smp_send_ipi_single,
616 .send_ipi_mask = mips_smp_send_ipi_mask,
617 #ifdef CONFIG_HOTPLUG_CPU
618 .cpu_disable = cps_cpu_disable,
619 .cpu_die = cps_cpu_die,
620 #endif
621 #ifdef CONFIG_KEXEC
622 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu,
623 #endif
624 };
625
mips_cps_smp_in_use(void)626 bool mips_cps_smp_in_use(void)
627 {
628 extern const struct plat_smp_ops *mp_ops;
629 return mp_ops == &cps_smp_ops;
630 }
631
register_cps_smp_ops(void)632 int register_cps_smp_ops(void)
633 {
634 if (!mips_cm_present()) {
635 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
636 return -ENODEV;
637 }
638
639 /* check we have a GIC - we need one for IPIs */
640 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
641 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
642 return -ENODEV;
643 }
644
645 register_smp_ops(&cps_smp_ops);
646 return 0;
647 }
648