1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2017, Nicholas Piggin, IBM Corporation
4 */
5
6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
7
8 #include <linux/export.h>
9 #include <linux/init.h>
10 #include <linux/jump_label.h>
11 #include <linux/libfdt.h>
12 #include <linux/memblock.h>
13 #include <linux/printk.h>
14 #include <linux/sched.h>
15 #include <linux/string.h>
16 #include <linux/threads.h>
17
18 #include <asm/cputable.h>
19 #include <asm/dt_cpu_ftrs.h>
20 #include <asm/mce.h>
21 #include <asm/mmu.h>
22 #include <asm/oprofile_impl.h>
23 #include <asm/prom.h>
24 #include <asm/setup.h>
25
26
27 /* Device-tree visible constants follow */
28 #define ISA_V3_0B 3000
29 #define ISA_V3_1 3100
30
31 #define USABLE_PR (1U << 0)
32 #define USABLE_OS (1U << 1)
33 #define USABLE_HV (1U << 2)
34
35 #define HV_SUPPORT_HFSCR (1U << 0)
36 #define OS_SUPPORT_FSCR (1U << 0)
37
38 /* For parsing, we define all bits set as "NONE" case */
39 #define HV_SUPPORT_NONE 0xffffffffU
40 #define OS_SUPPORT_NONE 0xffffffffU
41
42 struct dt_cpu_feature {
43 const char *name;
44 uint32_t isa;
45 uint32_t usable_privilege;
46 uint32_t hv_support;
47 uint32_t os_support;
48 uint32_t hfscr_bit_nr;
49 uint32_t fscr_bit_nr;
50 uint32_t hwcap_bit_nr;
51 /* fdt parsing */
52 unsigned long node;
53 int enabled;
54 int disabled;
55 };
56
57 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
58
59 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
60 PPC_FEATURE_ARCH_2_06 |\
61 PPC_FEATURE_ICACHE_SNOOP)
62 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
63 PPC_FEATURE2_ISEL)
64 /*
65 * Set up the base CPU
66 */
67
68 static int hv_mode;
69
70 static struct {
71 u64 lpcr;
72 u64 lpcr_clear;
73 u64 hfscr;
74 u64 fscr;
75 u64 pcr;
76 } system_registers;
77
78 static void (*init_pmu_registers)(void);
79
__restore_cpu_cpufeatures(void)80 static void __restore_cpu_cpufeatures(void)
81 {
82 u64 lpcr;
83
84 /*
85 * LPCR is restored by the power on engine already. It can be changed
86 * after early init e.g., by radix enable, and we have no unified API
87 * for saving and restoring such SPRs.
88 *
89 * This ->restore hook should really be removed from idle and register
90 * restore moved directly into the idle restore code, because this code
91 * doesn't know how idle is implemented or what it needs restored here.
92 *
93 * The best we can do to accommodate secondary boot and idle restore
94 * for now is "or" LPCR with existing.
95 */
96 lpcr = mfspr(SPRN_LPCR);
97 lpcr |= system_registers.lpcr;
98 lpcr &= ~system_registers.lpcr_clear;
99 mtspr(SPRN_LPCR, lpcr);
100 if (hv_mode) {
101 mtspr(SPRN_LPID, 0);
102 mtspr(SPRN_HFSCR, system_registers.hfscr);
103 mtspr(SPRN_PCR, system_registers.pcr);
104 }
105 mtspr(SPRN_FSCR, system_registers.fscr);
106
107 if (init_pmu_registers)
108 init_pmu_registers();
109 }
110
111 static char dt_cpu_name[64];
112
113 static struct cpu_spec __initdata base_cpu_spec = {
114 .cpu_name = NULL,
115 .cpu_features = CPU_FTRS_DT_CPU_BASE,
116 .cpu_user_features = COMMON_USER_BASE,
117 .cpu_user_features2 = COMMON_USER2_BASE,
118 .mmu_features = 0,
119 .icache_bsize = 32, /* minimum block size, fixed by */
120 .dcache_bsize = 32, /* cache info init. */
121 .num_pmcs = 0,
122 .pmc_type = PPC_PMC_DEFAULT,
123 .oprofile_cpu_type = NULL,
124 .oprofile_type = PPC_OPROFILE_INVALID,
125 .cpu_setup = NULL,
126 .cpu_restore = __restore_cpu_cpufeatures,
127 .machine_check_early = NULL,
128 .platform = NULL,
129 };
130
cpufeatures_setup_cpu(void)131 static void __init cpufeatures_setup_cpu(void)
132 {
133 set_cur_cpu_spec(&base_cpu_spec);
134
135 cur_cpu_spec->pvr_mask = -1;
136 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
137
138 /* Initialize the base environment -- clear FSCR/HFSCR. */
139 hv_mode = !!(mfmsr() & MSR_HV);
140 if (hv_mode) {
141 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
142 mtspr(SPRN_HFSCR, 0);
143 }
144 mtspr(SPRN_FSCR, 0);
145 mtspr(SPRN_PCR, PCR_MASK);
146
147 /*
148 * LPCR does not get cleared, to match behaviour with secondaries
149 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this
150 * could clear LPCR too.
151 */
152 }
153
feat_try_enable_unknown(struct dt_cpu_feature * f)154 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
155 {
156 if (f->hv_support == HV_SUPPORT_NONE) {
157 } else if (f->hv_support & HV_SUPPORT_HFSCR) {
158 u64 hfscr = mfspr(SPRN_HFSCR);
159 hfscr |= 1UL << f->hfscr_bit_nr;
160 mtspr(SPRN_HFSCR, hfscr);
161 } else {
162 /* Does not have a known recipe */
163 return 0;
164 }
165
166 if (f->os_support == OS_SUPPORT_NONE) {
167 } else if (f->os_support & OS_SUPPORT_FSCR) {
168 u64 fscr = mfspr(SPRN_FSCR);
169 fscr |= 1UL << f->fscr_bit_nr;
170 mtspr(SPRN_FSCR, fscr);
171 } else {
172 /* Does not have a known recipe */
173 return 0;
174 }
175
176 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
177 uint32_t word = f->hwcap_bit_nr / 32;
178 uint32_t bit = f->hwcap_bit_nr % 32;
179
180 if (word == 0)
181 cur_cpu_spec->cpu_user_features |= 1U << bit;
182 else if (word == 1)
183 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
184 else
185 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
186 }
187
188 return 1;
189 }
190
feat_enable(struct dt_cpu_feature * f)191 static int __init feat_enable(struct dt_cpu_feature *f)
192 {
193 if (f->hv_support != HV_SUPPORT_NONE) {
194 if (f->hfscr_bit_nr != -1) {
195 u64 hfscr = mfspr(SPRN_HFSCR);
196 hfscr |= 1UL << f->hfscr_bit_nr;
197 mtspr(SPRN_HFSCR, hfscr);
198 }
199 }
200
201 if (f->os_support != OS_SUPPORT_NONE) {
202 if (f->fscr_bit_nr != -1) {
203 u64 fscr = mfspr(SPRN_FSCR);
204 fscr |= 1UL << f->fscr_bit_nr;
205 mtspr(SPRN_FSCR, fscr);
206 }
207 }
208
209 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
210 uint32_t word = f->hwcap_bit_nr / 32;
211 uint32_t bit = f->hwcap_bit_nr % 32;
212
213 if (word == 0)
214 cur_cpu_spec->cpu_user_features |= 1U << bit;
215 else if (word == 1)
216 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
217 else
218 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
219 }
220
221 return 1;
222 }
223
feat_disable(struct dt_cpu_feature * f)224 static int __init feat_disable(struct dt_cpu_feature *f)
225 {
226 return 0;
227 }
228
feat_enable_hv(struct dt_cpu_feature * f)229 static int __init feat_enable_hv(struct dt_cpu_feature *f)
230 {
231 u64 lpcr;
232
233 if (!hv_mode) {
234 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
235 return 0;
236 }
237
238 mtspr(SPRN_LPID, 0);
239
240 lpcr = mfspr(SPRN_LPCR);
241 lpcr &= ~LPCR_LPES0; /* HV external interrupts */
242 mtspr(SPRN_LPCR, lpcr);
243
244 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
245
246 return 1;
247 }
248
feat_enable_le(struct dt_cpu_feature * f)249 static int __init feat_enable_le(struct dt_cpu_feature *f)
250 {
251 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
252 return 1;
253 }
254
feat_enable_smt(struct dt_cpu_feature * f)255 static int __init feat_enable_smt(struct dt_cpu_feature *f)
256 {
257 cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
258 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
259 return 1;
260 }
261
feat_enable_idle_nap(struct dt_cpu_feature * f)262 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
263 {
264 u64 lpcr;
265
266 /* Set PECE wakeup modes for ISA 207 */
267 lpcr = mfspr(SPRN_LPCR);
268 lpcr |= LPCR_PECE0;
269 lpcr |= LPCR_PECE1;
270 lpcr |= LPCR_PECE2;
271 mtspr(SPRN_LPCR, lpcr);
272
273 return 1;
274 }
275
feat_enable_align_dsisr(struct dt_cpu_feature * f)276 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
277 {
278 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
279
280 return 1;
281 }
282
feat_enable_idle_stop(struct dt_cpu_feature * f)283 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
284 {
285 u64 lpcr;
286
287 /* Set PECE wakeup modes for ISAv3.0B */
288 lpcr = mfspr(SPRN_LPCR);
289 lpcr |= LPCR_PECE0;
290 lpcr |= LPCR_PECE1;
291 lpcr |= LPCR_PECE2;
292 mtspr(SPRN_LPCR, lpcr);
293
294 return 1;
295 }
296
feat_enable_mmu_hash(struct dt_cpu_feature * f)297 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
298 {
299 u64 lpcr;
300
301 lpcr = mfspr(SPRN_LPCR);
302 lpcr &= ~LPCR_ISL;
303
304 /* VRMASD */
305 lpcr |= LPCR_VPM0;
306 lpcr &= ~LPCR_VPM1;
307 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
308 mtspr(SPRN_LPCR, lpcr);
309
310 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
311 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
312
313 return 1;
314 }
315
feat_enable_mmu_hash_v3(struct dt_cpu_feature * f)316 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
317 {
318 u64 lpcr;
319
320 system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR);
321 lpcr = mfspr(SPRN_LPCR);
322 lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR);
323 mtspr(SPRN_LPCR, lpcr);
324
325 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
326 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
327
328 return 1;
329 }
330
331
feat_enable_mmu_radix(struct dt_cpu_feature * f)332 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
333 {
334 #ifdef CONFIG_PPC_RADIX_MMU
335 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
336 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
337 cur_cpu_spec->mmu_features |= MMU_FTR_GTSE;
338 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
339
340 return 1;
341 #endif
342 return 0;
343 }
344
feat_enable_dscr(struct dt_cpu_feature * f)345 static int __init feat_enable_dscr(struct dt_cpu_feature *f)
346 {
347 u64 lpcr;
348
349 /*
350 * Linux relies on FSCR[DSCR] being clear, so that we can take the
351 * facility unavailable interrupt and track the task's usage of DSCR.
352 * See facility_unavailable_exception().
353 * Clear the bit here so that feat_enable() doesn't set it.
354 */
355 f->fscr_bit_nr = -1;
356
357 feat_enable(f);
358
359 lpcr = mfspr(SPRN_LPCR);
360 lpcr &= ~LPCR_DPFD;
361 lpcr |= (4UL << LPCR_DPFD_SH);
362 mtspr(SPRN_LPCR, lpcr);
363
364 return 1;
365 }
366
hfscr_pmu_enable(void)367 static void hfscr_pmu_enable(void)
368 {
369 u64 hfscr = mfspr(SPRN_HFSCR);
370 hfscr |= PPC_BIT(60);
371 mtspr(SPRN_HFSCR, hfscr);
372 }
373
init_pmu_power8(void)374 static void init_pmu_power8(void)
375 {
376 if (hv_mode) {
377 mtspr(SPRN_MMCRC, 0);
378 mtspr(SPRN_MMCRH, 0);
379 }
380
381 mtspr(SPRN_MMCRA, 0);
382 mtspr(SPRN_MMCR0, 0);
383 mtspr(SPRN_MMCR1, 0);
384 mtspr(SPRN_MMCR2, 0);
385 mtspr(SPRN_MMCRS, 0);
386 }
387
feat_enable_mce_power8(struct dt_cpu_feature * f)388 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
389 {
390 cur_cpu_spec->platform = "power8";
391 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
392
393 return 1;
394 }
395
feat_enable_pmu_power8(struct dt_cpu_feature * f)396 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
397 {
398 hfscr_pmu_enable();
399
400 init_pmu_power8();
401 init_pmu_registers = init_pmu_power8;
402
403 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
404 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
405 if (pvr_version_is(PVR_POWER8E))
406 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
407
408 cur_cpu_spec->num_pmcs = 6;
409 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
410 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8";
411
412 return 1;
413 }
414
init_pmu_power9(void)415 static void init_pmu_power9(void)
416 {
417 if (hv_mode)
418 mtspr(SPRN_MMCRC, 0);
419
420 mtspr(SPRN_MMCRA, 0);
421 mtspr(SPRN_MMCR0, 0);
422 mtspr(SPRN_MMCR1, 0);
423 mtspr(SPRN_MMCR2, 0);
424 }
425
feat_enable_mce_power9(struct dt_cpu_feature * f)426 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
427 {
428 cur_cpu_spec->platform = "power9";
429 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
430
431 return 1;
432 }
433
feat_enable_pmu_power9(struct dt_cpu_feature * f)434 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
435 {
436 hfscr_pmu_enable();
437
438 init_pmu_power9();
439 init_pmu_registers = init_pmu_power9;
440
441 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
442 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
443
444 cur_cpu_spec->num_pmcs = 6;
445 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
446 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9";
447
448 return 1;
449 }
450
init_pmu_power10(void)451 static void init_pmu_power10(void)
452 {
453 init_pmu_power9();
454
455 mtspr(SPRN_MMCR3, 0);
456 mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
457 mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);
458 }
459
feat_enable_pmu_power10(struct dt_cpu_feature * f)460 static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
461 {
462 hfscr_pmu_enable();
463
464 init_pmu_power10();
465 init_pmu_registers = init_pmu_power10;
466
467 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
468 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
469
470 cur_cpu_spec->num_pmcs = 6;
471 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
472 cur_cpu_spec->oprofile_cpu_type = "ppc64/power10";
473
474 return 1;
475 }
476
feat_enable_mce_power10(struct dt_cpu_feature * f)477 static int __init feat_enable_mce_power10(struct dt_cpu_feature *f)
478 {
479 cur_cpu_spec->platform = "power10";
480 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p10;
481
482 return 1;
483 }
484
feat_enable_tm(struct dt_cpu_feature * f)485 static int __init feat_enable_tm(struct dt_cpu_feature *f)
486 {
487 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
488 feat_enable(f);
489 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
490 return 1;
491 #endif
492 return 0;
493 }
494
feat_enable_fp(struct dt_cpu_feature * f)495 static int __init feat_enable_fp(struct dt_cpu_feature *f)
496 {
497 feat_enable(f);
498 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
499
500 return 1;
501 }
502
feat_enable_vector(struct dt_cpu_feature * f)503 static int __init feat_enable_vector(struct dt_cpu_feature *f)
504 {
505 #ifdef CONFIG_ALTIVEC
506 feat_enable(f);
507 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
508 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
509 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
510
511 return 1;
512 #endif
513 return 0;
514 }
515
feat_enable_vsx(struct dt_cpu_feature * f)516 static int __init feat_enable_vsx(struct dt_cpu_feature *f)
517 {
518 #ifdef CONFIG_VSX
519 feat_enable(f);
520 cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
521 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
522
523 return 1;
524 #endif
525 return 0;
526 }
527
feat_enable_purr(struct dt_cpu_feature * f)528 static int __init feat_enable_purr(struct dt_cpu_feature *f)
529 {
530 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
531
532 return 1;
533 }
534
feat_enable_ebb(struct dt_cpu_feature * f)535 static int __init feat_enable_ebb(struct dt_cpu_feature *f)
536 {
537 /*
538 * PPC_FEATURE2_EBB is enabled in PMU init code because it has
539 * historically been related to the PMU facility. This may have
540 * to be decoupled if EBB becomes more generic. For now, follow
541 * existing convention.
542 */
543 f->hwcap_bit_nr = -1;
544 feat_enable(f);
545
546 return 1;
547 }
548
feat_enable_dbell(struct dt_cpu_feature * f)549 static int __init feat_enable_dbell(struct dt_cpu_feature *f)
550 {
551 u64 lpcr;
552
553 /* P9 has an HFSCR for privileged state */
554 feat_enable(f);
555
556 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
557
558 lpcr = mfspr(SPRN_LPCR);
559 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */
560 mtspr(SPRN_LPCR, lpcr);
561
562 return 1;
563 }
564
feat_enable_hvi(struct dt_cpu_feature * f)565 static int __init feat_enable_hvi(struct dt_cpu_feature *f)
566 {
567 u64 lpcr;
568
569 /*
570 * POWER9 XIVE interrupts including in OPAL XICS compatibility
571 * are always delivered as hypervisor virtualization interrupts (HVI)
572 * rather than EE.
573 *
574 * However LPES0 is not set here, in the chance that an EE does get
575 * delivered to the host somehow, the EE handler would not expect it
576 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could
577 * happen if there is a bug in interrupt controller code, or IC is
578 * misconfigured in systemsim.
579 */
580
581 lpcr = mfspr(SPRN_LPCR);
582 lpcr |= LPCR_HVICE; /* enable hvi interrupts */
583 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */
584 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
585 mtspr(SPRN_LPCR, lpcr);
586
587 return 1;
588 }
589
feat_enable_large_ci(struct dt_cpu_feature * f)590 static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
591 {
592 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
593
594 return 1;
595 }
596
feat_enable_mma(struct dt_cpu_feature * f)597 static int __init feat_enable_mma(struct dt_cpu_feature *f)
598 {
599 u64 pcr;
600
601 feat_enable(f);
602 pcr = mfspr(SPRN_PCR);
603 pcr &= ~PCR_MMA_DIS;
604 mtspr(SPRN_PCR, pcr);
605
606 return 1;
607 }
608
609 struct dt_cpu_feature_match {
610 const char *name;
611 int (*enable)(struct dt_cpu_feature *f);
612 u64 cpu_ftr_bit_mask;
613 };
614
615 static struct dt_cpu_feature_match __initdata
616 dt_cpu_feature_match_table[] = {
617 {"hypervisor", feat_enable_hv, 0},
618 {"big-endian", feat_enable, 0},
619 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
620 {"smt", feat_enable_smt, 0},
621 {"interrupt-facilities", feat_enable, 0},
622 {"system-call-vectored", feat_enable, 0},
623 {"timer-facilities", feat_enable, 0},
624 {"timer-facilities-v3", feat_enable, 0},
625 {"debug-facilities", feat_enable, 0},
626 {"come-from-address-register", feat_enable, CPU_FTR_CFAR},
627 {"branch-tracing", feat_enable, 0},
628 {"floating-point", feat_enable_fp, 0},
629 {"vector", feat_enable_vector, 0},
630 {"vector-scalar", feat_enable_vsx, 0},
631 {"vector-scalar-v3", feat_enable, 0},
632 {"decimal-floating-point", feat_enable, 0},
633 {"decimal-integer", feat_enable, 0},
634 {"quadword-load-store", feat_enable, 0},
635 {"vector-crypto", feat_enable, 0},
636 {"mmu-hash", feat_enable_mmu_hash, 0},
637 {"mmu-radix", feat_enable_mmu_radix, 0},
638 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
639 {"virtual-page-class-key-protection", feat_enable, 0},
640 {"transactional-memory", feat_enable_tm, CPU_FTR_TM},
641 {"transactional-memory-v3", feat_enable_tm, 0},
642 {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST},
643 {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG},
644 {"idle-nap", feat_enable_idle_nap, 0},
645 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
646 {"idle-stop", feat_enable_idle_stop, 0},
647 {"machine-check-power8", feat_enable_mce_power8, 0},
648 {"performance-monitor-power8", feat_enable_pmu_power8, 0},
649 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
650 {"event-based-branch", feat_enable_ebb, 0},
651 {"target-address-register", feat_enable, 0},
652 {"branch-history-rolling-buffer", feat_enable, 0},
653 {"control-register", feat_enable, CPU_FTR_CTRL},
654 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
655 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
656 {"processor-utilization-of-resources-register", feat_enable_purr, 0},
657 {"no-execute", feat_enable, 0},
658 {"strong-access-ordering", feat_enable, CPU_FTR_SAO},
659 {"cache-inhibited-large-page", feat_enable_large_ci, 0},
660 {"coprocessor-icswx", feat_enable, 0},
661 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
662 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
663 {"wait", feat_enable, 0},
664 {"atomic-memory-operations", feat_enable, 0},
665 {"branch-v3", feat_enable, 0},
666 {"copy-paste", feat_enable, 0},
667 {"decimal-floating-point-v3", feat_enable, 0},
668 {"decimal-integer-v3", feat_enable, 0},
669 {"fixed-point-v3", feat_enable, 0},
670 {"floating-point-v3", feat_enable, 0},
671 {"group-start-register", feat_enable, 0},
672 {"pc-relative-addressing", feat_enable, 0},
673 {"machine-check-power9", feat_enable_mce_power9, 0},
674 {"machine-check-power10", feat_enable_mce_power10, 0},
675 {"performance-monitor-power9", feat_enable_pmu_power9, 0},
676 {"performance-monitor-power10", feat_enable_pmu_power10, 0},
677 {"event-based-branch-v3", feat_enable, 0},
678 {"random-number-generator", feat_enable, 0},
679 {"system-call-vectored", feat_disable, 0},
680 {"trace-interrupt-v3", feat_enable, 0},
681 {"vector-v3", feat_enable, 0},
682 {"vector-binary128", feat_enable, 0},
683 {"vector-binary16", feat_enable, 0},
684 {"wait-v3", feat_enable, 0},
685 {"prefix-instructions", feat_enable, 0},
686 {"matrix-multiply-assist", feat_enable_mma, 0},
687 {"debug-facilities-v31", feat_enable, CPU_FTR_DAWR1},
688 };
689
690 static bool __initdata using_dt_cpu_ftrs;
691 static bool __initdata enable_unknown = true;
692
dt_cpu_ftrs_parse(char * str)693 static int __init dt_cpu_ftrs_parse(char *str)
694 {
695 if (!str)
696 return 0;
697
698 if (!strcmp(str, "off"))
699 using_dt_cpu_ftrs = false;
700 else if (!strcmp(str, "known"))
701 enable_unknown = false;
702 else
703 return 1;
704
705 return 0;
706 }
707 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse);
708
cpufeatures_setup_start(u32 isa)709 static void __init cpufeatures_setup_start(u32 isa)
710 {
711 pr_info("setup for ISA %d\n", isa);
712
713 if (isa >= ISA_V3_0B) {
714 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
715 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
716 }
717
718 if (isa >= ISA_V3_1) {
719 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_31;
720 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_1;
721 }
722 }
723
cpufeatures_process_feature(struct dt_cpu_feature * f)724 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
725 {
726 const struct dt_cpu_feature_match *m;
727 bool known = false;
728 int i;
729
730 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
731 m = &dt_cpu_feature_match_table[i];
732 if (!strcmp(f->name, m->name)) {
733 known = true;
734 if (m->enable(f)) {
735 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
736 break;
737 }
738
739 pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
740 f->name);
741 return false;
742 }
743 }
744
745 if (!known && (!enable_unknown || !feat_try_enable_unknown(f))) {
746 pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
747 f->name);
748 return false;
749 }
750
751 if (known)
752 pr_debug("enabling: %s\n", f->name);
753 else
754 pr_debug("enabling: %s (unknown)\n", f->name);
755
756 return true;
757 }
758
759 /*
760 * Handle POWER9 broadcast tlbie invalidation issue using
761 * cpu feature flag.
762 */
update_tlbie_feature_flag(unsigned long pvr)763 static __init void update_tlbie_feature_flag(unsigned long pvr)
764 {
765 if (PVR_VER(pvr) == PVR_POWER9) {
766 /*
767 * Set the tlbie feature flag for anything below
768 * Nimbus DD 2.3 and Cumulus DD 1.3
769 */
770 if ((pvr & 0xe000) == 0) {
771 /* Nimbus */
772 if ((pvr & 0xfff) < 0x203)
773 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
774 } else if ((pvr & 0xc000) == 0) {
775 /* Cumulus */
776 if ((pvr & 0xfff) < 0x103)
777 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
778 } else {
779 WARN_ONCE(1, "Unknown PVR");
780 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
781 }
782
783 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_ERAT_BUG;
784 }
785 }
786
cpufeatures_cpu_quirks(void)787 static __init void cpufeatures_cpu_quirks(void)
788 {
789 unsigned long version = mfspr(SPRN_PVR);
790
791 /*
792 * Not all quirks can be derived from the cpufeatures device tree.
793 */
794 if ((version & 0xffffefff) == 0x004e0200) {
795 /* DD2.0 has no feature flag */
796 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
797 } else if ((version & 0xffffefff) == 0x004e0201) {
798 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
799 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
800 } else if ((version & 0xffffefff) == 0x004e0202) {
801 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST;
802 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG;
803 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
804 } else if ((version & 0xffff0000) == 0x004e0000) {
805 /* DD2.1 and up have DD2_1 */
806 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
807 }
808
809 if ((version & 0xffff0000) == 0x004e0000) {
810 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
811 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TIDR;
812 }
813
814 update_tlbie_feature_flag(version);
815 }
816
cpufeatures_setup_finished(void)817 static void __init cpufeatures_setup_finished(void)
818 {
819 cpufeatures_cpu_quirks();
820
821 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
822 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
823 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
824 }
825
826 /* Make sure powerpc_base_platform is non-NULL */
827 powerpc_base_platform = cur_cpu_spec->platform;
828
829 system_registers.lpcr = mfspr(SPRN_LPCR);
830 system_registers.hfscr = mfspr(SPRN_HFSCR);
831 system_registers.fscr = mfspr(SPRN_FSCR);
832 system_registers.pcr = mfspr(SPRN_PCR);
833
834 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
835 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
836 }
837
disabled_on_cmdline(void)838 static int __init disabled_on_cmdline(void)
839 {
840 unsigned long root, chosen;
841 const char *p;
842
843 root = of_get_flat_dt_root();
844 chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
845 if (chosen == -FDT_ERR_NOTFOUND)
846 return false;
847
848 p = of_get_flat_dt_prop(chosen, "bootargs", NULL);
849 if (!p)
850 return false;
851
852 if (strstr(p, "dt_cpu_ftrs=off"))
853 return true;
854
855 return false;
856 }
857
fdt_find_cpu_features(unsigned long node,const char * uname,int depth,void * data)858 static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
859 int depth, void *data)
860 {
861 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
862 && of_get_flat_dt_prop(node, "isa", NULL))
863 return 1;
864
865 return 0;
866 }
867
dt_cpu_ftrs_in_use(void)868 bool __init dt_cpu_ftrs_in_use(void)
869 {
870 return using_dt_cpu_ftrs;
871 }
872
dt_cpu_ftrs_init(void * fdt)873 bool __init dt_cpu_ftrs_init(void *fdt)
874 {
875 using_dt_cpu_ftrs = false;
876
877 /* Setup and verify the FDT, if it fails we just bail */
878 if (!early_init_dt_verify(fdt))
879 return false;
880
881 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
882 return false;
883
884 if (disabled_on_cmdline())
885 return false;
886
887 cpufeatures_setup_cpu();
888
889 using_dt_cpu_ftrs = true;
890 return true;
891 }
892
893 static int nr_dt_cpu_features;
894 static struct dt_cpu_feature *dt_cpu_features;
895
process_cpufeatures_node(unsigned long node,const char * uname,int i)896 static int __init process_cpufeatures_node(unsigned long node,
897 const char *uname, int i)
898 {
899 const __be32 *prop;
900 struct dt_cpu_feature *f;
901 int len;
902
903 f = &dt_cpu_features[i];
904
905 f->node = node;
906
907 f->name = uname;
908
909 prop = of_get_flat_dt_prop(node, "isa", &len);
910 if (!prop) {
911 pr_warn("%s: missing isa property\n", uname);
912 return 0;
913 }
914 f->isa = be32_to_cpup(prop);
915
916 prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
917 if (!prop) {
918 pr_warn("%s: missing usable-privilege property", uname);
919 return 0;
920 }
921 f->usable_privilege = be32_to_cpup(prop);
922
923 prop = of_get_flat_dt_prop(node, "hv-support", &len);
924 if (prop)
925 f->hv_support = be32_to_cpup(prop);
926 else
927 f->hv_support = HV_SUPPORT_NONE;
928
929 prop = of_get_flat_dt_prop(node, "os-support", &len);
930 if (prop)
931 f->os_support = be32_to_cpup(prop);
932 else
933 f->os_support = OS_SUPPORT_NONE;
934
935 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
936 if (prop)
937 f->hfscr_bit_nr = be32_to_cpup(prop);
938 else
939 f->hfscr_bit_nr = -1;
940 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
941 if (prop)
942 f->fscr_bit_nr = be32_to_cpup(prop);
943 else
944 f->fscr_bit_nr = -1;
945 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
946 if (prop)
947 f->hwcap_bit_nr = be32_to_cpup(prop);
948 else
949 f->hwcap_bit_nr = -1;
950
951 if (f->usable_privilege & USABLE_HV) {
952 if (!(mfmsr() & MSR_HV)) {
953 pr_warn("%s: HV feature passed to guest\n", uname);
954 return 0;
955 }
956
957 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
958 pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
959 return 0;
960 }
961
962 if (f->hv_support == HV_SUPPORT_HFSCR) {
963 if (f->hfscr_bit_nr == -1) {
964 pr_warn("%s: missing hfscr_bit_nr\n", uname);
965 return 0;
966 }
967 }
968 } else {
969 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
970 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
971 return 0;
972 }
973 }
974
975 if (f->usable_privilege & USABLE_OS) {
976 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
977 pr_warn("%s: unwanted fscr_bit_nr\n", uname);
978 return 0;
979 }
980
981 if (f->os_support == OS_SUPPORT_FSCR) {
982 if (f->fscr_bit_nr == -1) {
983 pr_warn("%s: missing fscr_bit_nr\n", uname);
984 return 0;
985 }
986 }
987 } else {
988 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
989 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
990 return 0;
991 }
992 }
993
994 if (!(f->usable_privilege & USABLE_PR)) {
995 if (f->hwcap_bit_nr != -1) {
996 pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
997 return 0;
998 }
999 }
1000
1001 /* Do all the independent features in the first pass */
1002 if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
1003 if (cpufeatures_process_feature(f))
1004 f->enabled = 1;
1005 else
1006 f->disabled = 1;
1007 }
1008
1009 return 0;
1010 }
1011
cpufeatures_deps_enable(struct dt_cpu_feature * f)1012 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
1013 {
1014 const __be32 *prop;
1015 int len;
1016 int nr_deps;
1017 int i;
1018
1019 if (f->enabled || f->disabled)
1020 return;
1021
1022 prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
1023 if (!prop) {
1024 pr_warn("%s: missing dependencies property", f->name);
1025 return;
1026 }
1027
1028 nr_deps = len / sizeof(int);
1029
1030 for (i = 0; i < nr_deps; i++) {
1031 unsigned long phandle = be32_to_cpu(prop[i]);
1032 int j;
1033
1034 for (j = 0; j < nr_dt_cpu_features; j++) {
1035 struct dt_cpu_feature *d = &dt_cpu_features[j];
1036
1037 if (of_get_flat_dt_phandle(d->node) == phandle) {
1038 cpufeatures_deps_enable(d);
1039 if (d->disabled) {
1040 f->disabled = 1;
1041 return;
1042 }
1043 }
1044 }
1045 }
1046
1047 if (cpufeatures_process_feature(f))
1048 f->enabled = 1;
1049 else
1050 f->disabled = 1;
1051 }
1052
scan_cpufeatures_subnodes(unsigned long node,const char * uname,void * data)1053 static int __init scan_cpufeatures_subnodes(unsigned long node,
1054 const char *uname,
1055 void *data)
1056 {
1057 int *count = data;
1058
1059 process_cpufeatures_node(node, uname, *count);
1060
1061 (*count)++;
1062
1063 return 0;
1064 }
1065
count_cpufeatures_subnodes(unsigned long node,const char * uname,void * data)1066 static int __init count_cpufeatures_subnodes(unsigned long node,
1067 const char *uname,
1068 void *data)
1069 {
1070 int *count = data;
1071
1072 (*count)++;
1073
1074 return 0;
1075 }
1076
dt_cpu_ftrs_scan_callback(unsigned long node,const char * uname,int depth,void * data)1077 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
1078 *uname, int depth, void *data)
1079 {
1080 const __be32 *prop;
1081 int count, i;
1082 u32 isa;
1083
1084 /* We are scanning "ibm,powerpc-cpu-features" nodes only */
1085 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
1086 return 0;
1087
1088 prop = of_get_flat_dt_prop(node, "isa", NULL);
1089 if (!prop)
1090 /* We checked before, "can't happen" */
1091 return 0;
1092
1093 isa = be32_to_cpup(prop);
1094
1095 /* Count and allocate space for cpu features */
1096 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
1097 &nr_dt_cpu_features);
1098 dt_cpu_features = memblock_alloc(sizeof(struct dt_cpu_feature) * nr_dt_cpu_features, PAGE_SIZE);
1099 if (!dt_cpu_features)
1100 panic("%s: Failed to allocate %zu bytes align=0x%lx\n",
1101 __func__,
1102 sizeof(struct dt_cpu_feature) * nr_dt_cpu_features,
1103 PAGE_SIZE);
1104
1105 cpufeatures_setup_start(isa);
1106
1107 /* Scan nodes into dt_cpu_features and enable those without deps */
1108 count = 0;
1109 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
1110
1111 /* Recursive enable remaining features with dependencies */
1112 for (i = 0; i < nr_dt_cpu_features; i++) {
1113 struct dt_cpu_feature *f = &dt_cpu_features[i];
1114
1115 cpufeatures_deps_enable(f);
1116 }
1117
1118 prop = of_get_flat_dt_prop(node, "display-name", NULL);
1119 if (prop && strlen((char *)prop) != 0) {
1120 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
1121 cur_cpu_spec->cpu_name = dt_cpu_name;
1122 }
1123
1124 cpufeatures_setup_finished();
1125
1126 memblock_free(__pa(dt_cpu_features),
1127 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features);
1128
1129 return 0;
1130 }
1131
dt_cpu_ftrs_scan(void)1132 void __init dt_cpu_ftrs_scan(void)
1133 {
1134 if (!using_dt_cpu_ftrs)
1135 return;
1136
1137 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);
1138 }
1139