1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Single-step support.
4 *
5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
6 */
7 #include <linux/kernel.h>
8 #include <linux/kprobes.h>
9 #include <linux/ptrace.h>
10 #include <linux/prefetch.h>
11 #include <asm/sstep.h>
12 #include <asm/processor.h>
13 #include <linux/uaccess.h>
14 #include <asm/cpu_has_feature.h>
15 #include <asm/cputable.h>
16 #include <asm/disassemble.h>
17
18 extern char system_call_common[];
19 extern char system_call_vectored_emulate[];
20
21 #ifdef CONFIG_PPC64
22 /* Bits in SRR1 that are copied from MSR */
23 #define MSR_MASK 0xffffffff87c0ffffUL
24 #else
25 #define MSR_MASK 0x87c0ffff
26 #endif
27
28 /* Bits in XER */
29 #define XER_SO 0x80000000U
30 #define XER_OV 0x40000000U
31 #define XER_CA 0x20000000U
32 #define XER_OV32 0x00080000U
33 #define XER_CA32 0x00040000U
34
35 #ifdef CONFIG_PPC_FPU
36 /*
37 * Functions in ldstfp.S
38 */
39 extern void get_fpr(int rn, double *p);
40 extern void put_fpr(int rn, const double *p);
41 extern void get_vr(int rn, __vector128 *p);
42 extern void put_vr(int rn, __vector128 *p);
43 extern void load_vsrn(int vsr, const void *p);
44 extern void store_vsrn(int vsr, void *p);
45 extern void conv_sp_to_dp(const float *sp, double *dp);
46 extern void conv_dp_to_sp(const double *dp, float *sp);
47 #endif
48
49 #ifdef __powerpc64__
50 /*
51 * Functions in quad.S
52 */
53 extern int do_lq(unsigned long ea, unsigned long *regs);
54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
57 unsigned int *crp);
58 #endif
59
60 #ifdef __LITTLE_ENDIAN__
61 #define IS_LE 1
62 #define IS_BE 0
63 #else
64 #define IS_LE 0
65 #define IS_BE 1
66 #endif
67
68 /*
69 * Emulate the truncation of 64 bit values in 32-bit mode.
70 */
truncate_if_32bit(unsigned long msr,unsigned long val)71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
72 unsigned long val)
73 {
74 #ifdef __powerpc64__
75 if ((msr & MSR_64BIT) == 0)
76 val &= 0xffffffffUL;
77 #endif
78 return val;
79 }
80
81 /*
82 * Determine whether a conditional branch instruction would branch.
83 */
branch_taken(unsigned int instr,const struct pt_regs * regs,struct instruction_op * op)84 static nokprobe_inline int branch_taken(unsigned int instr,
85 const struct pt_regs *regs,
86 struct instruction_op *op)
87 {
88 unsigned int bo = (instr >> 21) & 0x1f;
89 unsigned int bi;
90
91 if ((bo & 4) == 0) {
92 /* decrement counter */
93 op->type |= DECCTR;
94 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
95 return 0;
96 }
97 if ((bo & 0x10) == 0) {
98 /* check bit from CR */
99 bi = (instr >> 16) & 0x1f;
100 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
101 return 0;
102 }
103 return 1;
104 }
105
address_ok(struct pt_regs * regs,unsigned long ea,int nb)106 static nokprobe_inline long address_ok(struct pt_regs *regs,
107 unsigned long ea, int nb)
108 {
109 if (!user_mode(regs))
110 return 1;
111 if (access_ok((void __user *)ea, nb))
112 return 1;
113 if (access_ok((void __user *)ea, 1))
114 /* Access overlaps the end of the user region */
115 regs->dar = TASK_SIZE_MAX - 1;
116 else
117 regs->dar = ea;
118 return 0;
119 }
120
121 /*
122 * Calculate effective address for a D-form instruction
123 */
dform_ea(unsigned int instr,const struct pt_regs * regs)124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
125 const struct pt_regs *regs)
126 {
127 int ra;
128 unsigned long ea;
129
130 ra = (instr >> 16) & 0x1f;
131 ea = (signed short) instr; /* sign-extend */
132 if (ra)
133 ea += regs->gpr[ra];
134
135 return ea;
136 }
137
138 #ifdef __powerpc64__
139 /*
140 * Calculate effective address for a DS-form instruction
141 */
dsform_ea(unsigned int instr,const struct pt_regs * regs)142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
143 const struct pt_regs *regs)
144 {
145 int ra;
146 unsigned long ea;
147
148 ra = (instr >> 16) & 0x1f;
149 ea = (signed short) (instr & ~3); /* sign-extend */
150 if (ra)
151 ea += regs->gpr[ra];
152
153 return ea;
154 }
155
156 /*
157 * Calculate effective address for a DQ-form instruction
158 */
dqform_ea(unsigned int instr,const struct pt_regs * regs)159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
160 const struct pt_regs *regs)
161 {
162 int ra;
163 unsigned long ea;
164
165 ra = (instr >> 16) & 0x1f;
166 ea = (signed short) (instr & ~0xf); /* sign-extend */
167 if (ra)
168 ea += regs->gpr[ra];
169
170 return ea;
171 }
172 #endif /* __powerpc64 */
173
174 /*
175 * Calculate effective address for an X-form instruction
176 */
xform_ea(unsigned int instr,const struct pt_regs * regs)177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
178 const struct pt_regs *regs)
179 {
180 int ra, rb;
181 unsigned long ea;
182
183 ra = (instr >> 16) & 0x1f;
184 rb = (instr >> 11) & 0x1f;
185 ea = regs->gpr[rb];
186 if (ra)
187 ea += regs->gpr[ra];
188
189 return ea;
190 }
191
192 /*
193 * Calculate effective address for a MLS:D-form / 8LS:D-form
194 * prefixed instruction
195 */
mlsd_8lsd_ea(unsigned int instr,unsigned int suffix,const struct pt_regs * regs)196 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
197 unsigned int suffix,
198 const struct pt_regs *regs)
199 {
200 int ra, prefix_r;
201 unsigned int dd;
202 unsigned long ea, d0, d1, d;
203
204 prefix_r = GET_PREFIX_R(instr);
205 ra = GET_PREFIX_RA(suffix);
206
207 d0 = instr & 0x3ffff;
208 d1 = suffix & 0xffff;
209 d = (d0 << 16) | d1;
210
211 /*
212 * sign extend a 34 bit number
213 */
214 dd = (unsigned int)(d >> 2);
215 ea = (signed int)dd;
216 ea = (ea << 2) | (d & 0x3);
217
218 if (!prefix_r && ra)
219 ea += regs->gpr[ra];
220 else if (!prefix_r && !ra)
221 ; /* Leave ea as is */
222 else if (prefix_r)
223 ea += regs->nip;
224
225 /*
226 * (prefix_r && ra) is an invalid form. Should already be
227 * checked for by caller!
228 */
229
230 return ea;
231 }
232
233 /*
234 * Return the largest power of 2, not greater than sizeof(unsigned long),
235 * such that x is a multiple of it.
236 */
max_align(unsigned long x)237 static nokprobe_inline unsigned long max_align(unsigned long x)
238 {
239 x |= sizeof(unsigned long);
240 return x & -x; /* isolates rightmost bit */
241 }
242
byterev_2(unsigned long x)243 static nokprobe_inline unsigned long byterev_2(unsigned long x)
244 {
245 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
246 }
247
byterev_4(unsigned long x)248 static nokprobe_inline unsigned long byterev_4(unsigned long x)
249 {
250 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
251 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
252 }
253
254 #ifdef __powerpc64__
byterev_8(unsigned long x)255 static nokprobe_inline unsigned long byterev_8(unsigned long x)
256 {
257 return (byterev_4(x) << 32) | byterev_4(x >> 32);
258 }
259 #endif
260
do_byte_reverse(void * ptr,int nb)261 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
262 {
263 switch (nb) {
264 case 2:
265 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
266 break;
267 case 4:
268 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
269 break;
270 #ifdef __powerpc64__
271 case 8:
272 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
273 break;
274 case 16: {
275 unsigned long *up = (unsigned long *)ptr;
276 unsigned long tmp;
277 tmp = byterev_8(up[0]);
278 up[0] = byterev_8(up[1]);
279 up[1] = tmp;
280 break;
281 }
282 #endif
283 default:
284 WARN_ON_ONCE(1);
285 }
286 }
287
read_mem_aligned(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)288 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
289 unsigned long ea, int nb,
290 struct pt_regs *regs)
291 {
292 int err = 0;
293 unsigned long x = 0;
294
295 switch (nb) {
296 case 1:
297 err = __get_user(x, (unsigned char __user *) ea);
298 break;
299 case 2:
300 err = __get_user(x, (unsigned short __user *) ea);
301 break;
302 case 4:
303 err = __get_user(x, (unsigned int __user *) ea);
304 break;
305 #ifdef __powerpc64__
306 case 8:
307 err = __get_user(x, (unsigned long __user *) ea);
308 break;
309 #endif
310 }
311 if (!err)
312 *dest = x;
313 else
314 regs->dar = ea;
315 return err;
316 }
317
318 /*
319 * Copy from userspace to a buffer, using the largest possible
320 * aligned accesses, up to sizeof(long).
321 */
copy_mem_in(u8 * dest,unsigned long ea,int nb,struct pt_regs * regs)322 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
323 struct pt_regs *regs)
324 {
325 int err = 0;
326 int c;
327
328 for (; nb > 0; nb -= c) {
329 c = max_align(ea);
330 if (c > nb)
331 c = max_align(nb);
332 switch (c) {
333 case 1:
334 err = __get_user(*dest, (unsigned char __user *) ea);
335 break;
336 case 2:
337 err = __get_user(*(u16 *)dest,
338 (unsigned short __user *) ea);
339 break;
340 case 4:
341 err = __get_user(*(u32 *)dest,
342 (unsigned int __user *) ea);
343 break;
344 #ifdef __powerpc64__
345 case 8:
346 err = __get_user(*(unsigned long *)dest,
347 (unsigned long __user *) ea);
348 break;
349 #endif
350 }
351 if (err) {
352 regs->dar = ea;
353 return err;
354 }
355 dest += c;
356 ea += c;
357 }
358 return 0;
359 }
360
read_mem_unaligned(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)361 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
362 unsigned long ea, int nb,
363 struct pt_regs *regs)
364 {
365 union {
366 unsigned long ul;
367 u8 b[sizeof(unsigned long)];
368 } u;
369 int i;
370 int err;
371
372 u.ul = 0;
373 i = IS_BE ? sizeof(unsigned long) - nb : 0;
374 err = copy_mem_in(&u.b[i], ea, nb, regs);
375 if (!err)
376 *dest = u.ul;
377 return err;
378 }
379
380 /*
381 * Read memory at address ea for nb bytes, return 0 for success
382 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
383 * If nb < sizeof(long), the result is right-justified on BE systems.
384 */
read_mem(unsigned long * dest,unsigned long ea,int nb,struct pt_regs * regs)385 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
386 struct pt_regs *regs)
387 {
388 if (!address_ok(regs, ea, nb))
389 return -EFAULT;
390 if ((ea & (nb - 1)) == 0)
391 return read_mem_aligned(dest, ea, nb, regs);
392 return read_mem_unaligned(dest, ea, nb, regs);
393 }
394 NOKPROBE_SYMBOL(read_mem);
395
write_mem_aligned(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)396 static nokprobe_inline int write_mem_aligned(unsigned long val,
397 unsigned long ea, int nb,
398 struct pt_regs *regs)
399 {
400 int err = 0;
401
402 switch (nb) {
403 case 1:
404 err = __put_user(val, (unsigned char __user *) ea);
405 break;
406 case 2:
407 err = __put_user(val, (unsigned short __user *) ea);
408 break;
409 case 4:
410 err = __put_user(val, (unsigned int __user *) ea);
411 break;
412 #ifdef __powerpc64__
413 case 8:
414 err = __put_user(val, (unsigned long __user *) ea);
415 break;
416 #endif
417 }
418 if (err)
419 regs->dar = ea;
420 return err;
421 }
422
423 /*
424 * Copy from a buffer to userspace, using the largest possible
425 * aligned accesses, up to sizeof(long).
426 */
copy_mem_out(u8 * dest,unsigned long ea,int nb,struct pt_regs * regs)427 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
428 struct pt_regs *regs)
429 {
430 int err = 0;
431 int c;
432
433 for (; nb > 0; nb -= c) {
434 c = max_align(ea);
435 if (c > nb)
436 c = max_align(nb);
437 switch (c) {
438 case 1:
439 err = __put_user(*dest, (unsigned char __user *) ea);
440 break;
441 case 2:
442 err = __put_user(*(u16 *)dest,
443 (unsigned short __user *) ea);
444 break;
445 case 4:
446 err = __put_user(*(u32 *)dest,
447 (unsigned int __user *) ea);
448 break;
449 #ifdef __powerpc64__
450 case 8:
451 err = __put_user(*(unsigned long *)dest,
452 (unsigned long __user *) ea);
453 break;
454 #endif
455 }
456 if (err) {
457 regs->dar = ea;
458 return err;
459 }
460 dest += c;
461 ea += c;
462 }
463 return 0;
464 }
465
write_mem_unaligned(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)466 static nokprobe_inline int write_mem_unaligned(unsigned long val,
467 unsigned long ea, int nb,
468 struct pt_regs *regs)
469 {
470 union {
471 unsigned long ul;
472 u8 b[sizeof(unsigned long)];
473 } u;
474 int i;
475
476 u.ul = val;
477 i = IS_BE ? sizeof(unsigned long) - nb : 0;
478 return copy_mem_out(&u.b[i], ea, nb, regs);
479 }
480
481 /*
482 * Write memory at address ea for nb bytes, return 0 for success
483 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
484 */
write_mem(unsigned long val,unsigned long ea,int nb,struct pt_regs * regs)485 static int write_mem(unsigned long val, unsigned long ea, int nb,
486 struct pt_regs *regs)
487 {
488 if (!address_ok(regs, ea, nb))
489 return -EFAULT;
490 if ((ea & (nb - 1)) == 0)
491 return write_mem_aligned(val, ea, nb, regs);
492 return write_mem_unaligned(val, ea, nb, regs);
493 }
494 NOKPROBE_SYMBOL(write_mem);
495
496 #ifdef CONFIG_PPC_FPU
497 /*
498 * These access either the real FP register or the image in the
499 * thread_struct, depending on regs->msr & MSR_FP.
500 */
do_fp_load(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)501 static int do_fp_load(struct instruction_op *op, unsigned long ea,
502 struct pt_regs *regs, bool cross_endian)
503 {
504 int err, rn, nb;
505 union {
506 int i;
507 unsigned int u;
508 float f;
509 double d[2];
510 unsigned long l[2];
511 u8 b[2 * sizeof(double)];
512 } u;
513
514 nb = GETSIZE(op->type);
515 if (nb > sizeof(u))
516 return -EINVAL;
517 if (!address_ok(regs, ea, nb))
518 return -EFAULT;
519 rn = op->reg;
520 err = copy_mem_in(u.b, ea, nb, regs);
521 if (err)
522 return err;
523 if (unlikely(cross_endian)) {
524 do_byte_reverse(u.b, min(nb, 8));
525 if (nb == 16)
526 do_byte_reverse(&u.b[8], 8);
527 }
528 preempt_disable();
529 if (nb == 4) {
530 if (op->type & FPCONV)
531 conv_sp_to_dp(&u.f, &u.d[0]);
532 else if (op->type & SIGNEXT)
533 u.l[0] = u.i;
534 else
535 u.l[0] = u.u;
536 }
537 if (regs->msr & MSR_FP)
538 put_fpr(rn, &u.d[0]);
539 else
540 current->thread.TS_FPR(rn) = u.l[0];
541 if (nb == 16) {
542 /* lfdp */
543 rn |= 1;
544 if (regs->msr & MSR_FP)
545 put_fpr(rn, &u.d[1]);
546 else
547 current->thread.TS_FPR(rn) = u.l[1];
548 }
549 preempt_enable();
550 return 0;
551 }
552 NOKPROBE_SYMBOL(do_fp_load);
553
do_fp_store(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)554 static int do_fp_store(struct instruction_op *op, unsigned long ea,
555 struct pt_regs *regs, bool cross_endian)
556 {
557 int rn, nb;
558 union {
559 unsigned int u;
560 float f;
561 double d[2];
562 unsigned long l[2];
563 u8 b[2 * sizeof(double)];
564 } u;
565
566 nb = GETSIZE(op->type);
567 if (nb > sizeof(u))
568 return -EINVAL;
569 if (!address_ok(regs, ea, nb))
570 return -EFAULT;
571 rn = op->reg;
572 preempt_disable();
573 if (regs->msr & MSR_FP)
574 get_fpr(rn, &u.d[0]);
575 else
576 u.l[0] = current->thread.TS_FPR(rn);
577 if (nb == 4) {
578 if (op->type & FPCONV)
579 conv_dp_to_sp(&u.d[0], &u.f);
580 else
581 u.u = u.l[0];
582 }
583 if (nb == 16) {
584 rn |= 1;
585 if (regs->msr & MSR_FP)
586 get_fpr(rn, &u.d[1]);
587 else
588 u.l[1] = current->thread.TS_FPR(rn);
589 }
590 preempt_enable();
591 if (unlikely(cross_endian)) {
592 do_byte_reverse(u.b, min(nb, 8));
593 if (nb == 16)
594 do_byte_reverse(&u.b[8], 8);
595 }
596 return copy_mem_out(u.b, ea, nb, regs);
597 }
598 NOKPROBE_SYMBOL(do_fp_store);
599 #endif
600
601 #ifdef CONFIG_ALTIVEC
602 /* For Altivec/VMX, no need to worry about alignment */
do_vec_load(int rn,unsigned long ea,int size,struct pt_regs * regs,bool cross_endian)603 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
604 int size, struct pt_regs *regs,
605 bool cross_endian)
606 {
607 int err;
608 union {
609 __vector128 v;
610 u8 b[sizeof(__vector128)];
611 } u = {};
612
613 if (size > sizeof(u))
614 return -EINVAL;
615
616 if (!address_ok(regs, ea & ~0xfUL, 16))
617 return -EFAULT;
618 /* align to multiple of size */
619 ea &= ~(size - 1);
620 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
621 if (err)
622 return err;
623 if (unlikely(cross_endian))
624 do_byte_reverse(&u.b[ea & 0xf], size);
625 preempt_disable();
626 if (regs->msr & MSR_VEC)
627 put_vr(rn, &u.v);
628 else
629 current->thread.vr_state.vr[rn] = u.v;
630 preempt_enable();
631 return 0;
632 }
633
do_vec_store(int rn,unsigned long ea,int size,struct pt_regs * regs,bool cross_endian)634 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
635 int size, struct pt_regs *regs,
636 bool cross_endian)
637 {
638 union {
639 __vector128 v;
640 u8 b[sizeof(__vector128)];
641 } u;
642
643 if (size > sizeof(u))
644 return -EINVAL;
645
646 if (!address_ok(regs, ea & ~0xfUL, 16))
647 return -EFAULT;
648 /* align to multiple of size */
649 ea &= ~(size - 1);
650
651 preempt_disable();
652 if (regs->msr & MSR_VEC)
653 get_vr(rn, &u.v);
654 else
655 u.v = current->thread.vr_state.vr[rn];
656 preempt_enable();
657 if (unlikely(cross_endian))
658 do_byte_reverse(&u.b[ea & 0xf], size);
659 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
660 }
661 #endif /* CONFIG_ALTIVEC */
662
663 #ifdef __powerpc64__
emulate_lq(struct pt_regs * regs,unsigned long ea,int reg,bool cross_endian)664 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
665 int reg, bool cross_endian)
666 {
667 int err;
668
669 if (!address_ok(regs, ea, 16))
670 return -EFAULT;
671 /* if aligned, should be atomic */
672 if ((ea & 0xf) == 0) {
673 err = do_lq(ea, ®s->gpr[reg]);
674 } else {
675 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
676 if (!err)
677 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
678 }
679 if (!err && unlikely(cross_endian))
680 do_byte_reverse(®s->gpr[reg], 16);
681 return err;
682 }
683
emulate_stq(struct pt_regs * regs,unsigned long ea,int reg,bool cross_endian)684 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
685 int reg, bool cross_endian)
686 {
687 int err;
688 unsigned long vals[2];
689
690 if (!address_ok(regs, ea, 16))
691 return -EFAULT;
692 vals[0] = regs->gpr[reg];
693 vals[1] = regs->gpr[reg + 1];
694 if (unlikely(cross_endian))
695 do_byte_reverse(vals, 16);
696
697 /* if aligned, should be atomic */
698 if ((ea & 0xf) == 0)
699 return do_stq(ea, vals[0], vals[1]);
700
701 err = write_mem(vals[IS_LE], ea, 8, regs);
702 if (!err)
703 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
704 return err;
705 }
706 #endif /* __powerpc64 */
707
708 #ifdef CONFIG_VSX
emulate_vsx_load(struct instruction_op * op,union vsx_reg * reg,const void * mem,bool rev)709 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
710 const void *mem, bool rev)
711 {
712 int size, read_size;
713 int i, j;
714 const unsigned int *wp;
715 const unsigned short *hp;
716 const unsigned char *bp;
717
718 size = GETSIZE(op->type);
719 reg->d[0] = reg->d[1] = 0;
720
721 switch (op->element_size) {
722 case 16:
723 /* whole vector; lxv[x] or lxvl[l] */
724 if (size == 0)
725 break;
726 memcpy(reg, mem, size);
727 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
728 rev = !rev;
729 if (rev)
730 do_byte_reverse(reg, 16);
731 break;
732 case 8:
733 /* scalar loads, lxvd2x, lxvdsx */
734 read_size = (size >= 8) ? 8 : size;
735 i = IS_LE ? 8 : 8 - read_size;
736 memcpy(®->b[i], mem, read_size);
737 if (rev)
738 do_byte_reverse(®->b[i], 8);
739 if (size < 8) {
740 if (op->type & SIGNEXT) {
741 /* size == 4 is the only case here */
742 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
743 } else if (op->vsx_flags & VSX_FPCONV) {
744 preempt_disable();
745 conv_sp_to_dp(®->fp[1 + IS_LE],
746 ®->dp[IS_LE]);
747 preempt_enable();
748 }
749 } else {
750 if (size == 16) {
751 unsigned long v = *(unsigned long *)(mem + 8);
752 reg->d[IS_BE] = !rev ? v : byterev_8(v);
753 } else if (op->vsx_flags & VSX_SPLAT)
754 reg->d[IS_BE] = reg->d[IS_LE];
755 }
756 break;
757 case 4:
758 /* lxvw4x, lxvwsx */
759 wp = mem;
760 for (j = 0; j < size / 4; ++j) {
761 i = IS_LE ? 3 - j : j;
762 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
763 }
764 if (op->vsx_flags & VSX_SPLAT) {
765 u32 val = reg->w[IS_LE ? 3 : 0];
766 for (; j < 4; ++j) {
767 i = IS_LE ? 3 - j : j;
768 reg->w[i] = val;
769 }
770 }
771 break;
772 case 2:
773 /* lxvh8x */
774 hp = mem;
775 for (j = 0; j < size / 2; ++j) {
776 i = IS_LE ? 7 - j : j;
777 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
778 }
779 break;
780 case 1:
781 /* lxvb16x */
782 bp = mem;
783 for (j = 0; j < size; ++j) {
784 i = IS_LE ? 15 - j : j;
785 reg->b[i] = *bp++;
786 }
787 break;
788 }
789 }
790 EXPORT_SYMBOL_GPL(emulate_vsx_load);
791 NOKPROBE_SYMBOL(emulate_vsx_load);
792
emulate_vsx_store(struct instruction_op * op,const union vsx_reg * reg,void * mem,bool rev)793 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
794 void *mem, bool rev)
795 {
796 int size, write_size;
797 int i, j;
798 union vsx_reg buf;
799 unsigned int *wp;
800 unsigned short *hp;
801 unsigned char *bp;
802
803 size = GETSIZE(op->type);
804
805 switch (op->element_size) {
806 case 16:
807 /* stxv, stxvx, stxvl, stxvll */
808 if (size == 0)
809 break;
810 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
811 rev = !rev;
812 if (rev) {
813 /* reverse 16 bytes */
814 buf.d[0] = byterev_8(reg->d[1]);
815 buf.d[1] = byterev_8(reg->d[0]);
816 reg = &buf;
817 }
818 memcpy(mem, reg, size);
819 break;
820 case 8:
821 /* scalar stores, stxvd2x */
822 write_size = (size >= 8) ? 8 : size;
823 i = IS_LE ? 8 : 8 - write_size;
824 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
825 buf.d[0] = buf.d[1] = 0;
826 preempt_disable();
827 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
828 preempt_enable();
829 reg = &buf;
830 }
831 memcpy(mem, ®->b[i], write_size);
832 if (size == 16)
833 memcpy(mem + 8, ®->d[IS_BE], 8);
834 if (unlikely(rev)) {
835 do_byte_reverse(mem, write_size);
836 if (size == 16)
837 do_byte_reverse(mem + 8, 8);
838 }
839 break;
840 case 4:
841 /* stxvw4x */
842 wp = mem;
843 for (j = 0; j < size / 4; ++j) {
844 i = IS_LE ? 3 - j : j;
845 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
846 }
847 break;
848 case 2:
849 /* stxvh8x */
850 hp = mem;
851 for (j = 0; j < size / 2; ++j) {
852 i = IS_LE ? 7 - j : j;
853 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
854 }
855 break;
856 case 1:
857 /* stvxb16x */
858 bp = mem;
859 for (j = 0; j < size; ++j) {
860 i = IS_LE ? 15 - j : j;
861 *bp++ = reg->b[i];
862 }
863 break;
864 }
865 }
866 EXPORT_SYMBOL_GPL(emulate_vsx_store);
867 NOKPROBE_SYMBOL(emulate_vsx_store);
868
do_vsx_load(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)869 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
870 unsigned long ea, struct pt_regs *regs,
871 bool cross_endian)
872 {
873 int reg = op->reg;
874 u8 mem[16];
875 union vsx_reg buf;
876 int size = GETSIZE(op->type);
877
878 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
879 return -EFAULT;
880
881 emulate_vsx_load(op, &buf, mem, cross_endian);
882 preempt_disable();
883 if (reg < 32) {
884 /* FP regs + extensions */
885 if (regs->msr & MSR_FP) {
886 load_vsrn(reg, &buf);
887 } else {
888 current->thread.fp_state.fpr[reg][0] = buf.d[0];
889 current->thread.fp_state.fpr[reg][1] = buf.d[1];
890 }
891 } else {
892 if (regs->msr & MSR_VEC)
893 load_vsrn(reg, &buf);
894 else
895 current->thread.vr_state.vr[reg - 32] = buf.v;
896 }
897 preempt_enable();
898 return 0;
899 }
900
do_vsx_store(struct instruction_op * op,unsigned long ea,struct pt_regs * regs,bool cross_endian)901 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
902 unsigned long ea, struct pt_regs *regs,
903 bool cross_endian)
904 {
905 int reg = op->reg;
906 u8 mem[16];
907 union vsx_reg buf;
908 int size = GETSIZE(op->type);
909
910 if (!address_ok(regs, ea, size))
911 return -EFAULT;
912
913 preempt_disable();
914 if (reg < 32) {
915 /* FP regs + extensions */
916 if (regs->msr & MSR_FP) {
917 store_vsrn(reg, &buf);
918 } else {
919 buf.d[0] = current->thread.fp_state.fpr[reg][0];
920 buf.d[1] = current->thread.fp_state.fpr[reg][1];
921 }
922 } else {
923 if (regs->msr & MSR_VEC)
924 store_vsrn(reg, &buf);
925 else
926 buf.v = current->thread.vr_state.vr[reg - 32];
927 }
928 preempt_enable();
929 emulate_vsx_store(op, &buf, mem, cross_endian);
930 return copy_mem_out(mem, ea, size, regs);
931 }
932 #endif /* CONFIG_VSX */
933
emulate_dcbz(unsigned long ea,struct pt_regs * regs)934 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
935 {
936 int err;
937 unsigned long i, size;
938
939 #ifdef __powerpc64__
940 size = ppc64_caches.l1d.block_size;
941 if (!(regs->msr & MSR_64BIT))
942 ea &= 0xffffffffUL;
943 #else
944 size = L1_CACHE_BYTES;
945 #endif
946 ea &= ~(size - 1);
947 if (!address_ok(regs, ea, size))
948 return -EFAULT;
949 for (i = 0; i < size; i += sizeof(long)) {
950 err = __put_user(0, (unsigned long __user *) (ea + i));
951 if (err) {
952 regs->dar = ea;
953 return err;
954 }
955 }
956 return 0;
957 }
958 NOKPROBE_SYMBOL(emulate_dcbz);
959
960 #define __put_user_asmx(x, addr, err, op, cr) \
961 __asm__ __volatile__( \
962 ".machine push\n" \
963 ".machine power8\n" \
964 "1: " op " %2,0,%3\n" \
965 ".machine pop\n" \
966 " mfcr %1\n" \
967 "2:\n" \
968 ".section .fixup,\"ax\"\n" \
969 "3: li %0,%4\n" \
970 " b 2b\n" \
971 ".previous\n" \
972 EX_TABLE(1b, 3b) \
973 : "=r" (err), "=r" (cr) \
974 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
975
976 #define __get_user_asmx(x, addr, err, op) \
977 __asm__ __volatile__( \
978 ".machine push\n" \
979 ".machine power8\n" \
980 "1: "op" %1,0,%2\n" \
981 ".machine pop\n" \
982 "2:\n" \
983 ".section .fixup,\"ax\"\n" \
984 "3: li %0,%3\n" \
985 " b 2b\n" \
986 ".previous\n" \
987 EX_TABLE(1b, 3b) \
988 : "=r" (err), "=r" (x) \
989 : "r" (addr), "i" (-EFAULT), "0" (err))
990
991 #define __cacheop_user_asmx(addr, err, op) \
992 __asm__ __volatile__( \
993 "1: "op" 0,%1\n" \
994 "2:\n" \
995 ".section .fixup,\"ax\"\n" \
996 "3: li %0,%3\n" \
997 " b 2b\n" \
998 ".previous\n" \
999 EX_TABLE(1b, 3b) \
1000 : "=r" (err) \
1001 : "r" (addr), "i" (-EFAULT), "0" (err))
1002
set_cr0(const struct pt_regs * regs,struct instruction_op * op)1003 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1004 struct instruction_op *op)
1005 {
1006 long val = op->val;
1007
1008 op->type |= SETCC;
1009 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1010 #ifdef __powerpc64__
1011 if (!(regs->msr & MSR_64BIT))
1012 val = (int) val;
1013 #endif
1014 if (val < 0)
1015 op->ccval |= 0x80000000;
1016 else if (val > 0)
1017 op->ccval |= 0x40000000;
1018 else
1019 op->ccval |= 0x20000000;
1020 }
1021
set_ca32(struct instruction_op * op,bool val)1022 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1023 {
1024 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1025 if (val)
1026 op->xerval |= XER_CA32;
1027 else
1028 op->xerval &= ~XER_CA32;
1029 }
1030 }
1031
add_with_carry(const struct pt_regs * regs,struct instruction_op * op,int rd,unsigned long val1,unsigned long val2,unsigned long carry_in)1032 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1033 struct instruction_op *op, int rd,
1034 unsigned long val1, unsigned long val2,
1035 unsigned long carry_in)
1036 {
1037 unsigned long val = val1 + val2;
1038
1039 if (carry_in)
1040 ++val;
1041 op->type = COMPUTE + SETREG + SETXER;
1042 op->reg = rd;
1043 op->val = val;
1044 #ifdef __powerpc64__
1045 if (!(regs->msr & MSR_64BIT)) {
1046 val = (unsigned int) val;
1047 val1 = (unsigned int) val1;
1048 }
1049 #endif
1050 op->xerval = regs->xer;
1051 if (val < val1 || (carry_in && val == val1))
1052 op->xerval |= XER_CA;
1053 else
1054 op->xerval &= ~XER_CA;
1055
1056 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1057 (carry_in && (unsigned int)val == (unsigned int)val1));
1058 }
1059
do_cmp_signed(const struct pt_regs * regs,struct instruction_op * op,long v1,long v2,int crfld)1060 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1061 struct instruction_op *op,
1062 long v1, long v2, int crfld)
1063 {
1064 unsigned int crval, shift;
1065
1066 op->type = COMPUTE + SETCC;
1067 crval = (regs->xer >> 31) & 1; /* get SO bit */
1068 if (v1 < v2)
1069 crval |= 8;
1070 else if (v1 > v2)
1071 crval |= 4;
1072 else
1073 crval |= 2;
1074 shift = (7 - crfld) * 4;
1075 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1076 }
1077
do_cmp_unsigned(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2,int crfld)1078 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1079 struct instruction_op *op,
1080 unsigned long v1,
1081 unsigned long v2, int crfld)
1082 {
1083 unsigned int crval, shift;
1084
1085 op->type = COMPUTE + SETCC;
1086 crval = (regs->xer >> 31) & 1; /* get SO bit */
1087 if (v1 < v2)
1088 crval |= 8;
1089 else if (v1 > v2)
1090 crval |= 4;
1091 else
1092 crval |= 2;
1093 shift = (7 - crfld) * 4;
1094 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1095 }
1096
do_cmpb(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2)1097 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1098 struct instruction_op *op,
1099 unsigned long v1, unsigned long v2)
1100 {
1101 unsigned long long out_val, mask;
1102 int i;
1103
1104 out_val = 0;
1105 for (i = 0; i < 8; i++) {
1106 mask = 0xffUL << (i * 8);
1107 if ((v1 & mask) == (v2 & mask))
1108 out_val |= mask;
1109 }
1110 op->val = out_val;
1111 }
1112
1113 /*
1114 * The size parameter is used to adjust the equivalent popcnt instruction.
1115 * popcntb = 8, popcntw = 32, popcntd = 64
1116 */
do_popcnt(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,int size)1117 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1118 struct instruction_op *op,
1119 unsigned long v1, int size)
1120 {
1121 unsigned long long out = v1;
1122
1123 out -= (out >> 1) & 0x5555555555555555ULL;
1124 out = (0x3333333333333333ULL & out) +
1125 (0x3333333333333333ULL & (out >> 2));
1126 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1127
1128 if (size == 8) { /* popcntb */
1129 op->val = out;
1130 return;
1131 }
1132 out += out >> 8;
1133 out += out >> 16;
1134 if (size == 32) { /* popcntw */
1135 op->val = out & 0x0000003f0000003fULL;
1136 return;
1137 }
1138
1139 out = (out + (out >> 32)) & 0x7f;
1140 op->val = out; /* popcntd */
1141 }
1142
1143 #ifdef CONFIG_PPC64
do_bpermd(const struct pt_regs * regs,struct instruction_op * op,unsigned long v1,unsigned long v2)1144 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1145 struct instruction_op *op,
1146 unsigned long v1, unsigned long v2)
1147 {
1148 unsigned char perm, idx;
1149 unsigned int i;
1150
1151 perm = 0;
1152 for (i = 0; i < 8; i++) {
1153 idx = (v1 >> (i * 8)) & 0xff;
1154 if (idx < 64)
1155 if (v2 & PPC_BIT(idx))
1156 perm |= 1 << i;
1157 }
1158 op->val = perm;
1159 }
1160 #endif /* CONFIG_PPC64 */
1161 /*
1162 * The size parameter adjusts the equivalent prty instruction.
1163 * prtyw = 32, prtyd = 64
1164 */
do_prty(const struct pt_regs * regs,struct instruction_op * op,unsigned long v,int size)1165 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1166 struct instruction_op *op,
1167 unsigned long v, int size)
1168 {
1169 unsigned long long res = v ^ (v >> 8);
1170
1171 res ^= res >> 16;
1172 if (size == 32) { /* prtyw */
1173 op->val = res & 0x0000000100000001ULL;
1174 return;
1175 }
1176
1177 res ^= res >> 32;
1178 op->val = res & 1; /*prtyd */
1179 }
1180
trap_compare(long v1,long v2)1181 static nokprobe_inline int trap_compare(long v1, long v2)
1182 {
1183 int ret = 0;
1184
1185 if (v1 < v2)
1186 ret |= 0x10;
1187 else if (v1 > v2)
1188 ret |= 0x08;
1189 else
1190 ret |= 0x04;
1191 if ((unsigned long)v1 < (unsigned long)v2)
1192 ret |= 0x02;
1193 else if ((unsigned long)v1 > (unsigned long)v2)
1194 ret |= 0x01;
1195 return ret;
1196 }
1197
1198 /*
1199 * Elements of 32-bit rotate and mask instructions.
1200 */
1201 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1202 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1203 #ifdef __powerpc64__
1204 #define MASK64_L(mb) (~0UL >> (mb))
1205 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1206 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1207 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1208 #else
1209 #define DATA32(x) (x)
1210 #endif
1211 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1212
1213 /*
1214 * Decode an instruction, and return information about it in *op
1215 * without changing *regs.
1216 * Integer arithmetic and logical instructions, branches, and barrier
1217 * instructions can be emulated just using the information in *op.
1218 *
1219 * Return value is 1 if the instruction can be emulated just by
1220 * updating *regs with the information in *op, -1 if we need the
1221 * GPRs but *regs doesn't contain the full register set, or 0
1222 * otherwise.
1223 */
analyse_instr(struct instruction_op * op,const struct pt_regs * regs,struct ppc_inst instr)1224 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1225 struct ppc_inst instr)
1226 {
1227 #ifdef CONFIG_PPC64
1228 unsigned int suffixopcode, prefixtype, prefix_r;
1229 #endif
1230 unsigned int opcode, ra, rb, rc, rd, spr, u;
1231 unsigned long int imm;
1232 unsigned long int val, val2;
1233 unsigned int mb, me, sh;
1234 unsigned int word, suffix;
1235 long ival;
1236
1237 word = ppc_inst_val(instr);
1238 suffix = ppc_inst_suffix(instr);
1239
1240 op->type = COMPUTE;
1241
1242 opcode = ppc_inst_primary_opcode(instr);
1243 switch (opcode) {
1244 case 16: /* bc */
1245 op->type = BRANCH;
1246 imm = (signed short)(word & 0xfffc);
1247 if ((word & 2) == 0)
1248 imm += regs->nip;
1249 op->val = truncate_if_32bit(regs->msr, imm);
1250 if (word & 1)
1251 op->type |= SETLK;
1252 if (branch_taken(word, regs, op))
1253 op->type |= BRTAKEN;
1254 return 1;
1255 #ifdef CONFIG_PPC64
1256 case 17: /* sc */
1257 if ((word & 0xfe2) == 2)
1258 op->type = SYSCALL;
1259 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1260 (word & 0xfe3) == 1) { /* scv */
1261 op->type = SYSCALL_VECTORED_0;
1262 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1263 goto unknown_opcode;
1264 } else
1265 op->type = UNKNOWN;
1266 return 0;
1267 #endif
1268 case 18: /* b */
1269 op->type = BRANCH | BRTAKEN;
1270 imm = word & 0x03fffffc;
1271 if (imm & 0x02000000)
1272 imm -= 0x04000000;
1273 if ((word & 2) == 0)
1274 imm += regs->nip;
1275 op->val = truncate_if_32bit(regs->msr, imm);
1276 if (word & 1)
1277 op->type |= SETLK;
1278 return 1;
1279 case 19:
1280 switch ((word >> 1) & 0x3ff) {
1281 case 0: /* mcrf */
1282 op->type = COMPUTE + SETCC;
1283 rd = 7 - ((word >> 23) & 0x7);
1284 ra = 7 - ((word >> 18) & 0x7);
1285 rd *= 4;
1286 ra *= 4;
1287 val = (regs->ccr >> ra) & 0xf;
1288 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1289 return 1;
1290
1291 case 16: /* bclr */
1292 case 528: /* bcctr */
1293 op->type = BRANCH;
1294 imm = (word & 0x400)? regs->ctr: regs->link;
1295 op->val = truncate_if_32bit(regs->msr, imm);
1296 if (word & 1)
1297 op->type |= SETLK;
1298 if (branch_taken(word, regs, op))
1299 op->type |= BRTAKEN;
1300 return 1;
1301
1302 case 18: /* rfid, scary */
1303 if (regs->msr & MSR_PR)
1304 goto priv;
1305 op->type = RFI;
1306 return 0;
1307
1308 case 150: /* isync */
1309 op->type = BARRIER | BARRIER_ISYNC;
1310 return 1;
1311
1312 case 33: /* crnor */
1313 case 129: /* crandc */
1314 case 193: /* crxor */
1315 case 225: /* crnand */
1316 case 257: /* crand */
1317 case 289: /* creqv */
1318 case 417: /* crorc */
1319 case 449: /* cror */
1320 op->type = COMPUTE + SETCC;
1321 ra = (word >> 16) & 0x1f;
1322 rb = (word >> 11) & 0x1f;
1323 rd = (word >> 21) & 0x1f;
1324 ra = (regs->ccr >> (31 - ra)) & 1;
1325 rb = (regs->ccr >> (31 - rb)) & 1;
1326 val = (word >> (6 + ra * 2 + rb)) & 1;
1327 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1328 (val << (31 - rd));
1329 return 1;
1330 }
1331 break;
1332 case 31:
1333 switch ((word >> 1) & 0x3ff) {
1334 case 598: /* sync */
1335 op->type = BARRIER + BARRIER_SYNC;
1336 #ifdef __powerpc64__
1337 switch ((word >> 21) & 3) {
1338 case 1: /* lwsync */
1339 op->type = BARRIER + BARRIER_LWSYNC;
1340 break;
1341 case 2: /* ptesync */
1342 op->type = BARRIER + BARRIER_PTESYNC;
1343 break;
1344 }
1345 #endif
1346 return 1;
1347
1348 case 854: /* eieio */
1349 op->type = BARRIER + BARRIER_EIEIO;
1350 return 1;
1351 }
1352 break;
1353 }
1354
1355 /* Following cases refer to regs->gpr[], so we need all regs */
1356 if (!FULL_REGS(regs))
1357 return -1;
1358
1359 rd = (word >> 21) & 0x1f;
1360 ra = (word >> 16) & 0x1f;
1361 rb = (word >> 11) & 0x1f;
1362 rc = (word >> 6) & 0x1f;
1363
1364 switch (opcode) {
1365 #ifdef __powerpc64__
1366 case 1:
1367 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1368 goto unknown_opcode;
1369
1370 prefix_r = GET_PREFIX_R(word);
1371 ra = GET_PREFIX_RA(suffix);
1372 rd = (suffix >> 21) & 0x1f;
1373 op->reg = rd;
1374 op->val = regs->gpr[rd];
1375 suffixopcode = get_op(suffix);
1376 prefixtype = (word >> 24) & 0x3;
1377 switch (prefixtype) {
1378 case 2:
1379 if (prefix_r && ra)
1380 return 0;
1381 switch (suffixopcode) {
1382 case 14: /* paddi */
1383 op->type = COMPUTE | PREFIXED;
1384 op->val = mlsd_8lsd_ea(word, suffix, regs);
1385 goto compute_done;
1386 }
1387 }
1388 break;
1389 case 2: /* tdi */
1390 if (rd & trap_compare(regs->gpr[ra], (short) word))
1391 goto trap;
1392 return 1;
1393 #endif
1394 case 3: /* twi */
1395 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1396 goto trap;
1397 return 1;
1398
1399 #ifdef __powerpc64__
1400 case 4:
1401 /*
1402 * There are very many instructions with this primary opcode
1403 * introduced in the ISA as early as v2.03. However, the ones
1404 * we currently emulate were all introduced with ISA 3.0
1405 */
1406 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1407 goto unknown_opcode;
1408
1409 switch (word & 0x3f) {
1410 case 48: /* maddhd */
1411 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1412 "=r" (op->val) : "r" (regs->gpr[ra]),
1413 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1414 goto compute_done;
1415
1416 case 49: /* maddhdu */
1417 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1418 "=r" (op->val) : "r" (regs->gpr[ra]),
1419 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1420 goto compute_done;
1421
1422 case 51: /* maddld */
1423 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1424 "=r" (op->val) : "r" (regs->gpr[ra]),
1425 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1426 goto compute_done;
1427 }
1428
1429 /*
1430 * There are other instructions from ISA 3.0 with the same
1431 * primary opcode which do not have emulation support yet.
1432 */
1433 goto unknown_opcode;
1434 #endif
1435
1436 case 7: /* mulli */
1437 op->val = regs->gpr[ra] * (short) word;
1438 goto compute_done;
1439
1440 case 8: /* subfic */
1441 imm = (short) word;
1442 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1443 return 1;
1444
1445 case 10: /* cmpli */
1446 imm = (unsigned short) word;
1447 val = regs->gpr[ra];
1448 #ifdef __powerpc64__
1449 if ((rd & 1) == 0)
1450 val = (unsigned int) val;
1451 #endif
1452 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1453 return 1;
1454
1455 case 11: /* cmpi */
1456 imm = (short) word;
1457 val = regs->gpr[ra];
1458 #ifdef __powerpc64__
1459 if ((rd & 1) == 0)
1460 val = (int) val;
1461 #endif
1462 do_cmp_signed(regs, op, val, imm, rd >> 2);
1463 return 1;
1464
1465 case 12: /* addic */
1466 imm = (short) word;
1467 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1468 return 1;
1469
1470 case 13: /* addic. */
1471 imm = (short) word;
1472 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1473 set_cr0(regs, op);
1474 return 1;
1475
1476 case 14: /* addi */
1477 imm = (short) word;
1478 if (ra)
1479 imm += regs->gpr[ra];
1480 op->val = imm;
1481 goto compute_done;
1482
1483 case 15: /* addis */
1484 imm = ((short) word) << 16;
1485 if (ra)
1486 imm += regs->gpr[ra];
1487 op->val = imm;
1488 goto compute_done;
1489
1490 case 19:
1491 if (((word >> 1) & 0x1f) == 2) {
1492 /* addpcis */
1493 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1494 goto unknown_opcode;
1495 imm = (short) (word & 0xffc1); /* d0 + d2 fields */
1496 imm |= (word >> 15) & 0x3e; /* d1 field */
1497 op->val = regs->nip + (imm << 16) + 4;
1498 goto compute_done;
1499 }
1500 op->type = UNKNOWN;
1501 return 0;
1502
1503 case 20: /* rlwimi */
1504 mb = (word >> 6) & 0x1f;
1505 me = (word >> 1) & 0x1f;
1506 val = DATA32(regs->gpr[rd]);
1507 imm = MASK32(mb, me);
1508 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1509 goto logical_done;
1510
1511 case 21: /* rlwinm */
1512 mb = (word >> 6) & 0x1f;
1513 me = (word >> 1) & 0x1f;
1514 val = DATA32(regs->gpr[rd]);
1515 op->val = ROTATE(val, rb) & MASK32(mb, me);
1516 goto logical_done;
1517
1518 case 23: /* rlwnm */
1519 mb = (word >> 6) & 0x1f;
1520 me = (word >> 1) & 0x1f;
1521 rb = regs->gpr[rb] & 0x1f;
1522 val = DATA32(regs->gpr[rd]);
1523 op->val = ROTATE(val, rb) & MASK32(mb, me);
1524 goto logical_done;
1525
1526 case 24: /* ori */
1527 op->val = regs->gpr[rd] | (unsigned short) word;
1528 goto logical_done_nocc;
1529
1530 case 25: /* oris */
1531 imm = (unsigned short) word;
1532 op->val = regs->gpr[rd] | (imm << 16);
1533 goto logical_done_nocc;
1534
1535 case 26: /* xori */
1536 op->val = regs->gpr[rd] ^ (unsigned short) word;
1537 goto logical_done_nocc;
1538
1539 case 27: /* xoris */
1540 imm = (unsigned short) word;
1541 op->val = regs->gpr[rd] ^ (imm << 16);
1542 goto logical_done_nocc;
1543
1544 case 28: /* andi. */
1545 op->val = regs->gpr[rd] & (unsigned short) word;
1546 set_cr0(regs, op);
1547 goto logical_done_nocc;
1548
1549 case 29: /* andis. */
1550 imm = (unsigned short) word;
1551 op->val = regs->gpr[rd] & (imm << 16);
1552 set_cr0(regs, op);
1553 goto logical_done_nocc;
1554
1555 #ifdef __powerpc64__
1556 case 30: /* rld* */
1557 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1558 val = regs->gpr[rd];
1559 if ((word & 0x10) == 0) {
1560 sh = rb | ((word & 2) << 4);
1561 val = ROTATE(val, sh);
1562 switch ((word >> 2) & 3) {
1563 case 0: /* rldicl */
1564 val &= MASK64_L(mb);
1565 break;
1566 case 1: /* rldicr */
1567 val &= MASK64_R(mb);
1568 break;
1569 case 2: /* rldic */
1570 val &= MASK64(mb, 63 - sh);
1571 break;
1572 case 3: /* rldimi */
1573 imm = MASK64(mb, 63 - sh);
1574 val = (regs->gpr[ra] & ~imm) |
1575 (val & imm);
1576 }
1577 op->val = val;
1578 goto logical_done;
1579 } else {
1580 sh = regs->gpr[rb] & 0x3f;
1581 val = ROTATE(val, sh);
1582 switch ((word >> 1) & 7) {
1583 case 0: /* rldcl */
1584 op->val = val & MASK64_L(mb);
1585 goto logical_done;
1586 case 1: /* rldcr */
1587 op->val = val & MASK64_R(mb);
1588 goto logical_done;
1589 }
1590 }
1591 #endif
1592 op->type = UNKNOWN; /* illegal instruction */
1593 return 0;
1594
1595 case 31:
1596 /* isel occupies 32 minor opcodes */
1597 if (((word >> 1) & 0x1f) == 15) {
1598 mb = (word >> 6) & 0x1f; /* bc field */
1599 val = (regs->ccr >> (31 - mb)) & 1;
1600 val2 = (ra) ? regs->gpr[ra] : 0;
1601
1602 op->val = (val) ? val2 : regs->gpr[rb];
1603 goto compute_done;
1604 }
1605
1606 switch ((word >> 1) & 0x3ff) {
1607 case 4: /* tw */
1608 if (rd == 0x1f ||
1609 (rd & trap_compare((int)regs->gpr[ra],
1610 (int)regs->gpr[rb])))
1611 goto trap;
1612 return 1;
1613 #ifdef __powerpc64__
1614 case 68: /* td */
1615 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1616 goto trap;
1617 return 1;
1618 #endif
1619 case 83: /* mfmsr */
1620 if (regs->msr & MSR_PR)
1621 goto priv;
1622 op->type = MFMSR;
1623 op->reg = rd;
1624 return 0;
1625 case 146: /* mtmsr */
1626 if (regs->msr & MSR_PR)
1627 goto priv;
1628 op->type = MTMSR;
1629 op->reg = rd;
1630 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1631 return 0;
1632 #ifdef CONFIG_PPC64
1633 case 178: /* mtmsrd */
1634 if (regs->msr & MSR_PR)
1635 goto priv;
1636 op->type = MTMSR;
1637 op->reg = rd;
1638 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1639 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1640 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1641 op->val = imm;
1642 return 0;
1643 #endif
1644
1645 case 19: /* mfcr */
1646 imm = 0xffffffffUL;
1647 if ((word >> 20) & 1) {
1648 imm = 0xf0000000UL;
1649 for (sh = 0; sh < 8; ++sh) {
1650 if (word & (0x80000 >> sh))
1651 break;
1652 imm >>= 4;
1653 }
1654 }
1655 op->val = regs->ccr & imm;
1656 goto compute_done;
1657
1658 case 144: /* mtcrf */
1659 op->type = COMPUTE + SETCC;
1660 imm = 0xf0000000UL;
1661 val = regs->gpr[rd];
1662 op->ccval = regs->ccr;
1663 for (sh = 0; sh < 8; ++sh) {
1664 if (word & (0x80000 >> sh))
1665 op->ccval = (op->ccval & ~imm) |
1666 (val & imm);
1667 imm >>= 4;
1668 }
1669 return 1;
1670
1671 case 339: /* mfspr */
1672 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1673 op->type = MFSPR;
1674 op->reg = rd;
1675 op->spr = spr;
1676 if (spr == SPRN_XER || spr == SPRN_LR ||
1677 spr == SPRN_CTR)
1678 return 1;
1679 return 0;
1680
1681 case 467: /* mtspr */
1682 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1683 op->type = MTSPR;
1684 op->val = regs->gpr[rd];
1685 op->spr = spr;
1686 if (spr == SPRN_XER || spr == SPRN_LR ||
1687 spr == SPRN_CTR)
1688 return 1;
1689 return 0;
1690
1691 /*
1692 * Compare instructions
1693 */
1694 case 0: /* cmp */
1695 val = regs->gpr[ra];
1696 val2 = regs->gpr[rb];
1697 #ifdef __powerpc64__
1698 if ((rd & 1) == 0) {
1699 /* word (32-bit) compare */
1700 val = (int) val;
1701 val2 = (int) val2;
1702 }
1703 #endif
1704 do_cmp_signed(regs, op, val, val2, rd >> 2);
1705 return 1;
1706
1707 case 32: /* cmpl */
1708 val = regs->gpr[ra];
1709 val2 = regs->gpr[rb];
1710 #ifdef __powerpc64__
1711 if ((rd & 1) == 0) {
1712 /* word (32-bit) compare */
1713 val = (unsigned int) val;
1714 val2 = (unsigned int) val2;
1715 }
1716 #endif
1717 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1718 return 1;
1719
1720 case 508: /* cmpb */
1721 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1722 goto logical_done_nocc;
1723
1724 /*
1725 * Arithmetic instructions
1726 */
1727 case 8: /* subfc */
1728 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1729 regs->gpr[rb], 1);
1730 goto arith_done;
1731 #ifdef __powerpc64__
1732 case 9: /* mulhdu */
1733 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1734 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1735 goto arith_done;
1736 #endif
1737 case 10: /* addc */
1738 add_with_carry(regs, op, rd, regs->gpr[ra],
1739 regs->gpr[rb], 0);
1740 goto arith_done;
1741
1742 case 11: /* mulhwu */
1743 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1744 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1745 goto arith_done;
1746
1747 case 40: /* subf */
1748 op->val = regs->gpr[rb] - regs->gpr[ra];
1749 goto arith_done;
1750 #ifdef __powerpc64__
1751 case 73: /* mulhd */
1752 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1753 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1754 goto arith_done;
1755 #endif
1756 case 75: /* mulhw */
1757 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1758 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1759 goto arith_done;
1760
1761 case 104: /* neg */
1762 op->val = -regs->gpr[ra];
1763 goto arith_done;
1764
1765 case 136: /* subfe */
1766 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1767 regs->gpr[rb], regs->xer & XER_CA);
1768 goto arith_done;
1769
1770 case 138: /* adde */
1771 add_with_carry(regs, op, rd, regs->gpr[ra],
1772 regs->gpr[rb], regs->xer & XER_CA);
1773 goto arith_done;
1774
1775 case 200: /* subfze */
1776 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1777 regs->xer & XER_CA);
1778 goto arith_done;
1779
1780 case 202: /* addze */
1781 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1782 regs->xer & XER_CA);
1783 goto arith_done;
1784
1785 case 232: /* subfme */
1786 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1787 regs->xer & XER_CA);
1788 goto arith_done;
1789 #ifdef __powerpc64__
1790 case 233: /* mulld */
1791 op->val = regs->gpr[ra] * regs->gpr[rb];
1792 goto arith_done;
1793 #endif
1794 case 234: /* addme */
1795 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1796 regs->xer & XER_CA);
1797 goto arith_done;
1798
1799 case 235: /* mullw */
1800 op->val = (long)(int) regs->gpr[ra] *
1801 (int) regs->gpr[rb];
1802
1803 goto arith_done;
1804 #ifdef __powerpc64__
1805 case 265: /* modud */
1806 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1807 goto unknown_opcode;
1808 op->val = regs->gpr[ra] % regs->gpr[rb];
1809 goto compute_done;
1810 #endif
1811 case 266: /* add */
1812 op->val = regs->gpr[ra] + regs->gpr[rb];
1813 goto arith_done;
1814
1815 case 267: /* moduw */
1816 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1817 goto unknown_opcode;
1818 op->val = (unsigned int) regs->gpr[ra] %
1819 (unsigned int) regs->gpr[rb];
1820 goto compute_done;
1821 #ifdef __powerpc64__
1822 case 457: /* divdu */
1823 op->val = regs->gpr[ra] / regs->gpr[rb];
1824 goto arith_done;
1825 #endif
1826 case 459: /* divwu */
1827 op->val = (unsigned int) regs->gpr[ra] /
1828 (unsigned int) regs->gpr[rb];
1829 goto arith_done;
1830 #ifdef __powerpc64__
1831 case 489: /* divd */
1832 op->val = (long int) regs->gpr[ra] /
1833 (long int) regs->gpr[rb];
1834 goto arith_done;
1835 #endif
1836 case 491: /* divw */
1837 op->val = (int) regs->gpr[ra] /
1838 (int) regs->gpr[rb];
1839 goto arith_done;
1840 #ifdef __powerpc64__
1841 case 425: /* divde[.] */
1842 asm volatile(PPC_DIVDE(%0, %1, %2) :
1843 "=r" (op->val) : "r" (regs->gpr[ra]),
1844 "r" (regs->gpr[rb]));
1845 goto arith_done;
1846 case 393: /* divdeu[.] */
1847 asm volatile(PPC_DIVDEU(%0, %1, %2) :
1848 "=r" (op->val) : "r" (regs->gpr[ra]),
1849 "r" (regs->gpr[rb]));
1850 goto arith_done;
1851 #endif
1852 case 755: /* darn */
1853 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1854 goto unknown_opcode;
1855 switch (ra & 0x3) {
1856 case 0:
1857 /* 32-bit conditioned */
1858 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1859 goto compute_done;
1860
1861 case 1:
1862 /* 64-bit conditioned */
1863 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1864 goto compute_done;
1865
1866 case 2:
1867 /* 64-bit raw */
1868 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1869 goto compute_done;
1870 }
1871
1872 goto unknown_opcode;
1873 #ifdef __powerpc64__
1874 case 777: /* modsd */
1875 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1876 goto unknown_opcode;
1877 op->val = (long int) regs->gpr[ra] %
1878 (long int) regs->gpr[rb];
1879 goto compute_done;
1880 #endif
1881 case 779: /* modsw */
1882 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1883 goto unknown_opcode;
1884 op->val = (int) regs->gpr[ra] %
1885 (int) regs->gpr[rb];
1886 goto compute_done;
1887
1888
1889 /*
1890 * Logical instructions
1891 */
1892 case 26: /* cntlzw */
1893 val = (unsigned int) regs->gpr[rd];
1894 op->val = ( val ? __builtin_clz(val) : 32 );
1895 goto logical_done;
1896 #ifdef __powerpc64__
1897 case 58: /* cntlzd */
1898 val = regs->gpr[rd];
1899 op->val = ( val ? __builtin_clzl(val) : 64 );
1900 goto logical_done;
1901 #endif
1902 case 28: /* and */
1903 op->val = regs->gpr[rd] & regs->gpr[rb];
1904 goto logical_done;
1905
1906 case 60: /* andc */
1907 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1908 goto logical_done;
1909
1910 case 122: /* popcntb */
1911 do_popcnt(regs, op, regs->gpr[rd], 8);
1912 goto logical_done_nocc;
1913
1914 case 124: /* nor */
1915 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1916 goto logical_done;
1917
1918 case 154: /* prtyw */
1919 do_prty(regs, op, regs->gpr[rd], 32);
1920 goto logical_done_nocc;
1921
1922 case 186: /* prtyd */
1923 do_prty(regs, op, regs->gpr[rd], 64);
1924 goto logical_done_nocc;
1925 #ifdef CONFIG_PPC64
1926 case 252: /* bpermd */
1927 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1928 goto logical_done_nocc;
1929 #endif
1930 case 284: /* xor */
1931 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1932 goto logical_done;
1933
1934 case 316: /* xor */
1935 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1936 goto logical_done;
1937
1938 case 378: /* popcntw */
1939 do_popcnt(regs, op, regs->gpr[rd], 32);
1940 goto logical_done_nocc;
1941
1942 case 412: /* orc */
1943 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1944 goto logical_done;
1945
1946 case 444: /* or */
1947 op->val = regs->gpr[rd] | regs->gpr[rb];
1948 goto logical_done;
1949
1950 case 476: /* nand */
1951 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1952 goto logical_done;
1953 #ifdef CONFIG_PPC64
1954 case 506: /* popcntd */
1955 do_popcnt(regs, op, regs->gpr[rd], 64);
1956 goto logical_done_nocc;
1957 #endif
1958 case 538: /* cnttzw */
1959 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1960 goto unknown_opcode;
1961 val = (unsigned int) regs->gpr[rd];
1962 op->val = (val ? __builtin_ctz(val) : 32);
1963 goto logical_done;
1964 #ifdef __powerpc64__
1965 case 570: /* cnttzd */
1966 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1967 goto unknown_opcode;
1968 val = regs->gpr[rd];
1969 op->val = (val ? __builtin_ctzl(val) : 64);
1970 goto logical_done;
1971 #endif
1972 case 922: /* extsh */
1973 op->val = (signed short) regs->gpr[rd];
1974 goto logical_done;
1975
1976 case 954: /* extsb */
1977 op->val = (signed char) regs->gpr[rd];
1978 goto logical_done;
1979 #ifdef __powerpc64__
1980 case 986: /* extsw */
1981 op->val = (signed int) regs->gpr[rd];
1982 goto logical_done;
1983 #endif
1984
1985 /*
1986 * Shift instructions
1987 */
1988 case 24: /* slw */
1989 sh = regs->gpr[rb] & 0x3f;
1990 if (sh < 32)
1991 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1992 else
1993 op->val = 0;
1994 goto logical_done;
1995
1996 case 536: /* srw */
1997 sh = regs->gpr[rb] & 0x3f;
1998 if (sh < 32)
1999 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2000 else
2001 op->val = 0;
2002 goto logical_done;
2003
2004 case 792: /* sraw */
2005 op->type = COMPUTE + SETREG + SETXER;
2006 sh = regs->gpr[rb] & 0x3f;
2007 ival = (signed int) regs->gpr[rd];
2008 op->val = ival >> (sh < 32 ? sh : 31);
2009 op->xerval = regs->xer;
2010 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2011 op->xerval |= XER_CA;
2012 else
2013 op->xerval &= ~XER_CA;
2014 set_ca32(op, op->xerval & XER_CA);
2015 goto logical_done;
2016
2017 case 824: /* srawi */
2018 op->type = COMPUTE + SETREG + SETXER;
2019 sh = rb;
2020 ival = (signed int) regs->gpr[rd];
2021 op->val = ival >> sh;
2022 op->xerval = regs->xer;
2023 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2024 op->xerval |= XER_CA;
2025 else
2026 op->xerval &= ~XER_CA;
2027 set_ca32(op, op->xerval & XER_CA);
2028 goto logical_done;
2029
2030 #ifdef __powerpc64__
2031 case 27: /* sld */
2032 sh = regs->gpr[rb] & 0x7f;
2033 if (sh < 64)
2034 op->val = regs->gpr[rd] << sh;
2035 else
2036 op->val = 0;
2037 goto logical_done;
2038
2039 case 539: /* srd */
2040 sh = regs->gpr[rb] & 0x7f;
2041 if (sh < 64)
2042 op->val = regs->gpr[rd] >> sh;
2043 else
2044 op->val = 0;
2045 goto logical_done;
2046
2047 case 794: /* srad */
2048 op->type = COMPUTE + SETREG + SETXER;
2049 sh = regs->gpr[rb] & 0x7f;
2050 ival = (signed long int) regs->gpr[rd];
2051 op->val = ival >> (sh < 64 ? sh : 63);
2052 op->xerval = regs->xer;
2053 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2054 op->xerval |= XER_CA;
2055 else
2056 op->xerval &= ~XER_CA;
2057 set_ca32(op, op->xerval & XER_CA);
2058 goto logical_done;
2059
2060 case 826: /* sradi with sh_5 = 0 */
2061 case 827: /* sradi with sh_5 = 1 */
2062 op->type = COMPUTE + SETREG + SETXER;
2063 sh = rb | ((word & 2) << 4);
2064 ival = (signed long int) regs->gpr[rd];
2065 op->val = ival >> sh;
2066 op->xerval = regs->xer;
2067 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2068 op->xerval |= XER_CA;
2069 else
2070 op->xerval &= ~XER_CA;
2071 set_ca32(op, op->xerval & XER_CA);
2072 goto logical_done;
2073
2074 case 890: /* extswsli with sh_5 = 0 */
2075 case 891: /* extswsli with sh_5 = 1 */
2076 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2077 goto unknown_opcode;
2078 op->type = COMPUTE + SETREG;
2079 sh = rb | ((word & 2) << 4);
2080 val = (signed int) regs->gpr[rd];
2081 if (sh)
2082 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2083 else
2084 op->val = val;
2085 goto logical_done;
2086
2087 #endif /* __powerpc64__ */
2088
2089 /*
2090 * Cache instructions
2091 */
2092 case 54: /* dcbst */
2093 op->type = MKOP(CACHEOP, DCBST, 0);
2094 op->ea = xform_ea(word, regs);
2095 return 0;
2096
2097 case 86: /* dcbf */
2098 op->type = MKOP(CACHEOP, DCBF, 0);
2099 op->ea = xform_ea(word, regs);
2100 return 0;
2101
2102 case 246: /* dcbtst */
2103 op->type = MKOP(CACHEOP, DCBTST, 0);
2104 op->ea = xform_ea(word, regs);
2105 op->reg = rd;
2106 return 0;
2107
2108 case 278: /* dcbt */
2109 op->type = MKOP(CACHEOP, DCBTST, 0);
2110 op->ea = xform_ea(word, regs);
2111 op->reg = rd;
2112 return 0;
2113
2114 case 982: /* icbi */
2115 op->type = MKOP(CACHEOP, ICBI, 0);
2116 op->ea = xform_ea(word, regs);
2117 return 0;
2118
2119 case 1014: /* dcbz */
2120 op->type = MKOP(CACHEOP, DCBZ, 0);
2121 op->ea = xform_ea(word, regs);
2122 return 0;
2123 }
2124 break;
2125 }
2126
2127 /*
2128 * Loads and stores.
2129 */
2130 op->type = UNKNOWN;
2131 op->update_reg = ra;
2132 op->reg = rd;
2133 op->val = regs->gpr[rd];
2134 u = (word >> 20) & UPDATE;
2135 op->vsx_flags = 0;
2136
2137 switch (opcode) {
2138 case 31:
2139 u = word & UPDATE;
2140 op->ea = xform_ea(word, regs);
2141 switch ((word >> 1) & 0x3ff) {
2142 case 20: /* lwarx */
2143 op->type = MKOP(LARX, 0, 4);
2144 break;
2145
2146 case 150: /* stwcx. */
2147 op->type = MKOP(STCX, 0, 4);
2148 break;
2149
2150 #ifdef __powerpc64__
2151 case 84: /* ldarx */
2152 op->type = MKOP(LARX, 0, 8);
2153 break;
2154
2155 case 214: /* stdcx. */
2156 op->type = MKOP(STCX, 0, 8);
2157 break;
2158
2159 case 52: /* lbarx */
2160 op->type = MKOP(LARX, 0, 1);
2161 break;
2162
2163 case 694: /* stbcx. */
2164 op->type = MKOP(STCX, 0, 1);
2165 break;
2166
2167 case 116: /* lharx */
2168 op->type = MKOP(LARX, 0, 2);
2169 break;
2170
2171 case 726: /* sthcx. */
2172 op->type = MKOP(STCX, 0, 2);
2173 break;
2174
2175 case 276: /* lqarx */
2176 if (!((rd & 1) || rd == ra || rd == rb))
2177 op->type = MKOP(LARX, 0, 16);
2178 break;
2179
2180 case 182: /* stqcx. */
2181 if (!(rd & 1))
2182 op->type = MKOP(STCX, 0, 16);
2183 break;
2184 #endif
2185
2186 case 23: /* lwzx */
2187 case 55: /* lwzux */
2188 op->type = MKOP(LOAD, u, 4);
2189 break;
2190
2191 case 87: /* lbzx */
2192 case 119: /* lbzux */
2193 op->type = MKOP(LOAD, u, 1);
2194 break;
2195
2196 #ifdef CONFIG_ALTIVEC
2197 /*
2198 * Note: for the load/store vector element instructions,
2199 * bits of the EA say which field of the VMX register to use.
2200 */
2201 case 7: /* lvebx */
2202 op->type = MKOP(LOAD_VMX, 0, 1);
2203 op->element_size = 1;
2204 break;
2205
2206 case 39: /* lvehx */
2207 op->type = MKOP(LOAD_VMX, 0, 2);
2208 op->element_size = 2;
2209 break;
2210
2211 case 71: /* lvewx */
2212 op->type = MKOP(LOAD_VMX, 0, 4);
2213 op->element_size = 4;
2214 break;
2215
2216 case 103: /* lvx */
2217 case 359: /* lvxl */
2218 op->type = MKOP(LOAD_VMX, 0, 16);
2219 op->element_size = 16;
2220 break;
2221
2222 case 135: /* stvebx */
2223 op->type = MKOP(STORE_VMX, 0, 1);
2224 op->element_size = 1;
2225 break;
2226
2227 case 167: /* stvehx */
2228 op->type = MKOP(STORE_VMX, 0, 2);
2229 op->element_size = 2;
2230 break;
2231
2232 case 199: /* stvewx */
2233 op->type = MKOP(STORE_VMX, 0, 4);
2234 op->element_size = 4;
2235 break;
2236
2237 case 231: /* stvx */
2238 case 487: /* stvxl */
2239 op->type = MKOP(STORE_VMX, 0, 16);
2240 break;
2241 #endif /* CONFIG_ALTIVEC */
2242
2243 #ifdef __powerpc64__
2244 case 21: /* ldx */
2245 case 53: /* ldux */
2246 op->type = MKOP(LOAD, u, 8);
2247 break;
2248
2249 case 149: /* stdx */
2250 case 181: /* stdux */
2251 op->type = MKOP(STORE, u, 8);
2252 break;
2253 #endif
2254
2255 case 151: /* stwx */
2256 case 183: /* stwux */
2257 op->type = MKOP(STORE, u, 4);
2258 break;
2259
2260 case 215: /* stbx */
2261 case 247: /* stbux */
2262 op->type = MKOP(STORE, u, 1);
2263 break;
2264
2265 case 279: /* lhzx */
2266 case 311: /* lhzux */
2267 op->type = MKOP(LOAD, u, 2);
2268 break;
2269
2270 #ifdef __powerpc64__
2271 case 341: /* lwax */
2272 case 373: /* lwaux */
2273 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2274 break;
2275 #endif
2276
2277 case 343: /* lhax */
2278 case 375: /* lhaux */
2279 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2280 break;
2281
2282 case 407: /* sthx */
2283 case 439: /* sthux */
2284 op->type = MKOP(STORE, u, 2);
2285 break;
2286
2287 #ifdef __powerpc64__
2288 case 532: /* ldbrx */
2289 op->type = MKOP(LOAD, BYTEREV, 8);
2290 break;
2291
2292 #endif
2293 case 533: /* lswx */
2294 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2295 break;
2296
2297 case 534: /* lwbrx */
2298 op->type = MKOP(LOAD, BYTEREV, 4);
2299 break;
2300
2301 case 597: /* lswi */
2302 if (rb == 0)
2303 rb = 32; /* # bytes to load */
2304 op->type = MKOP(LOAD_MULTI, 0, rb);
2305 op->ea = ra ? regs->gpr[ra] : 0;
2306 break;
2307
2308 #ifdef CONFIG_PPC_FPU
2309 case 535: /* lfsx */
2310 case 567: /* lfsux */
2311 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2312 break;
2313
2314 case 599: /* lfdx */
2315 case 631: /* lfdux */
2316 op->type = MKOP(LOAD_FP, u, 8);
2317 break;
2318
2319 case 663: /* stfsx */
2320 case 695: /* stfsux */
2321 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2322 break;
2323
2324 case 727: /* stfdx */
2325 case 759: /* stfdux */
2326 op->type = MKOP(STORE_FP, u, 8);
2327 break;
2328
2329 #ifdef __powerpc64__
2330 case 791: /* lfdpx */
2331 op->type = MKOP(LOAD_FP, 0, 16);
2332 break;
2333
2334 case 855: /* lfiwax */
2335 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2336 break;
2337
2338 case 887: /* lfiwzx */
2339 op->type = MKOP(LOAD_FP, 0, 4);
2340 break;
2341
2342 case 919: /* stfdpx */
2343 op->type = MKOP(STORE_FP, 0, 16);
2344 break;
2345
2346 case 983: /* stfiwx */
2347 op->type = MKOP(STORE_FP, 0, 4);
2348 break;
2349 #endif /* __powerpc64 */
2350 #endif /* CONFIG_PPC_FPU */
2351
2352 #ifdef __powerpc64__
2353 case 660: /* stdbrx */
2354 op->type = MKOP(STORE, BYTEREV, 8);
2355 op->val = byterev_8(regs->gpr[rd]);
2356 break;
2357
2358 #endif
2359 case 661: /* stswx */
2360 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2361 break;
2362
2363 case 662: /* stwbrx */
2364 op->type = MKOP(STORE, BYTEREV, 4);
2365 op->val = byterev_4(regs->gpr[rd]);
2366 break;
2367
2368 case 725: /* stswi */
2369 if (rb == 0)
2370 rb = 32; /* # bytes to store */
2371 op->type = MKOP(STORE_MULTI, 0, rb);
2372 op->ea = ra ? regs->gpr[ra] : 0;
2373 break;
2374
2375 case 790: /* lhbrx */
2376 op->type = MKOP(LOAD, BYTEREV, 2);
2377 break;
2378
2379 case 918: /* sthbrx */
2380 op->type = MKOP(STORE, BYTEREV, 2);
2381 op->val = byterev_2(regs->gpr[rd]);
2382 break;
2383
2384 #ifdef CONFIG_VSX
2385 case 12: /* lxsiwzx */
2386 op->reg = rd | ((word & 1) << 5);
2387 op->type = MKOP(LOAD_VSX, 0, 4);
2388 op->element_size = 8;
2389 break;
2390
2391 case 76: /* lxsiwax */
2392 op->reg = rd | ((word & 1) << 5);
2393 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2394 op->element_size = 8;
2395 break;
2396
2397 case 140: /* stxsiwx */
2398 op->reg = rd | ((word & 1) << 5);
2399 op->type = MKOP(STORE_VSX, 0, 4);
2400 op->element_size = 8;
2401 break;
2402
2403 case 268: /* lxvx */
2404 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2405 goto unknown_opcode;
2406 op->reg = rd | ((word & 1) << 5);
2407 op->type = MKOP(LOAD_VSX, 0, 16);
2408 op->element_size = 16;
2409 op->vsx_flags = VSX_CHECK_VEC;
2410 break;
2411
2412 case 269: /* lxvl */
2413 case 301: { /* lxvll */
2414 int nb;
2415 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2416 goto unknown_opcode;
2417 op->reg = rd | ((word & 1) << 5);
2418 op->ea = ra ? regs->gpr[ra] : 0;
2419 nb = regs->gpr[rb] & 0xff;
2420 if (nb > 16)
2421 nb = 16;
2422 op->type = MKOP(LOAD_VSX, 0, nb);
2423 op->element_size = 16;
2424 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2425 VSX_CHECK_VEC;
2426 break;
2427 }
2428 case 332: /* lxvdsx */
2429 op->reg = rd | ((word & 1) << 5);
2430 op->type = MKOP(LOAD_VSX, 0, 8);
2431 op->element_size = 8;
2432 op->vsx_flags = VSX_SPLAT;
2433 break;
2434
2435 case 364: /* lxvwsx */
2436 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2437 goto unknown_opcode;
2438 op->reg = rd | ((word & 1) << 5);
2439 op->type = MKOP(LOAD_VSX, 0, 4);
2440 op->element_size = 4;
2441 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2442 break;
2443
2444 case 396: /* stxvx */
2445 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2446 goto unknown_opcode;
2447 op->reg = rd | ((word & 1) << 5);
2448 op->type = MKOP(STORE_VSX, 0, 16);
2449 op->element_size = 16;
2450 op->vsx_flags = VSX_CHECK_VEC;
2451 break;
2452
2453 case 397: /* stxvl */
2454 case 429: { /* stxvll */
2455 int nb;
2456 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2457 goto unknown_opcode;
2458 op->reg = rd | ((word & 1) << 5);
2459 op->ea = ra ? regs->gpr[ra] : 0;
2460 nb = regs->gpr[rb] & 0xff;
2461 if (nb > 16)
2462 nb = 16;
2463 op->type = MKOP(STORE_VSX, 0, nb);
2464 op->element_size = 16;
2465 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2466 VSX_CHECK_VEC;
2467 break;
2468 }
2469 case 524: /* lxsspx */
2470 op->reg = rd | ((word & 1) << 5);
2471 op->type = MKOP(LOAD_VSX, 0, 4);
2472 op->element_size = 8;
2473 op->vsx_flags = VSX_FPCONV;
2474 break;
2475
2476 case 588: /* lxsdx */
2477 op->reg = rd | ((word & 1) << 5);
2478 op->type = MKOP(LOAD_VSX, 0, 8);
2479 op->element_size = 8;
2480 break;
2481
2482 case 652: /* stxsspx */
2483 op->reg = rd | ((word & 1) << 5);
2484 op->type = MKOP(STORE_VSX, 0, 4);
2485 op->element_size = 8;
2486 op->vsx_flags = VSX_FPCONV;
2487 break;
2488
2489 case 716: /* stxsdx */
2490 op->reg = rd | ((word & 1) << 5);
2491 op->type = MKOP(STORE_VSX, 0, 8);
2492 op->element_size = 8;
2493 break;
2494
2495 case 780: /* lxvw4x */
2496 op->reg = rd | ((word & 1) << 5);
2497 op->type = MKOP(LOAD_VSX, 0, 16);
2498 op->element_size = 4;
2499 break;
2500
2501 case 781: /* lxsibzx */
2502 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2503 goto unknown_opcode;
2504 op->reg = rd | ((word & 1) << 5);
2505 op->type = MKOP(LOAD_VSX, 0, 1);
2506 op->element_size = 8;
2507 op->vsx_flags = VSX_CHECK_VEC;
2508 break;
2509
2510 case 812: /* lxvh8x */
2511 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2512 goto unknown_opcode;
2513 op->reg = rd | ((word & 1) << 5);
2514 op->type = MKOP(LOAD_VSX, 0, 16);
2515 op->element_size = 2;
2516 op->vsx_flags = VSX_CHECK_VEC;
2517 break;
2518
2519 case 813: /* lxsihzx */
2520 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2521 goto unknown_opcode;
2522 op->reg = rd | ((word & 1) << 5);
2523 op->type = MKOP(LOAD_VSX, 0, 2);
2524 op->element_size = 8;
2525 op->vsx_flags = VSX_CHECK_VEC;
2526 break;
2527
2528 case 844: /* lxvd2x */
2529 op->reg = rd | ((word & 1) << 5);
2530 op->type = MKOP(LOAD_VSX, 0, 16);
2531 op->element_size = 8;
2532 break;
2533
2534 case 876: /* lxvb16x */
2535 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2536 goto unknown_opcode;
2537 op->reg = rd | ((word & 1) << 5);
2538 op->type = MKOP(LOAD_VSX, 0, 16);
2539 op->element_size = 1;
2540 op->vsx_flags = VSX_CHECK_VEC;
2541 break;
2542
2543 case 908: /* stxvw4x */
2544 op->reg = rd | ((word & 1) << 5);
2545 op->type = MKOP(STORE_VSX, 0, 16);
2546 op->element_size = 4;
2547 break;
2548
2549 case 909: /* stxsibx */
2550 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2551 goto unknown_opcode;
2552 op->reg = rd | ((word & 1) << 5);
2553 op->type = MKOP(STORE_VSX, 0, 1);
2554 op->element_size = 8;
2555 op->vsx_flags = VSX_CHECK_VEC;
2556 break;
2557
2558 case 940: /* stxvh8x */
2559 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2560 goto unknown_opcode;
2561 op->reg = rd | ((word & 1) << 5);
2562 op->type = MKOP(STORE_VSX, 0, 16);
2563 op->element_size = 2;
2564 op->vsx_flags = VSX_CHECK_VEC;
2565 break;
2566
2567 case 941: /* stxsihx */
2568 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2569 goto unknown_opcode;
2570 op->reg = rd | ((word & 1) << 5);
2571 op->type = MKOP(STORE_VSX, 0, 2);
2572 op->element_size = 8;
2573 op->vsx_flags = VSX_CHECK_VEC;
2574 break;
2575
2576 case 972: /* stxvd2x */
2577 op->reg = rd | ((word & 1) << 5);
2578 op->type = MKOP(STORE_VSX, 0, 16);
2579 op->element_size = 8;
2580 break;
2581
2582 case 1004: /* stxvb16x */
2583 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2584 goto unknown_opcode;
2585 op->reg = rd | ((word & 1) << 5);
2586 op->type = MKOP(STORE_VSX, 0, 16);
2587 op->element_size = 1;
2588 op->vsx_flags = VSX_CHECK_VEC;
2589 break;
2590
2591 #endif /* CONFIG_VSX */
2592 }
2593 break;
2594
2595 case 32: /* lwz */
2596 case 33: /* lwzu */
2597 op->type = MKOP(LOAD, u, 4);
2598 op->ea = dform_ea(word, regs);
2599 break;
2600
2601 case 34: /* lbz */
2602 case 35: /* lbzu */
2603 op->type = MKOP(LOAD, u, 1);
2604 op->ea = dform_ea(word, regs);
2605 break;
2606
2607 case 36: /* stw */
2608 case 37: /* stwu */
2609 op->type = MKOP(STORE, u, 4);
2610 op->ea = dform_ea(word, regs);
2611 break;
2612
2613 case 38: /* stb */
2614 case 39: /* stbu */
2615 op->type = MKOP(STORE, u, 1);
2616 op->ea = dform_ea(word, regs);
2617 break;
2618
2619 case 40: /* lhz */
2620 case 41: /* lhzu */
2621 op->type = MKOP(LOAD, u, 2);
2622 op->ea = dform_ea(word, regs);
2623 break;
2624
2625 case 42: /* lha */
2626 case 43: /* lhau */
2627 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2628 op->ea = dform_ea(word, regs);
2629 break;
2630
2631 case 44: /* sth */
2632 case 45: /* sthu */
2633 op->type = MKOP(STORE, u, 2);
2634 op->ea = dform_ea(word, regs);
2635 break;
2636
2637 case 46: /* lmw */
2638 if (ra >= rd)
2639 break; /* invalid form, ra in range to load */
2640 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2641 op->ea = dform_ea(word, regs);
2642 break;
2643
2644 case 47: /* stmw */
2645 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2646 op->ea = dform_ea(word, regs);
2647 break;
2648
2649 #ifdef CONFIG_PPC_FPU
2650 case 48: /* lfs */
2651 case 49: /* lfsu */
2652 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2653 op->ea = dform_ea(word, regs);
2654 break;
2655
2656 case 50: /* lfd */
2657 case 51: /* lfdu */
2658 op->type = MKOP(LOAD_FP, u, 8);
2659 op->ea = dform_ea(word, regs);
2660 break;
2661
2662 case 52: /* stfs */
2663 case 53: /* stfsu */
2664 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2665 op->ea = dform_ea(word, regs);
2666 break;
2667
2668 case 54: /* stfd */
2669 case 55: /* stfdu */
2670 op->type = MKOP(STORE_FP, u, 8);
2671 op->ea = dform_ea(word, regs);
2672 break;
2673 #endif
2674
2675 #ifdef __powerpc64__
2676 case 56: /* lq */
2677 if (!((rd & 1) || (rd == ra)))
2678 op->type = MKOP(LOAD, 0, 16);
2679 op->ea = dqform_ea(word, regs);
2680 break;
2681 #endif
2682
2683 #ifdef CONFIG_VSX
2684 case 57: /* lfdp, lxsd, lxssp */
2685 op->ea = dsform_ea(word, regs);
2686 switch (word & 3) {
2687 case 0: /* lfdp */
2688 if (rd & 1)
2689 break; /* reg must be even */
2690 op->type = MKOP(LOAD_FP, 0, 16);
2691 break;
2692 case 2: /* lxsd */
2693 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2694 goto unknown_opcode;
2695 op->reg = rd + 32;
2696 op->type = MKOP(LOAD_VSX, 0, 8);
2697 op->element_size = 8;
2698 op->vsx_flags = VSX_CHECK_VEC;
2699 break;
2700 case 3: /* lxssp */
2701 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2702 goto unknown_opcode;
2703 op->reg = rd + 32;
2704 op->type = MKOP(LOAD_VSX, 0, 4);
2705 op->element_size = 8;
2706 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2707 break;
2708 }
2709 break;
2710 #endif /* CONFIG_VSX */
2711
2712 #ifdef __powerpc64__
2713 case 58: /* ld[u], lwa */
2714 op->ea = dsform_ea(word, regs);
2715 switch (word & 3) {
2716 case 0: /* ld */
2717 op->type = MKOP(LOAD, 0, 8);
2718 break;
2719 case 1: /* ldu */
2720 op->type = MKOP(LOAD, UPDATE, 8);
2721 break;
2722 case 2: /* lwa */
2723 op->type = MKOP(LOAD, SIGNEXT, 4);
2724 break;
2725 }
2726 break;
2727 #endif
2728
2729 #ifdef CONFIG_VSX
2730 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2731 switch (word & 7) {
2732 case 0: /* stfdp with LSB of DS field = 0 */
2733 case 4: /* stfdp with LSB of DS field = 1 */
2734 op->ea = dsform_ea(word, regs);
2735 op->type = MKOP(STORE_FP, 0, 16);
2736 break;
2737
2738 case 1: /* lxv */
2739 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2740 goto unknown_opcode;
2741 op->ea = dqform_ea(word, regs);
2742 if (word & 8)
2743 op->reg = rd + 32;
2744 op->type = MKOP(LOAD_VSX, 0, 16);
2745 op->element_size = 16;
2746 op->vsx_flags = VSX_CHECK_VEC;
2747 break;
2748
2749 case 2: /* stxsd with LSB of DS field = 0 */
2750 case 6: /* stxsd with LSB of DS field = 1 */
2751 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2752 goto unknown_opcode;
2753 op->ea = dsform_ea(word, regs);
2754 op->reg = rd + 32;
2755 op->type = MKOP(STORE_VSX, 0, 8);
2756 op->element_size = 8;
2757 op->vsx_flags = VSX_CHECK_VEC;
2758 break;
2759
2760 case 3: /* stxssp with LSB of DS field = 0 */
2761 case 7: /* stxssp with LSB of DS field = 1 */
2762 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2763 goto unknown_opcode;
2764 op->ea = dsform_ea(word, regs);
2765 op->reg = rd + 32;
2766 op->type = MKOP(STORE_VSX, 0, 4);
2767 op->element_size = 8;
2768 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2769 break;
2770
2771 case 5: /* stxv */
2772 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2773 goto unknown_opcode;
2774 op->ea = dqform_ea(word, regs);
2775 if (word & 8)
2776 op->reg = rd + 32;
2777 op->type = MKOP(STORE_VSX, 0, 16);
2778 op->element_size = 16;
2779 op->vsx_flags = VSX_CHECK_VEC;
2780 break;
2781 }
2782 break;
2783 #endif /* CONFIG_VSX */
2784
2785 #ifdef __powerpc64__
2786 case 62: /* std[u] */
2787 op->ea = dsform_ea(word, regs);
2788 switch (word & 3) {
2789 case 0: /* std */
2790 op->type = MKOP(STORE, 0, 8);
2791 break;
2792 case 1: /* stdu */
2793 op->type = MKOP(STORE, UPDATE, 8);
2794 break;
2795 case 2: /* stq */
2796 if (!(rd & 1))
2797 op->type = MKOP(STORE, 0, 16);
2798 break;
2799 }
2800 break;
2801 case 1: /* Prefixed instructions */
2802 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2803 goto unknown_opcode;
2804
2805 prefix_r = GET_PREFIX_R(word);
2806 ra = GET_PREFIX_RA(suffix);
2807 op->update_reg = ra;
2808 rd = (suffix >> 21) & 0x1f;
2809 op->reg = rd;
2810 op->val = regs->gpr[rd];
2811
2812 suffixopcode = get_op(suffix);
2813 prefixtype = (word >> 24) & 0x3;
2814 switch (prefixtype) {
2815 case 0: /* Type 00 Eight-Byte Load/Store */
2816 if (prefix_r && ra)
2817 break;
2818 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2819 switch (suffixopcode) {
2820 case 41: /* plwa */
2821 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2822 break;
2823 #ifdef CONFIG_VSX
2824 case 42: /* plxsd */
2825 op->reg = rd + 32;
2826 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2827 op->element_size = 8;
2828 op->vsx_flags = VSX_CHECK_VEC;
2829 break;
2830 case 43: /* plxssp */
2831 op->reg = rd + 32;
2832 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2833 op->element_size = 8;
2834 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2835 break;
2836 case 46: /* pstxsd */
2837 op->reg = rd + 32;
2838 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2839 op->element_size = 8;
2840 op->vsx_flags = VSX_CHECK_VEC;
2841 break;
2842 case 47: /* pstxssp */
2843 op->reg = rd + 32;
2844 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2845 op->element_size = 8;
2846 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2847 break;
2848 case 51: /* plxv1 */
2849 op->reg += 32;
2850 fallthrough;
2851 case 50: /* plxv0 */
2852 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2853 op->element_size = 16;
2854 op->vsx_flags = VSX_CHECK_VEC;
2855 break;
2856 case 55: /* pstxv1 */
2857 op->reg = rd + 32;
2858 fallthrough;
2859 case 54: /* pstxv0 */
2860 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2861 op->element_size = 16;
2862 op->vsx_flags = VSX_CHECK_VEC;
2863 break;
2864 #endif /* CONFIG_VSX */
2865 case 56: /* plq */
2866 op->type = MKOP(LOAD, PREFIXED, 16);
2867 break;
2868 case 57: /* pld */
2869 op->type = MKOP(LOAD, PREFIXED, 8);
2870 break;
2871 case 60: /* pstq */
2872 op->type = MKOP(STORE, PREFIXED, 16);
2873 break;
2874 case 61: /* pstd */
2875 op->type = MKOP(STORE, PREFIXED, 8);
2876 break;
2877 }
2878 break;
2879 case 1: /* Type 01 Eight-Byte Register-to-Register */
2880 break;
2881 case 2: /* Type 10 Modified Load/Store */
2882 if (prefix_r && ra)
2883 break;
2884 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2885 switch (suffixopcode) {
2886 case 32: /* plwz */
2887 op->type = MKOP(LOAD, PREFIXED, 4);
2888 break;
2889 case 34: /* plbz */
2890 op->type = MKOP(LOAD, PREFIXED, 1);
2891 break;
2892 case 36: /* pstw */
2893 op->type = MKOP(STORE, PREFIXED, 4);
2894 break;
2895 case 38: /* pstb */
2896 op->type = MKOP(STORE, PREFIXED, 1);
2897 break;
2898 case 40: /* plhz */
2899 op->type = MKOP(LOAD, PREFIXED, 2);
2900 break;
2901 case 42: /* plha */
2902 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2903 break;
2904 case 44: /* psth */
2905 op->type = MKOP(STORE, PREFIXED, 2);
2906 break;
2907 case 48: /* plfs */
2908 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2909 break;
2910 case 50: /* plfd */
2911 op->type = MKOP(LOAD_FP, PREFIXED, 8);
2912 break;
2913 case 52: /* pstfs */
2914 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2915 break;
2916 case 54: /* pstfd */
2917 op->type = MKOP(STORE_FP, PREFIXED, 8);
2918 break;
2919 }
2920 break;
2921 case 3: /* Type 11 Modified Register-to-Register */
2922 break;
2923 }
2924 #endif /* __powerpc64__ */
2925
2926 }
2927
2928 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
2929 switch (GETTYPE(op->type)) {
2930 case LOAD:
2931 if (ra == rd)
2932 goto unknown_opcode;
2933 fallthrough;
2934 case STORE:
2935 case LOAD_FP:
2936 case STORE_FP:
2937 if (ra == 0)
2938 goto unknown_opcode;
2939 }
2940 }
2941
2942 #ifdef CONFIG_VSX
2943 if ((GETTYPE(op->type) == LOAD_VSX ||
2944 GETTYPE(op->type) == STORE_VSX) &&
2945 !cpu_has_feature(CPU_FTR_VSX)) {
2946 return -1;
2947 }
2948 #endif /* CONFIG_VSX */
2949
2950 return 0;
2951
2952 unknown_opcode:
2953 op->type = UNKNOWN;
2954 return 0;
2955
2956 logical_done:
2957 if (word & 1)
2958 set_cr0(regs, op);
2959 logical_done_nocc:
2960 op->reg = ra;
2961 op->type |= SETREG;
2962 return 1;
2963
2964 arith_done:
2965 if (word & 1)
2966 set_cr0(regs, op);
2967 compute_done:
2968 op->reg = rd;
2969 op->type |= SETREG;
2970 return 1;
2971
2972 priv:
2973 op->type = INTERRUPT | 0x700;
2974 op->val = SRR1_PROGPRIV;
2975 return 0;
2976
2977 trap:
2978 op->type = INTERRUPT | 0x700;
2979 op->val = SRR1_PROGTRAP;
2980 return 0;
2981 }
2982 EXPORT_SYMBOL_GPL(analyse_instr);
2983 NOKPROBE_SYMBOL(analyse_instr);
2984
2985 /*
2986 * For PPC32 we always use stwu with r1 to change the stack pointer.
2987 * So this emulated store may corrupt the exception frame, now we
2988 * have to provide the exception frame trampoline, which is pushed
2989 * below the kprobed function stack. So we only update gpr[1] but
2990 * don't emulate the real store operation. We will do real store
2991 * operation safely in exception return code by checking this flag.
2992 */
handle_stack_update(unsigned long ea,struct pt_regs * regs)2993 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2994 {
2995 #ifdef CONFIG_PPC32
2996 /*
2997 * Check if we will touch kernel stack overflow
2998 */
2999 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
3000 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
3001 return -EINVAL;
3002 }
3003 #endif /* CONFIG_PPC32 */
3004 /*
3005 * Check if we already set since that means we'll
3006 * lose the previous value.
3007 */
3008 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3009 set_thread_flag(TIF_EMULATE_STACK_STORE);
3010 return 0;
3011 }
3012
do_signext(unsigned long * valp,int size)3013 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3014 {
3015 switch (size) {
3016 case 2:
3017 *valp = (signed short) *valp;
3018 break;
3019 case 4:
3020 *valp = (signed int) *valp;
3021 break;
3022 }
3023 }
3024
do_byterev(unsigned long * valp,int size)3025 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3026 {
3027 switch (size) {
3028 case 2:
3029 *valp = byterev_2(*valp);
3030 break;
3031 case 4:
3032 *valp = byterev_4(*valp);
3033 break;
3034 #ifdef __powerpc64__
3035 case 8:
3036 *valp = byterev_8(*valp);
3037 break;
3038 #endif
3039 }
3040 }
3041
3042 /*
3043 * Emulate an instruction that can be executed just by updating
3044 * fields in *regs.
3045 */
emulate_update_regs(struct pt_regs * regs,struct instruction_op * op)3046 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3047 {
3048 unsigned long next_pc;
3049
3050 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3051 switch (GETTYPE(op->type)) {
3052 case COMPUTE:
3053 if (op->type & SETREG)
3054 regs->gpr[op->reg] = op->val;
3055 if (op->type & SETCC)
3056 regs->ccr = op->ccval;
3057 if (op->type & SETXER)
3058 regs->xer = op->xerval;
3059 break;
3060
3061 case BRANCH:
3062 if (op->type & SETLK)
3063 regs->link = next_pc;
3064 if (op->type & BRTAKEN)
3065 next_pc = op->val;
3066 if (op->type & DECCTR)
3067 --regs->ctr;
3068 break;
3069
3070 case BARRIER:
3071 switch (op->type & BARRIER_MASK) {
3072 case BARRIER_SYNC:
3073 mb();
3074 break;
3075 case BARRIER_ISYNC:
3076 isync();
3077 break;
3078 case BARRIER_EIEIO:
3079 eieio();
3080 break;
3081 #ifdef CONFIG_PPC64
3082 case BARRIER_LWSYNC:
3083 asm volatile("lwsync" : : : "memory");
3084 break;
3085 case BARRIER_PTESYNC:
3086 asm volatile("ptesync" : : : "memory");
3087 break;
3088 #endif
3089 }
3090 break;
3091
3092 case MFSPR:
3093 switch (op->spr) {
3094 case SPRN_XER:
3095 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3096 break;
3097 case SPRN_LR:
3098 regs->gpr[op->reg] = regs->link;
3099 break;
3100 case SPRN_CTR:
3101 regs->gpr[op->reg] = regs->ctr;
3102 break;
3103 default:
3104 WARN_ON_ONCE(1);
3105 }
3106 break;
3107
3108 case MTSPR:
3109 switch (op->spr) {
3110 case SPRN_XER:
3111 regs->xer = op->val & 0xffffffffUL;
3112 break;
3113 case SPRN_LR:
3114 regs->link = op->val;
3115 break;
3116 case SPRN_CTR:
3117 regs->ctr = op->val;
3118 break;
3119 default:
3120 WARN_ON_ONCE(1);
3121 }
3122 break;
3123
3124 default:
3125 WARN_ON_ONCE(1);
3126 }
3127 regs->nip = next_pc;
3128 }
3129 NOKPROBE_SYMBOL(emulate_update_regs);
3130
3131 /*
3132 * Emulate a previously-analysed load or store instruction.
3133 * Return values are:
3134 * 0 = instruction emulated successfully
3135 * -EFAULT = address out of range or access faulted (regs->dar
3136 * contains the faulting address)
3137 * -EACCES = misaligned access, instruction requires alignment
3138 * -EINVAL = unknown operation in *op
3139 */
emulate_loadstore(struct pt_regs * regs,struct instruction_op * op)3140 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3141 {
3142 int err, size, type;
3143 int i, rd, nb;
3144 unsigned int cr;
3145 unsigned long val;
3146 unsigned long ea;
3147 bool cross_endian;
3148
3149 err = 0;
3150 size = GETSIZE(op->type);
3151 type = GETTYPE(op->type);
3152 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3153 ea = truncate_if_32bit(regs->msr, op->ea);
3154
3155 switch (type) {
3156 case LARX:
3157 if (ea & (size - 1))
3158 return -EACCES; /* can't handle misaligned */
3159 if (!address_ok(regs, ea, size))
3160 return -EFAULT;
3161 err = 0;
3162 val = 0;
3163 switch (size) {
3164 #ifdef __powerpc64__
3165 case 1:
3166 __get_user_asmx(val, ea, err, "lbarx");
3167 break;
3168 case 2:
3169 __get_user_asmx(val, ea, err, "lharx");
3170 break;
3171 #endif
3172 case 4:
3173 __get_user_asmx(val, ea, err, "lwarx");
3174 break;
3175 #ifdef __powerpc64__
3176 case 8:
3177 __get_user_asmx(val, ea, err, "ldarx");
3178 break;
3179 case 16:
3180 err = do_lqarx(ea, ®s->gpr[op->reg]);
3181 break;
3182 #endif
3183 default:
3184 return -EINVAL;
3185 }
3186 if (err) {
3187 regs->dar = ea;
3188 break;
3189 }
3190 if (size < 16)
3191 regs->gpr[op->reg] = val;
3192 break;
3193
3194 case STCX:
3195 if (ea & (size - 1))
3196 return -EACCES; /* can't handle misaligned */
3197 if (!address_ok(regs, ea, size))
3198 return -EFAULT;
3199 err = 0;
3200 switch (size) {
3201 #ifdef __powerpc64__
3202 case 1:
3203 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3204 break;
3205 case 2:
3206 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
3207 break;
3208 #endif
3209 case 4:
3210 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3211 break;
3212 #ifdef __powerpc64__
3213 case 8:
3214 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3215 break;
3216 case 16:
3217 err = do_stqcx(ea, regs->gpr[op->reg],
3218 regs->gpr[op->reg + 1], &cr);
3219 break;
3220 #endif
3221 default:
3222 return -EINVAL;
3223 }
3224 if (!err)
3225 regs->ccr = (regs->ccr & 0x0fffffff) |
3226 (cr & 0xe0000000) |
3227 ((regs->xer >> 3) & 0x10000000);
3228 else
3229 regs->dar = ea;
3230 break;
3231
3232 case LOAD:
3233 #ifdef __powerpc64__
3234 if (size == 16) {
3235 err = emulate_lq(regs, ea, op->reg, cross_endian);
3236 break;
3237 }
3238 #endif
3239 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3240 if (!err) {
3241 if (op->type & SIGNEXT)
3242 do_signext(®s->gpr[op->reg], size);
3243 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3244 do_byterev(®s->gpr[op->reg], size);
3245 }
3246 break;
3247
3248 #ifdef CONFIG_PPC_FPU
3249 case LOAD_FP:
3250 /*
3251 * If the instruction is in userspace, we can emulate it even
3252 * if the VMX state is not live, because we have the state
3253 * stored in the thread_struct. If the instruction is in
3254 * the kernel, we must not touch the state in the thread_struct.
3255 */
3256 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3257 return 0;
3258 err = do_fp_load(op, ea, regs, cross_endian);
3259 break;
3260 #endif
3261 #ifdef CONFIG_ALTIVEC
3262 case LOAD_VMX:
3263 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3264 return 0;
3265 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3266 break;
3267 #endif
3268 #ifdef CONFIG_VSX
3269 case LOAD_VSX: {
3270 unsigned long msrbit = MSR_VSX;
3271
3272 /*
3273 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3274 * when the target of the instruction is a vector register.
3275 */
3276 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3277 msrbit = MSR_VEC;
3278 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3279 return 0;
3280 err = do_vsx_load(op, ea, regs, cross_endian);
3281 break;
3282 }
3283 #endif
3284 case LOAD_MULTI:
3285 if (!address_ok(regs, ea, size))
3286 return -EFAULT;
3287 rd = op->reg;
3288 for (i = 0; i < size; i += 4) {
3289 unsigned int v32 = 0;
3290
3291 nb = size - i;
3292 if (nb > 4)
3293 nb = 4;
3294 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3295 if (err)
3296 break;
3297 if (unlikely(cross_endian))
3298 v32 = byterev_4(v32);
3299 regs->gpr[rd] = v32;
3300 ea += 4;
3301 /* reg number wraps from 31 to 0 for lsw[ix] */
3302 rd = (rd + 1) & 0x1f;
3303 }
3304 break;
3305
3306 case STORE:
3307 #ifdef __powerpc64__
3308 if (size == 16) {
3309 err = emulate_stq(regs, ea, op->reg, cross_endian);
3310 break;
3311 }
3312 #endif
3313 if ((op->type & UPDATE) && size == sizeof(long) &&
3314 op->reg == 1 && op->update_reg == 1 &&
3315 !(regs->msr & MSR_PR) &&
3316 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3317 err = handle_stack_update(ea, regs);
3318 break;
3319 }
3320 if (unlikely(cross_endian))
3321 do_byterev(&op->val, size);
3322 err = write_mem(op->val, ea, size, regs);
3323 break;
3324
3325 #ifdef CONFIG_PPC_FPU
3326 case STORE_FP:
3327 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3328 return 0;
3329 err = do_fp_store(op, ea, regs, cross_endian);
3330 break;
3331 #endif
3332 #ifdef CONFIG_ALTIVEC
3333 case STORE_VMX:
3334 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3335 return 0;
3336 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3337 break;
3338 #endif
3339 #ifdef CONFIG_VSX
3340 case STORE_VSX: {
3341 unsigned long msrbit = MSR_VSX;
3342
3343 /*
3344 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3345 * when the target of the instruction is a vector register.
3346 */
3347 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3348 msrbit = MSR_VEC;
3349 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3350 return 0;
3351 err = do_vsx_store(op, ea, regs, cross_endian);
3352 break;
3353 }
3354 #endif
3355 case STORE_MULTI:
3356 if (!address_ok(regs, ea, size))
3357 return -EFAULT;
3358 rd = op->reg;
3359 for (i = 0; i < size; i += 4) {
3360 unsigned int v32 = regs->gpr[rd];
3361
3362 nb = size - i;
3363 if (nb > 4)
3364 nb = 4;
3365 if (unlikely(cross_endian))
3366 v32 = byterev_4(v32);
3367 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3368 if (err)
3369 break;
3370 ea += 4;
3371 /* reg number wraps from 31 to 0 for stsw[ix] */
3372 rd = (rd + 1) & 0x1f;
3373 }
3374 break;
3375
3376 default:
3377 return -EINVAL;
3378 }
3379
3380 if (err)
3381 return err;
3382
3383 if (op->type & UPDATE)
3384 regs->gpr[op->update_reg] = op->ea;
3385
3386 return 0;
3387 }
3388 NOKPROBE_SYMBOL(emulate_loadstore);
3389
3390 /*
3391 * Emulate instructions that cause a transfer of control,
3392 * loads and stores, and a few other instructions.
3393 * Returns 1 if the step was emulated, 0 if not,
3394 * or -1 if the instruction is one that should not be stepped,
3395 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3396 */
emulate_step(struct pt_regs * regs,struct ppc_inst instr)3397 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3398 {
3399 struct instruction_op op;
3400 int r, err, type;
3401 unsigned long val;
3402 unsigned long ea;
3403
3404 r = analyse_instr(&op, regs, instr);
3405 if (r < 0)
3406 return r;
3407 if (r > 0) {
3408 emulate_update_regs(regs, &op);
3409 return 1;
3410 }
3411
3412 err = 0;
3413 type = GETTYPE(op.type);
3414
3415 if (OP_IS_LOAD_STORE(type)) {
3416 err = emulate_loadstore(regs, &op);
3417 if (err)
3418 return 0;
3419 goto instr_done;
3420 }
3421
3422 switch (type) {
3423 case CACHEOP:
3424 ea = truncate_if_32bit(regs->msr, op.ea);
3425 if (!address_ok(regs, ea, 8))
3426 return 0;
3427 switch (op.type & CACHEOP_MASK) {
3428 case DCBST:
3429 __cacheop_user_asmx(ea, err, "dcbst");
3430 break;
3431 case DCBF:
3432 __cacheop_user_asmx(ea, err, "dcbf");
3433 break;
3434 case DCBTST:
3435 if (op.reg == 0)
3436 prefetchw((void *) ea);
3437 break;
3438 case DCBT:
3439 if (op.reg == 0)
3440 prefetch((void *) ea);
3441 break;
3442 case ICBI:
3443 __cacheop_user_asmx(ea, err, "icbi");
3444 break;
3445 case DCBZ:
3446 err = emulate_dcbz(ea, regs);
3447 break;
3448 }
3449 if (err) {
3450 regs->dar = ea;
3451 return 0;
3452 }
3453 goto instr_done;
3454
3455 case MFMSR:
3456 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3457 goto instr_done;
3458
3459 case MTMSR:
3460 val = regs->gpr[op.reg];
3461 if ((val & MSR_RI) == 0)
3462 /* can't step mtmsr[d] that would clear MSR_RI */
3463 return -1;
3464 /* here op.val is the mask of bits to change */
3465 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3466 goto instr_done;
3467
3468 #ifdef CONFIG_PPC64
3469 case SYSCALL: /* sc */
3470 /*
3471 * N.B. this uses knowledge about how the syscall
3472 * entry code works. If that is changed, this will
3473 * need to be changed also.
3474 */
3475 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3476 cpu_has_feature(CPU_FTR_REAL_LE) &&
3477 regs->gpr[0] == 0x1ebe) {
3478 regs->msr ^= MSR_LE;
3479 goto instr_done;
3480 }
3481 regs->gpr[9] = regs->gpr[13];
3482 regs->gpr[10] = MSR_KERNEL;
3483 regs->gpr[11] = regs->nip + 4;
3484 regs->gpr[12] = regs->msr & MSR_MASK;
3485 regs->gpr[13] = (unsigned long) get_paca();
3486 regs->nip = (unsigned long) &system_call_common;
3487 regs->msr = MSR_KERNEL;
3488 return 1;
3489
3490 #ifdef CONFIG_PPC_BOOK3S_64
3491 case SYSCALL_VECTORED_0: /* scv 0 */
3492 regs->gpr[9] = regs->gpr[13];
3493 regs->gpr[10] = MSR_KERNEL;
3494 regs->gpr[11] = regs->nip + 4;
3495 regs->gpr[12] = regs->msr & MSR_MASK;
3496 regs->gpr[13] = (unsigned long) get_paca();
3497 regs->nip = (unsigned long) &system_call_vectored_emulate;
3498 regs->msr = MSR_KERNEL;
3499 return 1;
3500 #endif
3501
3502 case RFI:
3503 return -1;
3504 #endif
3505 }
3506 return 0;
3507
3508 instr_done:
3509 regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
3510 return 1;
3511 }
3512 NOKPROBE_SYMBOL(emulate_step);
3513