1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AMD Encrypted Register State Support
4 *
5 * Author: Joerg Roedel <jroedel@suse.de>
6 */
7
8 /*
9 * misc.h needs to be first because it knows how to include the other kernel
10 * headers in the pre-decompression code in a way that does not break
11 * compilation.
12 */
13 #include "misc.h"
14
15 #include <asm/pgtable_types.h>
16 #include <asm/sev-es.h>
17 #include <asm/trapnr.h>
18 #include <asm/trap_pf.h>
19 #include <asm/msr-index.h>
20 #include <asm/fpu/xcr.h>
21 #include <asm/ptrace.h>
22 #include <asm/svm.h>
23
24 #include "error.h"
25
26 struct ghcb boot_ghcb_page __aligned(PAGE_SIZE);
27 struct ghcb *boot_ghcb;
28
29 /*
30 * Copy a version of this function here - insn-eval.c can't be used in
31 * pre-decompression code.
32 */
insn_has_rep_prefix(struct insn * insn)33 static bool insn_has_rep_prefix(struct insn *insn)
34 {
35 insn_byte_t p;
36 int i;
37
38 insn_get_prefixes(insn);
39
40 for_each_insn_prefix(insn, i, p) {
41 if (p == 0xf2 || p == 0xf3)
42 return true;
43 }
44
45 return false;
46 }
47
48 /*
49 * Only a dummy for insn_get_seg_base() - Early boot-code is 64bit only and
50 * doesn't use segments.
51 */
insn_get_seg_base(struct pt_regs * regs,int seg_reg_idx)52 static unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
53 {
54 return 0UL;
55 }
56
sev_es_rd_ghcb_msr(void)57 static inline u64 sev_es_rd_ghcb_msr(void)
58 {
59 unsigned long low, high;
60
61 asm volatile("rdmsr" : "=a" (low), "=d" (high) :
62 "c" (MSR_AMD64_SEV_ES_GHCB));
63
64 return ((high << 32) | low);
65 }
66
sev_es_wr_ghcb_msr(u64 val)67 static inline void sev_es_wr_ghcb_msr(u64 val)
68 {
69 u32 low, high;
70
71 low = val & 0xffffffffUL;
72 high = val >> 32;
73
74 asm volatile("wrmsr" : : "c" (MSR_AMD64_SEV_ES_GHCB),
75 "a"(low), "d" (high) : "memory");
76 }
77
vc_decode_insn(struct es_em_ctxt * ctxt)78 static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
79 {
80 char buffer[MAX_INSN_SIZE];
81 enum es_result ret;
82
83 memcpy(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);
84
85 insn_init(&ctxt->insn, buffer, MAX_INSN_SIZE, 1);
86 insn_get_length(&ctxt->insn);
87
88 ret = ctxt->insn.immediate.got ? ES_OK : ES_DECODE_FAILED;
89
90 return ret;
91 }
92
vc_write_mem(struct es_em_ctxt * ctxt,void * dst,char * buf,size_t size)93 static enum es_result vc_write_mem(struct es_em_ctxt *ctxt,
94 void *dst, char *buf, size_t size)
95 {
96 memcpy(dst, buf, size);
97
98 return ES_OK;
99 }
100
vc_read_mem(struct es_em_ctxt * ctxt,void * src,char * buf,size_t size)101 static enum es_result vc_read_mem(struct es_em_ctxt *ctxt,
102 void *src, char *buf, size_t size)
103 {
104 memcpy(buf, src, size);
105
106 return ES_OK;
107 }
108
vc_ioio_check(struct es_em_ctxt * ctxt,u16 port,size_t size)109 static enum es_result vc_ioio_check(struct es_em_ctxt *ctxt, u16 port, size_t size)
110 {
111 return ES_OK;
112 }
113
fault_in_kernel_space(unsigned long address)114 static bool fault_in_kernel_space(unsigned long address)
115 {
116 return false;
117 }
118
119 #undef __init
120 #undef __pa
121 #define __init
122 #define __pa(x) ((unsigned long)(x))
123
124 #define __BOOT_COMPRESSED
125
126 /* Basic instruction decoding support needed */
127 #include "../../lib/inat.c"
128 #include "../../lib/insn.c"
129
130 /* Include code for early handlers */
131 #include "../../kernel/sev-es-shared.c"
132
early_setup_sev_es(void)133 static bool early_setup_sev_es(void)
134 {
135 if (!sev_es_negotiate_protocol())
136 sev_es_terminate(GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED);
137
138 if (set_page_decrypted((unsigned long)&boot_ghcb_page))
139 return false;
140
141 /* Page is now mapped decrypted, clear it */
142 memset(&boot_ghcb_page, 0, sizeof(boot_ghcb_page));
143
144 boot_ghcb = &boot_ghcb_page;
145
146 /* Initialize lookup tables for the instruction decoder */
147 inat_init_tables();
148
149 return true;
150 }
151
sev_es_shutdown_ghcb(void)152 void sev_es_shutdown_ghcb(void)
153 {
154 if (!boot_ghcb)
155 return;
156
157 if (!sev_es_check_cpu_features())
158 error("SEV-ES CPU Features missing.");
159
160 /*
161 * GHCB Page must be flushed from the cache and mapped encrypted again.
162 * Otherwise the running kernel will see strange cache effects when
163 * trying to use that page.
164 */
165 if (set_page_encrypted((unsigned long)&boot_ghcb_page))
166 error("Can't map GHCB page encrypted");
167
168 /*
169 * GHCB page is mapped encrypted again and flushed from the cache.
170 * Mark it non-present now to catch bugs when #VC exceptions trigger
171 * after this point.
172 */
173 if (set_page_non_present((unsigned long)&boot_ghcb_page))
174 error("Can't unmap GHCB page");
175 }
176
sev_es_check_ghcb_fault(unsigned long address)177 bool sev_es_check_ghcb_fault(unsigned long address)
178 {
179 /* Check whether the fault was on the GHCB page */
180 return ((address & PAGE_MASK) == (unsigned long)&boot_ghcb_page);
181 }
182
do_boot_stage2_vc(struct pt_regs * regs,unsigned long exit_code)183 void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code)
184 {
185 struct es_em_ctxt ctxt;
186 enum es_result result;
187
188 if (!boot_ghcb && !early_setup_sev_es())
189 sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST);
190
191 vc_ghcb_invalidate(boot_ghcb);
192 result = vc_init_em_ctxt(&ctxt, regs, exit_code);
193 if (result != ES_OK)
194 goto finish;
195
196 switch (exit_code) {
197 case SVM_EXIT_RDTSC:
198 case SVM_EXIT_RDTSCP:
199 result = vc_handle_rdtsc(boot_ghcb, &ctxt, exit_code);
200 break;
201 case SVM_EXIT_IOIO:
202 result = vc_handle_ioio(boot_ghcb, &ctxt);
203 break;
204 case SVM_EXIT_CPUID:
205 result = vc_handle_cpuid(boot_ghcb, &ctxt);
206 break;
207 default:
208 result = ES_UNSUPPORTED;
209 break;
210 }
211
212 finish:
213 if (result == ES_OK) {
214 vc_finish_insn(&ctxt);
215 } else if (result != ES_RETRY) {
216 /*
217 * For now, just halt the machine. That makes debugging easier,
218 * later we just call sev_es_terminate() here.
219 */
220 while (true)
221 asm volatile("hlt\n");
222 }
223 }
224