1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6
7 #include <linux/io.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
13 #include <asm/apic.h>
14 #include <asm/cacheinfo.h>
15 #include <asm/cpu.h>
16 #include <asm/spec-ctrl.h>
17 #include <asm/smp.h>
18 #include <asm/numa.h>
19 #include <asm/pci-direct.h>
20 #include <asm/delay.h>
21 #include <asm/debugreg.h>
22 #include <asm/resctrl.h>
23
24 #ifdef CONFIG_X86_64
25 # include <asm/mmconfig.h>
26 # include <asm/set_memory.h>
27 #endif
28
29 #include "cpu.h"
30
31 /*
32 * nodes_per_socket: Stores the number of nodes per socket.
33 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
34 * Node Identifiers[10:8]
35 */
36 static u32 nodes_per_socket = 1;
37
38 /*
39 * AMD errata checking
40 *
41 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
42 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
43 * have an OSVW id assigned, which it takes as first argument. Both take a
44 * variable number of family-specific model-stepping ranges created by
45 * AMD_MODEL_RANGE().
46 *
47 * Example:
48 *
49 * const int amd_erratum_319[] =
50 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
51 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
52 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
53 */
54
55 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
56 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
57 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
58 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
59 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
60 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
61 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
62
63 static const int amd_erratum_400[] =
64 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
65 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
66
67 static const int amd_erratum_383[] =
68 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
69
70 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
71 static const int amd_erratum_1054[] =
72 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
73
74 static const int amd_zenbleed[] =
75 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
76 AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
77 AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
78 AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
79
80 static const int amd_div0[] =
81 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
82 AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
83
84 static const int amd_erratum_1485[] =
85 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
86 AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
87
cpu_has_amd_erratum(struct cpuinfo_x86 * cpu,const int * erratum)88 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
89 {
90 int osvw_id = *erratum++;
91 u32 range;
92 u32 ms;
93
94 if (osvw_id >= 0 && osvw_id < 65536 &&
95 cpu_has(cpu, X86_FEATURE_OSVW)) {
96 u64 osvw_len;
97
98 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
99 if (osvw_id < osvw_len) {
100 u64 osvw_bits;
101
102 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
103 osvw_bits);
104 return osvw_bits & (1ULL << (osvw_id & 0x3f));
105 }
106 }
107
108 /* OSVW unavailable or ID unknown, match family-model-stepping range */
109 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
110 while ((range = *erratum++))
111 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
112 (ms >= AMD_MODEL_RANGE_START(range)) &&
113 (ms <= AMD_MODEL_RANGE_END(range)))
114 return true;
115
116 return false;
117 }
118
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)119 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
120 {
121 u32 gprs[8] = { 0 };
122 int err;
123
124 WARN_ONCE((boot_cpu_data.x86 != 0xf),
125 "%s should only be used on K8!\n", __func__);
126
127 gprs[1] = msr;
128 gprs[7] = 0x9c5a203a;
129
130 err = rdmsr_safe_regs(gprs);
131
132 *p = gprs[0] | ((u64)gprs[2] << 32);
133
134 return err;
135 }
136
wrmsrl_amd_safe(unsigned msr,unsigned long long val)137 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
138 {
139 u32 gprs[8] = { 0 };
140
141 WARN_ONCE((boot_cpu_data.x86 != 0xf),
142 "%s should only be used on K8!\n", __func__);
143
144 gprs[0] = (u32)val;
145 gprs[1] = msr;
146 gprs[2] = val >> 32;
147 gprs[7] = 0x9c5a203a;
148
149 return wrmsr_safe_regs(gprs);
150 }
151
152 /*
153 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
154 * misexecution of code under Linux. Owners of such processors should
155 * contact AMD for precise details and a CPU swap.
156 *
157 * See http://www.multimania.com/poulot/k6bug.html
158 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
159 * (Publication # 21266 Issue Date: August 1998)
160 *
161 * The following test is erm.. interesting. AMD neglected to up
162 * the chip setting when fixing the bug but they also tweaked some
163 * performance at the same time..
164 */
165
166 #ifdef CONFIG_X86_32
167 extern __visible void vide(void);
168 __asm__(".text\n"
169 ".globl vide\n"
170 ".type vide, @function\n"
171 ".align 4\n"
172 "vide: ret\n");
173 #endif
174
init_amd_k5(struct cpuinfo_x86 * c)175 static void init_amd_k5(struct cpuinfo_x86 *c)
176 {
177 #ifdef CONFIG_X86_32
178 /*
179 * General Systems BIOSen alias the cpu frequency registers
180 * of the Elan at 0x000df000. Unfortunately, one of the Linux
181 * drivers subsequently pokes it, and changes the CPU speed.
182 * Workaround : Remove the unneeded alias.
183 */
184 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
185 #define CBAR_ENB (0x80000000)
186 #define CBAR_KEY (0X000000CB)
187 if (c->x86_model == 9 || c->x86_model == 10) {
188 if (inl(CBAR) & CBAR_ENB)
189 outl(0 | CBAR_KEY, CBAR);
190 }
191 #endif
192 }
193
init_amd_k6(struct cpuinfo_x86 * c)194 static void init_amd_k6(struct cpuinfo_x86 *c)
195 {
196 #ifdef CONFIG_X86_32
197 u32 l, h;
198 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
199
200 if (c->x86_model < 6) {
201 /* Based on AMD doc 20734R - June 2000 */
202 if (c->x86_model == 0) {
203 clear_cpu_cap(c, X86_FEATURE_APIC);
204 set_cpu_cap(c, X86_FEATURE_PGE);
205 }
206 return;
207 }
208
209 if (c->x86_model == 6 && c->x86_stepping == 1) {
210 const int K6_BUG_LOOP = 1000000;
211 int n;
212 void (*f_vide)(void);
213 u64 d, d2;
214
215 pr_info("AMD K6 stepping B detected - ");
216
217 /*
218 * It looks like AMD fixed the 2.6.2 bug and improved indirect
219 * calls at the same time.
220 */
221
222 n = K6_BUG_LOOP;
223 f_vide = vide;
224 OPTIMIZER_HIDE_VAR(f_vide);
225 d = rdtsc();
226 while (n--)
227 f_vide();
228 d2 = rdtsc();
229 d = d2-d;
230
231 if (d > 20*K6_BUG_LOOP)
232 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
233 else
234 pr_cont("probably OK (after B9730xxxx).\n");
235 }
236
237 /* K6 with old style WHCR */
238 if (c->x86_model < 8 ||
239 (c->x86_model == 8 && c->x86_stepping < 8)) {
240 /* We can only write allocate on the low 508Mb */
241 if (mbytes > 508)
242 mbytes = 508;
243
244 rdmsr(MSR_K6_WHCR, l, h);
245 if ((l&0x0000FFFF) == 0) {
246 unsigned long flags;
247 l = (1<<0)|((mbytes/4)<<1);
248 local_irq_save(flags);
249 wbinvd();
250 wrmsr(MSR_K6_WHCR, l, h);
251 local_irq_restore(flags);
252 pr_info("Enabling old style K6 write allocation for %d Mb\n",
253 mbytes);
254 }
255 return;
256 }
257
258 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
259 c->x86_model == 9 || c->x86_model == 13) {
260 /* The more serious chips .. */
261
262 if (mbytes > 4092)
263 mbytes = 4092;
264
265 rdmsr(MSR_K6_WHCR, l, h);
266 if ((l&0xFFFF0000) == 0) {
267 unsigned long flags;
268 l = ((mbytes>>2)<<22)|(1<<16);
269 local_irq_save(flags);
270 wbinvd();
271 wrmsr(MSR_K6_WHCR, l, h);
272 local_irq_restore(flags);
273 pr_info("Enabling new style K6 write allocation for %d Mb\n",
274 mbytes);
275 }
276
277 return;
278 }
279
280 if (c->x86_model == 10) {
281 /* AMD Geode LX is model 10 */
282 /* placeholder for any needed mods */
283 return;
284 }
285 #endif
286 }
287
init_amd_k7(struct cpuinfo_x86 * c)288 static void init_amd_k7(struct cpuinfo_x86 *c)
289 {
290 #ifdef CONFIG_X86_32
291 u32 l, h;
292
293 /*
294 * Bit 15 of Athlon specific MSR 15, needs to be 0
295 * to enable SSE on Palomino/Morgan/Barton CPU's.
296 * If the BIOS didn't enable it already, enable it here.
297 */
298 if (c->x86_model >= 6 && c->x86_model <= 10) {
299 if (!cpu_has(c, X86_FEATURE_XMM)) {
300 pr_info("Enabling disabled K7/SSE Support.\n");
301 msr_clear_bit(MSR_K7_HWCR, 15);
302 set_cpu_cap(c, X86_FEATURE_XMM);
303 }
304 }
305
306 /*
307 * It's been determined by AMD that Athlons since model 8 stepping 1
308 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
309 * As per AMD technical note 27212 0.2
310 */
311 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
312 rdmsr(MSR_K7_CLK_CTL, l, h);
313 if ((l & 0xfff00000) != 0x20000000) {
314 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
315 l, ((l & 0x000fffff)|0x20000000));
316 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
317 }
318 }
319
320 /* calling is from identify_secondary_cpu() ? */
321 if (!c->cpu_index)
322 return;
323
324 /*
325 * Certain Athlons might work (for various values of 'work') in SMP
326 * but they are not certified as MP capable.
327 */
328 /* Athlon 660/661 is valid. */
329 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
330 (c->x86_stepping == 1)))
331 return;
332
333 /* Duron 670 is valid */
334 if ((c->x86_model == 7) && (c->x86_stepping == 0))
335 return;
336
337 /*
338 * Athlon 662, Duron 671, and Athlon >model 7 have capability
339 * bit. It's worth noting that the A5 stepping (662) of some
340 * Athlon XP's have the MP bit set.
341 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
342 * more.
343 */
344 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
345 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
346 (c->x86_model > 7))
347 if (cpu_has(c, X86_FEATURE_MP))
348 return;
349
350 /* If we get here, not a certified SMP capable AMD system. */
351
352 /*
353 * Don't taint if we are running SMP kernel on a single non-MP
354 * approved Athlon
355 */
356 WARN_ONCE(1, "WARNING: This combination of AMD"
357 " processors is not suitable for SMP.\n");
358 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
359 #endif
360 }
361
362 #ifdef CONFIG_NUMA
363 /*
364 * To workaround broken NUMA config. Read the comment in
365 * srat_detect_node().
366 */
nearby_node(int apicid)367 static int nearby_node(int apicid)
368 {
369 int i, node;
370
371 for (i = apicid - 1; i >= 0; i--) {
372 node = __apicid_to_node[i];
373 if (node != NUMA_NO_NODE && node_online(node))
374 return node;
375 }
376 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
377 node = __apicid_to_node[i];
378 if (node != NUMA_NO_NODE && node_online(node))
379 return node;
380 }
381 return first_node(node_online_map); /* Shouldn't happen */
382 }
383 #endif
384
385 /*
386 * Fix up cpu_core_id for pre-F17h systems to be in the
387 * [0 .. cores_per_node - 1] range. Not really needed but
388 * kept so as not to break existing setups.
389 */
legacy_fixup_core_id(struct cpuinfo_x86 * c)390 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
391 {
392 u32 cus_per_node;
393
394 if (c->x86 >= 0x17)
395 return;
396
397 cus_per_node = c->x86_max_cores / nodes_per_socket;
398 c->cpu_core_id %= cus_per_node;
399 }
400
401 /*
402 * Fixup core topology information for
403 * (1) AMD multi-node processors
404 * Assumption: Number of cores in each internal node is the same.
405 * (2) AMD processors supporting compute units
406 */
amd_get_topology(struct cpuinfo_x86 * c)407 static void amd_get_topology(struct cpuinfo_x86 *c)
408 {
409 int cpu = smp_processor_id();
410
411 /* get information required for multi-node processors */
412 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
413 int err;
414 u32 eax, ebx, ecx, edx;
415
416 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
417
418 c->cpu_die_id = ecx & 0xff;
419
420 if (c->x86 == 0x15)
421 c->cu_id = ebx & 0xff;
422
423 if (c->x86 >= 0x17) {
424 c->cpu_core_id = ebx & 0xff;
425
426 if (smp_num_siblings > 1)
427 c->x86_max_cores /= smp_num_siblings;
428 }
429
430 /*
431 * In case leaf B is available, use it to derive
432 * topology information.
433 */
434 err = detect_extended_topology(c);
435 if (!err)
436 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
437
438 cacheinfo_amd_init_llc_id(c, cpu);
439
440 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
441 u64 value;
442
443 rdmsrl(MSR_FAM10H_NODE_ID, value);
444 c->cpu_die_id = value & 7;
445
446 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
447 } else
448 return;
449
450 if (nodes_per_socket > 1) {
451 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
452 legacy_fixup_core_id(c);
453 }
454 }
455
456 /*
457 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
458 * Assumes number of cores is a power of two.
459 */
amd_detect_cmp(struct cpuinfo_x86 * c)460 static void amd_detect_cmp(struct cpuinfo_x86 *c)
461 {
462 unsigned bits;
463 int cpu = smp_processor_id();
464
465 bits = c->x86_coreid_bits;
466 /* Low order bits define the core id (index of core in socket) */
467 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
468 /* Convert the initial APIC ID into the socket ID */
469 c->phys_proc_id = c->initial_apicid >> bits;
470 /* use socket ID also for last level cache */
471 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
472 }
473
amd_detect_ppin(struct cpuinfo_x86 * c)474 static void amd_detect_ppin(struct cpuinfo_x86 *c)
475 {
476 unsigned long long val;
477
478 if (!cpu_has(c, X86_FEATURE_AMD_PPIN))
479 return;
480
481 /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */
482 if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val))
483 goto clear_ppin;
484
485 /* PPIN is locked in disabled mode, clear feature bit */
486 if ((val & 3UL) == 1UL)
487 goto clear_ppin;
488
489 /* If PPIN is disabled, try to enable it */
490 if (!(val & 2UL)) {
491 wrmsrl_safe(MSR_AMD_PPIN_CTL, val | 2UL);
492 rdmsrl_safe(MSR_AMD_PPIN_CTL, &val);
493 }
494
495 /* If PPIN_EN bit is 1, return from here; otherwise fall through */
496 if (val & 2UL)
497 return;
498
499 clear_ppin:
500 clear_cpu_cap(c, X86_FEATURE_AMD_PPIN);
501 }
502
amd_get_nb_id(int cpu)503 u16 amd_get_nb_id(int cpu)
504 {
505 return per_cpu(cpu_llc_id, cpu);
506 }
507 EXPORT_SYMBOL_GPL(amd_get_nb_id);
508
amd_get_nodes_per_socket(void)509 u32 amd_get_nodes_per_socket(void)
510 {
511 return nodes_per_socket;
512 }
513 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
514
srat_detect_node(struct cpuinfo_x86 * c)515 static void srat_detect_node(struct cpuinfo_x86 *c)
516 {
517 #ifdef CONFIG_NUMA
518 int cpu = smp_processor_id();
519 int node;
520 unsigned apicid = c->apicid;
521
522 node = numa_cpu_node(cpu);
523 if (node == NUMA_NO_NODE)
524 node = per_cpu(cpu_llc_id, cpu);
525
526 /*
527 * On multi-fabric platform (e.g. Numascale NumaChip) a
528 * platform-specific handler needs to be called to fixup some
529 * IDs of the CPU.
530 */
531 if (x86_cpuinit.fixup_cpu_id)
532 x86_cpuinit.fixup_cpu_id(c, node);
533
534 if (!node_online(node)) {
535 /*
536 * Two possibilities here:
537 *
538 * - The CPU is missing memory and no node was created. In
539 * that case try picking one from a nearby CPU.
540 *
541 * - The APIC IDs differ from the HyperTransport node IDs
542 * which the K8 northbridge parsing fills in. Assume
543 * they are all increased by a constant offset, but in
544 * the same order as the HT nodeids. If that doesn't
545 * result in a usable node fall back to the path for the
546 * previous case.
547 *
548 * This workaround operates directly on the mapping between
549 * APIC ID and NUMA node, assuming certain relationship
550 * between APIC ID, HT node ID and NUMA topology. As going
551 * through CPU mapping may alter the outcome, directly
552 * access __apicid_to_node[].
553 */
554 int ht_nodeid = c->initial_apicid;
555
556 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
557 node = __apicid_to_node[ht_nodeid];
558 /* Pick a nearby node */
559 if (!node_online(node))
560 node = nearby_node(apicid);
561 }
562 numa_set_node(cpu, node);
563 #endif
564 }
565
early_init_amd_mc(struct cpuinfo_x86 * c)566 static void early_init_amd_mc(struct cpuinfo_x86 *c)
567 {
568 #ifdef CONFIG_SMP
569 unsigned bits, ecx;
570
571 /* Multi core CPU? */
572 if (c->extended_cpuid_level < 0x80000008)
573 return;
574
575 ecx = cpuid_ecx(0x80000008);
576
577 c->x86_max_cores = (ecx & 0xff) + 1;
578
579 /* CPU telling us the core id bits shift? */
580 bits = (ecx >> 12) & 0xF;
581
582 /* Otherwise recompute */
583 if (bits == 0) {
584 while ((1 << bits) < c->x86_max_cores)
585 bits++;
586 }
587
588 c->x86_coreid_bits = bits;
589 #endif
590 }
591
bsp_init_amd(struct cpuinfo_x86 * c)592 static void bsp_init_amd(struct cpuinfo_x86 *c)
593 {
594
595 #ifdef CONFIG_X86_64
596 if (c->x86 >= 0xf) {
597 unsigned long long tseg;
598
599 /*
600 * Split up direct mapping around the TSEG SMM area.
601 * Don't do it for gbpages because there seems very little
602 * benefit in doing so.
603 */
604 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
605 unsigned long pfn = tseg >> PAGE_SHIFT;
606
607 pr_debug("tseg: %010llx\n", tseg);
608 if (pfn_range_is_mapped(pfn, pfn + 1))
609 set_memory_4k((unsigned long)__va(tseg), 1);
610 }
611 }
612 #endif
613
614 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
615
616 if (c->x86 > 0x10 ||
617 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
618 u64 val;
619
620 rdmsrl(MSR_K7_HWCR, val);
621 if (!(val & BIT(24)))
622 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
623 }
624 }
625
626 if (c->x86 == 0x15) {
627 unsigned long upperbit;
628 u32 cpuid, assoc;
629
630 cpuid = cpuid_edx(0x80000005);
631 assoc = cpuid >> 16 & 0xff;
632 upperbit = ((cpuid >> 24) << 10) / assoc;
633
634 va_align.mask = (upperbit - 1) & PAGE_MASK;
635 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
636
637 /* A random value per boot for bit slice [12:upper_bit) */
638 va_align.bits = get_random_int() & va_align.mask;
639 }
640
641 if (cpu_has(c, X86_FEATURE_MWAITX))
642 use_mwaitx_delay();
643
644 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
645 u32 ecx;
646
647 ecx = cpuid_ecx(0x8000001e);
648 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
649 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
650 u64 value;
651
652 rdmsrl(MSR_FAM10H_NODE_ID, value);
653 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
654 }
655
656 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
657 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
658 c->x86 >= 0x15 && c->x86 <= 0x17) {
659 unsigned int bit;
660
661 switch (c->x86) {
662 case 0x15: bit = 54; break;
663 case 0x16: bit = 33; break;
664 case 0x17: bit = 10; break;
665 default: return;
666 }
667 /*
668 * Try to cache the base value so further operations can
669 * avoid RMW. If that faults, do not enable SSBD.
670 */
671 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
672 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
673 setup_force_cpu_cap(X86_FEATURE_SSBD);
674 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
675 }
676 }
677
678 resctrl_cpu_detect(c);
679 }
680
early_detect_mem_encrypt(struct cpuinfo_x86 * c)681 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
682 {
683 u64 msr;
684
685 /*
686 * BIOS support is required for SME and SEV.
687 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
688 * the SME physical address space reduction value.
689 * If BIOS has not enabled SME then don't advertise the
690 * SME feature (set in scattered.c).
691 * For SEV: If BIOS has not enabled SEV then don't advertise the
692 * SEV and SEV_ES feature (set in scattered.c).
693 *
694 * In all cases, since support for SME and SEV requires long mode,
695 * don't advertise the feature under CONFIG_X86_32.
696 */
697 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
698 /* Check if memory encryption is enabled */
699 rdmsrl(MSR_K8_SYSCFG, msr);
700 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
701 goto clear_all;
702
703 /*
704 * Always adjust physical address bits. Even though this
705 * will be a value above 32-bits this is still done for
706 * CONFIG_X86_32 so that accurate values are reported.
707 */
708 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
709
710 if (IS_ENABLED(CONFIG_X86_32))
711 goto clear_all;
712
713 rdmsrl(MSR_K7_HWCR, msr);
714 if (!(msr & MSR_K7_HWCR_SMMLOCK))
715 goto clear_sev;
716
717 return;
718
719 clear_all:
720 setup_clear_cpu_cap(X86_FEATURE_SME);
721 clear_sev:
722 setup_clear_cpu_cap(X86_FEATURE_SEV);
723 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
724 }
725 }
726
early_init_amd(struct cpuinfo_x86 * c)727 static void early_init_amd(struct cpuinfo_x86 *c)
728 {
729 u64 value;
730 u32 dummy;
731
732 early_init_amd_mc(c);
733
734 #ifdef CONFIG_X86_32
735 if (c->x86 == 6)
736 set_cpu_cap(c, X86_FEATURE_K7);
737 #endif
738
739 if (c->x86 >= 0xf)
740 set_cpu_cap(c, X86_FEATURE_K8);
741
742 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
743
744 /*
745 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
746 * with P/T states and does not stop in deep C-states
747 */
748 if (c->x86_power & (1 << 8)) {
749 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
750 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
751 }
752
753 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
754 if (c->x86_power & BIT(12))
755 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
756
757 #ifdef CONFIG_X86_64
758 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
759 #else
760 /* Set MTRR capability flag if appropriate */
761 if (c->x86 == 5)
762 if (c->x86_model == 13 || c->x86_model == 9 ||
763 (c->x86_model == 8 && c->x86_stepping >= 8))
764 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
765 #endif
766 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
767 /*
768 * ApicID can always be treated as an 8-bit value for AMD APIC versions
769 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
770 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
771 * after 16h.
772 */
773 if (boot_cpu_has(X86_FEATURE_APIC)) {
774 if (c->x86 > 0x16)
775 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
776 else if (c->x86 >= 0xf) {
777 /* check CPU config space for extended APIC ID */
778 unsigned int val;
779
780 val = read_pci_config(0, 24, 0, 0x68);
781 if ((val >> 17 & 0x3) == 0x3)
782 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
783 }
784 }
785 #endif
786
787 /*
788 * This is only needed to tell the kernel whether to use VMCALL
789 * and VMMCALL. VMMCALL is never executed except under virt, so
790 * we can set it unconditionally.
791 */
792 set_cpu_cap(c, X86_FEATURE_VMMCALL);
793
794 /* F16h erratum 793, CVE-2013-6885 */
795 if (c->x86 == 0x16 && c->x86_model <= 0xf)
796 msr_set_bit(MSR_AMD64_LS_CFG, 15);
797
798 /*
799 * Check whether the machine is affected by erratum 400. This is
800 * used to select the proper idle routine and to enable the check
801 * whether the machine is affected in arch_post_acpi_init(), which
802 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
803 */
804 if (cpu_has_amd_erratum(c, amd_erratum_400))
805 set_cpu_bug(c, X86_BUG_AMD_E400);
806
807 early_detect_mem_encrypt(c);
808
809 /* Re-enable TopologyExtensions if switched off by BIOS */
810 if (c->x86 == 0x15 &&
811 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
812 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
813
814 if (msr_set_bit(0xc0011005, 54) > 0) {
815 rdmsrl(0xc0011005, value);
816 if (value & BIT_64(54)) {
817 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
818 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
819 }
820 }
821 }
822
823 if (cpu_has(c, X86_FEATURE_TOPOEXT))
824 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
825 }
826
init_amd_k8(struct cpuinfo_x86 * c)827 static void init_amd_k8(struct cpuinfo_x86 *c)
828 {
829 u32 level;
830 u64 value;
831
832 /* On C+ stepping K8 rep microcode works well for copy/memset */
833 level = cpuid_eax(1);
834 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
835 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
836
837 /*
838 * Some BIOSes incorrectly force this feature, but only K8 revision D
839 * (model = 0x14) and later actually support it.
840 * (AMD Erratum #110, docId: 25759).
841 */
842 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
843 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
844 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
845 value &= ~BIT_64(32);
846 wrmsrl_amd_safe(0xc001100d, value);
847 }
848 }
849
850 if (!c->x86_model_id[0])
851 strcpy(c->x86_model_id, "Hammer");
852
853 #ifdef CONFIG_SMP
854 /*
855 * Disable TLB flush filter by setting HWCR.FFDIS on K8
856 * bit 6 of msr C001_0015
857 *
858 * Errata 63 for SH-B3 steppings
859 * Errata 122 for all steppings (F+ have it disabled by default)
860 */
861 msr_set_bit(MSR_K7_HWCR, 6);
862 #endif
863 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
864 }
865
init_amd_gh(struct cpuinfo_x86 * c)866 static void init_amd_gh(struct cpuinfo_x86 *c)
867 {
868 #ifdef CONFIG_MMCONF_FAM10H
869 /* do this for boot cpu */
870 if (c == &boot_cpu_data)
871 check_enable_amd_mmconf_dmi();
872
873 fam10h_check_enable_mmcfg();
874 #endif
875
876 /*
877 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
878 * is always needed when GART is enabled, even in a kernel which has no
879 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
880 * If it doesn't, we do it here as suggested by the BKDG.
881 *
882 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
883 */
884 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
885
886 /*
887 * On family 10h BIOS may not have properly enabled WC+ support, causing
888 * it to be converted to CD memtype. This may result in performance
889 * degradation for certain nested-paging guests. Prevent this conversion
890 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
891 *
892 * NOTE: we want to use the _safe accessors so as not to #GP kvm
893 * guests on older kvm hosts.
894 */
895 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
896
897 if (cpu_has_amd_erratum(c, amd_erratum_383))
898 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
899 }
900
init_amd_ln(struct cpuinfo_x86 * c)901 static void init_amd_ln(struct cpuinfo_x86 *c)
902 {
903 /*
904 * Apply erratum 665 fix unconditionally so machines without a BIOS
905 * fix work.
906 */
907 msr_set_bit(MSR_AMD64_DE_CFG, 31);
908 }
909
910 static bool rdrand_force;
911
rdrand_cmdline(char * str)912 static int __init rdrand_cmdline(char *str)
913 {
914 if (!str)
915 return -EINVAL;
916
917 if (!strcmp(str, "force"))
918 rdrand_force = true;
919 else
920 return -EINVAL;
921
922 return 0;
923 }
924 early_param("rdrand", rdrand_cmdline);
925
clear_rdrand_cpuid_bit(struct cpuinfo_x86 * c)926 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
927 {
928 /*
929 * Saving of the MSR used to hide the RDRAND support during
930 * suspend/resume is done by arch/x86/power/cpu.c, which is
931 * dependent on CONFIG_PM_SLEEP.
932 */
933 if (!IS_ENABLED(CONFIG_PM_SLEEP))
934 return;
935
936 /*
937 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
938 * RDRAND support using the CPUID function directly.
939 */
940 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
941 return;
942
943 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
944
945 /*
946 * Verify that the CPUID change has occurred in case the kernel is
947 * running virtualized and the hypervisor doesn't support the MSR.
948 */
949 if (cpuid_ecx(1) & BIT(30)) {
950 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
951 return;
952 }
953
954 clear_cpu_cap(c, X86_FEATURE_RDRAND);
955 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
956 }
957
init_amd_jg(struct cpuinfo_x86 * c)958 static void init_amd_jg(struct cpuinfo_x86 *c)
959 {
960 /*
961 * Some BIOS implementations do not restore proper RDRAND support
962 * across suspend and resume. Check on whether to hide the RDRAND
963 * instruction support via CPUID.
964 */
965 clear_rdrand_cpuid_bit(c);
966 }
967
init_amd_bd(struct cpuinfo_x86 * c)968 static void init_amd_bd(struct cpuinfo_x86 *c)
969 {
970 u64 value;
971
972 /*
973 * The way access filter has a performance penalty on some workloads.
974 * Disable it on the affected CPUs.
975 */
976 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
977 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
978 value |= 0x1E;
979 wrmsrl_safe(MSR_F15H_IC_CFG, value);
980 }
981 }
982
983 /*
984 * Some BIOS implementations do not restore proper RDRAND support
985 * across suspend and resume. Check on whether to hide the RDRAND
986 * instruction support via CPUID.
987 */
988 clear_rdrand_cpuid_bit(c);
989 }
990
init_spectral_chicken(struct cpuinfo_x86 * c)991 void init_spectral_chicken(struct cpuinfo_x86 *c)
992 {
993 #ifdef CONFIG_CPU_UNRET_ENTRY
994 u64 value;
995
996 /*
997 * On Zen2 we offer this chicken (bit) on the altar of Speculation.
998 *
999 * This suppresses speculation from the middle of a basic block, i.e. it
1000 * suppresses non-branch predictions.
1001 *
1002 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
1003 */
1004 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
1005 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
1006 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
1007 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
1008 }
1009 }
1010 #endif
1011 /*
1012 * Work around Erratum 1386. The XSAVES instruction malfunctions in
1013 * certain circumstances on Zen1/2 uarch, and not all parts have had
1014 * updated microcode at the time of writing (March 2023).
1015 *
1016 * Affected parts all have no supervisor XSAVE states, meaning that
1017 * the XSAVEC instruction (which works fine) is equivalent.
1018 */
1019 clear_cpu_cap(c, X86_FEATURE_XSAVES);
1020 }
1021
init_amd_zn(struct cpuinfo_x86 * c)1022 static void init_amd_zn(struct cpuinfo_x86 *c)
1023 {
1024 set_cpu_cap(c, X86_FEATURE_ZEN);
1025
1026 #ifdef CONFIG_NUMA
1027 node_reclaim_distance = 32;
1028 #endif
1029
1030 /* Fix up CPUID bits, but only if not virtualised. */
1031 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1032
1033 /* Erratum 1076: CPB feature bit not being set in CPUID. */
1034 if (!cpu_has(c, X86_FEATURE_CPB))
1035 set_cpu_cap(c, X86_FEATURE_CPB);
1036
1037 /*
1038 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
1039 * Branch Type Confusion, but predate the allocation of the
1040 * BTC_NO bit.
1041 */
1042 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
1043 set_cpu_cap(c, X86_FEATURE_BTC_NO);
1044 }
1045 }
1046
cpu_has_zenbleed_microcode(void)1047 static bool cpu_has_zenbleed_microcode(void)
1048 {
1049 u32 good_rev = 0;
1050
1051 switch (boot_cpu_data.x86_model) {
1052 case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
1053 case 0x60 ... 0x67: good_rev = 0x0860010b; break;
1054 case 0x68 ... 0x6f: good_rev = 0x08608105; break;
1055 case 0x70 ... 0x7f: good_rev = 0x08701032; break;
1056 case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
1057
1058 default:
1059 return false;
1060 break;
1061 }
1062
1063 if (boot_cpu_data.microcode < good_rev)
1064 return false;
1065
1066 return true;
1067 }
1068
zenbleed_check(struct cpuinfo_x86 * c)1069 static void zenbleed_check(struct cpuinfo_x86 *c)
1070 {
1071 if (!cpu_has_amd_erratum(c, amd_zenbleed))
1072 return;
1073
1074 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
1075 return;
1076
1077 if (!cpu_has(c, X86_FEATURE_AVX))
1078 return;
1079
1080 if (!cpu_has_zenbleed_microcode()) {
1081 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
1082 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1083 } else {
1084 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1085 }
1086 }
1087
init_amd(struct cpuinfo_x86 * c)1088 static void init_amd(struct cpuinfo_x86 *c)
1089 {
1090 early_init_amd(c);
1091
1092 /*
1093 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1094 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
1095 */
1096 clear_cpu_cap(c, 0*32+31);
1097
1098 if (c->x86 >= 0x10)
1099 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1100
1101 /* get apicid instead of initial apic id from cpuid */
1102 c->apicid = hard_smp_processor_id();
1103
1104 /* K6s reports MCEs but don't actually have all the MSRs */
1105 if (c->x86 < 6)
1106 clear_cpu_cap(c, X86_FEATURE_MCE);
1107
1108 switch (c->x86) {
1109 case 4: init_amd_k5(c); break;
1110 case 5: init_amd_k6(c); break;
1111 case 6: init_amd_k7(c); break;
1112 case 0xf: init_amd_k8(c); break;
1113 case 0x10: init_amd_gh(c); break;
1114 case 0x12: init_amd_ln(c); break;
1115 case 0x15: init_amd_bd(c); break;
1116 case 0x16: init_amd_jg(c); break;
1117 case 0x17: init_spectral_chicken(c);
1118 fallthrough;
1119 case 0x19: init_amd_zn(c); break;
1120 }
1121
1122 /*
1123 * Enable workaround for FXSAVE leak on CPUs
1124 * without a XSaveErPtr feature
1125 */
1126 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1127 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1128
1129 cpu_detect_cache_sizes(c);
1130
1131 amd_detect_cmp(c);
1132 amd_get_topology(c);
1133 srat_detect_node(c);
1134 amd_detect_ppin(c);
1135
1136 init_amd_cacheinfo(c);
1137
1138 if (cpu_has(c, X86_FEATURE_XMM2)) {
1139 /*
1140 * Use LFENCE for execution serialization. On families which
1141 * don't have that MSR, LFENCE is already serializing.
1142 * msr_set_bit() uses the safe accessors, too, even if the MSR
1143 * is not present.
1144 */
1145 msr_set_bit(MSR_AMD64_DE_CFG,
1146 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1147
1148 /* A serializing LFENCE stops RDTSC speculation */
1149 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1150 }
1151
1152 /*
1153 * Family 0x12 and above processors have APIC timer
1154 * running in deep C states.
1155 */
1156 if (c->x86 > 0x11)
1157 set_cpu_cap(c, X86_FEATURE_ARAT);
1158
1159 /* 3DNow or LM implies PREFETCHW */
1160 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1161 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1162 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1163
1164 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1165 if (!cpu_has(c, X86_FEATURE_XENPV))
1166 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1167
1168 /*
1169 * Turn on the Instructions Retired free counter on machines not
1170 * susceptible to erratum #1054 "Instructions Retired Performance
1171 * Counter May Be Inaccurate".
1172 */
1173 if (cpu_has(c, X86_FEATURE_IRPERF) &&
1174 !cpu_has_amd_erratum(c, amd_erratum_1054))
1175 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1176
1177 check_null_seg_clears_base(c);
1178
1179 zenbleed_check(c);
1180
1181 if (cpu_has_amd_erratum(c, amd_div0)) {
1182 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
1183 setup_force_cpu_bug(X86_BUG_DIV0);
1184 }
1185
1186 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
1187 cpu_has_amd_erratum(c, amd_erratum_1485))
1188 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
1189 }
1190
1191 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)1192 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1193 {
1194 /* AMD errata T13 (order #21922) */
1195 if (c->x86 == 6) {
1196 /* Duron Rev A0 */
1197 if (c->x86_model == 3 && c->x86_stepping == 0)
1198 size = 64;
1199 /* Tbird rev A1/A2 */
1200 if (c->x86_model == 4 &&
1201 (c->x86_stepping == 0 || c->x86_stepping == 1))
1202 size = 256;
1203 }
1204 return size;
1205 }
1206 #endif
1207
cpu_detect_tlb_amd(struct cpuinfo_x86 * c)1208 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1209 {
1210 u32 ebx, eax, ecx, edx;
1211 u16 mask = 0xfff;
1212
1213 if (c->x86 < 0xf)
1214 return;
1215
1216 if (c->extended_cpuid_level < 0x80000006)
1217 return;
1218
1219 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1220
1221 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1222 tlb_lli_4k[ENTRIES] = ebx & mask;
1223
1224 /*
1225 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1226 * characteristics from the CPUID function 0x80000005 instead.
1227 */
1228 if (c->x86 == 0xf) {
1229 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1230 mask = 0xff;
1231 }
1232
1233 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1234 if (!((eax >> 16) & mask))
1235 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1236 else
1237 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1238
1239 /* a 4M entry uses two 2M entries */
1240 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1241
1242 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1243 if (!(eax & mask)) {
1244 /* Erratum 658 */
1245 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1246 tlb_lli_2m[ENTRIES] = 1024;
1247 } else {
1248 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1249 tlb_lli_2m[ENTRIES] = eax & 0xff;
1250 }
1251 } else
1252 tlb_lli_2m[ENTRIES] = eax & mask;
1253
1254 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1255 }
1256
1257 static const struct cpu_dev amd_cpu_dev = {
1258 .c_vendor = "AMD",
1259 .c_ident = { "AuthenticAMD" },
1260 #ifdef CONFIG_X86_32
1261 .legacy_models = {
1262 { .family = 4, .model_names =
1263 {
1264 [3] = "486 DX/2",
1265 [7] = "486 DX/2-WB",
1266 [8] = "486 DX/4",
1267 [9] = "486 DX/4-WB",
1268 [14] = "Am5x86-WT",
1269 [15] = "Am5x86-WB"
1270 }
1271 },
1272 },
1273 .legacy_cache_size = amd_size_cache,
1274 #endif
1275 .c_early_init = early_init_amd,
1276 .c_detect_tlb = cpu_detect_tlb_amd,
1277 .c_bsp_init = bsp_init_amd,
1278 .c_init = init_amd,
1279 .c_x86_vendor = X86_VENDOR_AMD,
1280 };
1281
1282 cpu_dev_register(amd_cpu_dev);
1283
set_dr_addr_mask(unsigned long mask,int dr)1284 void set_dr_addr_mask(unsigned long mask, int dr)
1285 {
1286 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1287 return;
1288
1289 switch (dr) {
1290 case 0:
1291 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1292 break;
1293 case 1:
1294 case 2:
1295 case 3:
1296 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1297 break;
1298 default:
1299 break;
1300 }
1301 }
1302
cpu_has_ibpb_brtype_microcode(void)1303 bool cpu_has_ibpb_brtype_microcode(void)
1304 {
1305 switch (boot_cpu_data.x86) {
1306 /* Zen1/2 IBPB flushes branch type predictions too. */
1307 case 0x17:
1308 return boot_cpu_has(X86_FEATURE_AMD_IBPB);
1309 case 0x19:
1310 /* Poke the MSR bit on Zen3/4 to check its presence. */
1311 if (!wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {
1312 setup_force_cpu_cap(X86_FEATURE_SBPB);
1313 return true;
1314 } else {
1315 return false;
1316 }
1317 default:
1318 return false;
1319 }
1320 }
1321
zenbleed_check_cpu(void * unused)1322 static void zenbleed_check_cpu(void *unused)
1323 {
1324 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
1325
1326 zenbleed_check(c);
1327 }
1328
amd_check_microcode(void)1329 void amd_check_microcode(void)
1330 {
1331 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
1332 return;
1333
1334 on_each_cpu(zenbleed_check_cpu, NULL, 1);
1335 }
1336
1337 /*
1338 * Issue a DIV 0/1 insn to clear any division data from previous DIV
1339 * operations.
1340 */
amd_clear_divider(void)1341 void noinstr amd_clear_divider(void)
1342 {
1343 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
1344 :: "a" (0), "d" (0), "r" (1));
1345 }
1346 EXPORT_SYMBOL_GPL(amd_clear_divider);
1347