1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Actions Semi Owl S500 SoC clock driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10 *
11 * Copyright (c) 2018 LSI-TEC - Caninos Loucos
12 * Author: Edgar Bernardi Righi <edgar.righi@lsitec.org.br>
13 */
14
15 #include <linux/clk-provider.h>
16 #include <linux/platform_device.h>
17
18 #include "owl-common.h"
19 #include "owl-composite.h"
20 #include "owl-divider.h"
21 #include "owl-factor.h"
22 #include "owl-fixed-factor.h"
23 #include "owl-gate.h"
24 #include "owl-mux.h"
25 #include "owl-pll.h"
26 #include "owl-reset.h"
27
28 #include <dt-bindings/clock/actions,s500-cmu.h>
29 #include <dt-bindings/reset/actions,s500-reset.h>
30
31 #define CMU_COREPLL (0x0000)
32 #define CMU_DEVPLL (0x0004)
33 #define CMU_DDRPLL (0x0008)
34 #define CMU_NANDPLL (0x000C)
35 #define CMU_DISPLAYPLL (0x0010)
36 #define CMU_AUDIOPLL (0x0014)
37 #define CMU_TVOUTPLL (0x0018)
38 #define CMU_BUSCLK (0x001C)
39 #define CMU_SENSORCLK (0x0020)
40 #define CMU_LCDCLK (0x0024)
41 #define CMU_DSICLK (0x0028)
42 #define CMU_CSICLK (0x002C)
43 #define CMU_DECLK (0x0030)
44 #define CMU_BISPCLK (0x0034)
45 #define CMU_BUSCLK1 (0x0038)
46 #define CMU_VDECLK (0x0040)
47 #define CMU_VCECLK (0x0044)
48 #define CMU_NANDCCLK (0x004C)
49 #define CMU_SD0CLK (0x0050)
50 #define CMU_SD1CLK (0x0054)
51 #define CMU_SD2CLK (0x0058)
52 #define CMU_UART0CLK (0x005C)
53 #define CMU_UART1CLK (0x0060)
54 #define CMU_UART2CLK (0x0064)
55 #define CMU_PWM4CLK (0x0068)
56 #define CMU_PWM5CLK (0x006C)
57 #define CMU_PWM0CLK (0x0070)
58 #define CMU_PWM1CLK (0x0074)
59 #define CMU_PWM2CLK (0x0078)
60 #define CMU_PWM3CLK (0x007C)
61 #define CMU_USBPLL (0x0080)
62 #define CMU_ETHERNETPLL (0x0084)
63 #define CMU_CVBSPLL (0x0088)
64 #define CMU_LENSCLK (0x008C)
65 #define CMU_GPU3DCLK (0x0090)
66 #define CMU_CORECTL (0x009C)
67 #define CMU_DEVCLKEN0 (0x00A0)
68 #define CMU_DEVCLKEN1 (0x00A4)
69 #define CMU_DEVRST0 (0x00A8)
70 #define CMU_DEVRST1 (0x00AC)
71 #define CMU_UART3CLK (0x00B0)
72 #define CMU_UART4CLK (0x00B4)
73 #define CMU_UART5CLK (0x00B8)
74 #define CMU_UART6CLK (0x00BC)
75 #define CMU_SSCLK (0x00C0)
76 #define CMU_DIGITALDEBUG (0x00D0)
77 #define CMU_ANALOGDEBUG (0x00D4)
78 #define CMU_COREPLLDEBUG (0x00D8)
79 #define CMU_DEVPLLDEBUG (0x00DC)
80 #define CMU_DDRPLLDEBUG (0x00E0)
81 #define CMU_NANDPLLDEBUG (0x00E4)
82 #define CMU_DISPLAYPLLDEBUG (0x00E8)
83 #define CMU_TVOUTPLLDEBUG (0x00EC)
84 #define CMU_DEEPCOLORPLLDEBUG (0x00F4)
85 #define CMU_AUDIOPLL_ETHPLLDEBUG (0x00F8)
86 #define CMU_CVBSPLLDEBUG (0x00FC)
87
88 #define OWL_S500_COREPLL_DELAY (150)
89 #define OWL_S500_DDRPLL_DELAY (63)
90 #define OWL_S500_DEVPLL_DELAY (28)
91 #define OWL_S500_NANDPLL_DELAY (44)
92 #define OWL_S500_DISPLAYPLL_DELAY (57)
93 #define OWL_S500_ETHERNETPLL_DELAY (25)
94 #define OWL_S500_AUDIOPLL_DELAY (100)
95
96 static const struct clk_pll_table clk_audio_pll_table[] = {
97 { 0, 45158400 }, { 1, 49152000 },
98 { 0, 0 },
99 };
100
101 /* pll clocks */
102 static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
103 static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
104 static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
105 static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
106 static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
107 static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
108 static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED);
109
110 static const char * const dev_clk_mux_p[] = { "hosc", "dev_pll_clk" };
111 static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
112 static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
113 static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
114 static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
115 static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
116 static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
117 static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
118 static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
119 static const char * const hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
120 static const char * const nand_clk_mux_p[] = { "nand_pll_clk", "display_pll_clk", "dev_clk", "ddr_pll_clk" };
121
122 static struct clk_factor_table sd_factor_table[] = {
123 /* bit0 ~ 4 */
124 { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
125 { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
126 { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
127 { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
128 { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
129 { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
130 { 24, 1, 25 },
131
132 /* bit8: /128 */
133 { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
134 { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
135 { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
136 { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
137 { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
138 { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
139 { 280, 1, 25 * 128 },
140 { 0, 0, 0 },
141 };
142
143 static struct clk_factor_table de_factor_table[] = {
144 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
145 { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
146 { 8, 1, 12 },
147 { 0, 0, 0 },
148 };
149
150 static struct clk_factor_table hde_factor_table[] = {
151 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
152 { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
153 { 0, 0, 0 },
154 };
155
156 static struct clk_div_table rmii_ref_div_table[] = {
157 { 0, 4 }, { 1, 10 },
158 { 0, 0 },
159 };
160
161 static struct clk_div_table std12rate_div_table[] = {
162 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
163 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
164 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
165 { 0, 0 },
166 };
167
168 static struct clk_div_table i2s_div_table[] = {
169 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
170 { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
171 { 8, 24 },
172 { 0, 0 },
173 };
174
175 static struct clk_div_table nand_div_table[] = {
176 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
177 { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
178 { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
179 { 0, 0 },
180 };
181
182 /* mux clock */
183 static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
184
185 /* gate clocks */
186 static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
187 static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
188 static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
189 static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
190 static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
191 static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
192 static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
193 static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
194
195 /* divider clocks */
196 static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
197 static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
198 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
199
200 /* factor clocks */
201 static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
202 static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
203
204 /* composite clocks */
205 static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
206 OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
207 { 0 },
208 OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
209 CLK_SET_RATE_PARENT);
210
211 static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
212 { 0 },
213 1, 1, 0);
214
215 static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
216 OWL_MUX_HW(CMU_VCECLK, 4, 2),
217 OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
218 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
219 0);
220
221 static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
222 OWL_MUX_HW(CMU_VDECLK, 4, 2),
223 OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
224 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
225 0);
226
227 static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p,
228 OWL_MUX_HW(CMU_BISPCLK, 4, 1),
229 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
230 OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
231 0);
232
233 static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
234 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
235 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
236 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
237 0);
238
239 static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
240 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
241 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
242 OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
243 0);
244
245 static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
246 OWL_MUX_HW(CMU_SD0CLK, 9, 1),
247 OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
248 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
249 0);
250
251 static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
252 OWL_MUX_HW(CMU_SD1CLK, 9, 1),
253 OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
254 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
255 0);
256
257 static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
258 OWL_MUX_HW(CMU_SD2CLK, 9, 1),
259 OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
260 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
261 0);
262
263 static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p,
264 OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
265 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
266 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
267 0);
268
269 static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p,
270 OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
271 OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
272 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
273 0);
274
275 static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p,
276 OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
277 OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
278 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
279 0);
280
281 static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p,
282 OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
283 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
284 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
285 0);
286
287 static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p,
288 OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
289 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
290 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
291 0);
292
293 static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p,
294 OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
295 OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
296 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
297 0);
298
299 static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
300 OWL_MUX_HW(CMU_DECLK, 12, 1),
301 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
302 0);
303
304 static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk",
305 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
306 1, 5, 0);
307
308 static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk",
309 OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
310 1, 5, 0);
311
312 static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk",
313 OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
314 1, 5, 0);
315
316 static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
317 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
318 1, 5, 0);
319
320 static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
321 OWL_MUX_HW(CMU_UART0CLK, 16, 1),
322 OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
323 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
324 CLK_IGNORE_UNUSED);
325
326 static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
327 OWL_MUX_HW(CMU_UART1CLK, 16, 1),
328 OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
329 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
330 CLK_IGNORE_UNUSED);
331
332 static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
333 OWL_MUX_HW(CMU_UART2CLK, 16, 1),
334 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
335 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
336 CLK_IGNORE_UNUSED);
337
338 static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
339 OWL_MUX_HW(CMU_UART3CLK, 16, 1),
340 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
341 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
342 CLK_IGNORE_UNUSED);
343
344 static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
345 OWL_MUX_HW(CMU_UART4CLK, 16, 1),
346 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
347 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
348 CLK_IGNORE_UNUSED);
349
350 static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
351 OWL_MUX_HW(CMU_UART5CLK, 16, 1),
352 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
353 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
354 CLK_IGNORE_UNUSED);
355
356 static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
357 OWL_MUX_HW(CMU_UART6CLK, 16, 1),
358 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
359 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
360 CLK_IGNORE_UNUSED);
361
362 static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
363 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
364 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
365 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
366 0);
367
368 static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
369 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
370 OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
371 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
372 0);
373
374 static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
375 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
376 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
377 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
378 0);
379
380 static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p,
381 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
382 OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
383 OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
384 0);
385
386 static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p,
387 OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
388 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
389 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
390 CLK_SET_RATE_PARENT);
391
392 static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p,
393 OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
394 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
395 OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),
396 CLK_SET_RATE_PARENT);
397
398 static struct owl_clk_common *s500_clks[] = {
399 ðernet_pll_clk.common,
400 &core_pll_clk.common,
401 &ddr_pll_clk.common,
402 &dev_pll_clk.common,
403 &nand_pll_clk.common,
404 &audio_pll_clk.common,
405 &display_pll_clk.common,
406 &dev_clk.common,
407 &timer_clk.common,
408 &i2c0_clk.common,
409 &i2c1_clk.common,
410 &i2c2_clk.common,
411 &i2c3_clk.common,
412 &uart0_clk.common,
413 &uart1_clk.common,
414 &uart2_clk.common,
415 &uart3_clk.common,
416 &uart4_clk.common,
417 &uart5_clk.common,
418 &uart6_clk.common,
419 &pwm0_clk.common,
420 &pwm1_clk.common,
421 &pwm2_clk.common,
422 &pwm3_clk.common,
423 &pwm4_clk.common,
424 &pwm5_clk.common,
425 &sensor0_clk.common,
426 &sensor1_clk.common,
427 &sd0_clk.common,
428 &sd1_clk.common,
429 &sd2_clk.common,
430 &bisp_clk.common,
431 &ahb_clk.common,
432 &ahbprediv_clk.common,
433 &h_clk.common,
434 &spi0_clk.common,
435 &spi1_clk.common,
436 &spi2_clk.common,
437 &spi3_clk.common,
438 &rmii_ref_clk.common,
439 &de_clk.common,
440 &de1_clk.common,
441 &de2_clk.common,
442 &i2srx_clk.common,
443 &i2stx_clk.common,
444 &hdmia_clk.common,
445 &hdmi_clk.common,
446 &vce_clk.common,
447 &vde_clk.common,
448 &spdif_clk.common,
449 &nand_clk.common,
450 &ecc_clk.common,
451 &apb_clk.common,
452 &dmac_clk.common,
453 &gpio_clk.common,
454 };
455
456 static struct clk_hw_onecell_data s500_hw_clks = {
457 .hws = {
458 [CLK_ETHERNET_PLL] = ðernet_pll_clk.common.hw,
459 [CLK_CORE_PLL] = &core_pll_clk.common.hw,
460 [CLK_DDR_PLL] = &ddr_pll_clk.common.hw,
461 [CLK_NAND_PLL] = &nand_pll_clk.common.hw,
462 [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw,
463 [CLK_DEV_PLL] = &dev_pll_clk.common.hw,
464 [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw,
465 [CLK_TIMER] = &timer_clk.common.hw,
466 [CLK_DEV] = &dev_clk.common.hw,
467 [CLK_DE] = &de_clk.common.hw,
468 [CLK_DE1] = &de1_clk.common.hw,
469 [CLK_DE2] = &de2_clk.common.hw,
470 [CLK_I2C0] = &i2c0_clk.common.hw,
471 [CLK_I2C1] = &i2c1_clk.common.hw,
472 [CLK_I2C2] = &i2c2_clk.common.hw,
473 [CLK_I2C3] = &i2c3_clk.common.hw,
474 [CLK_I2SRX] = &i2srx_clk.common.hw,
475 [CLK_I2STX] = &i2stx_clk.common.hw,
476 [CLK_UART0] = &uart0_clk.common.hw,
477 [CLK_UART1] = &uart1_clk.common.hw,
478 [CLK_UART2] = &uart2_clk.common.hw,
479 [CLK_UART3] = &uart3_clk.common.hw,
480 [CLK_UART4] = &uart4_clk.common.hw,
481 [CLK_UART5] = &uart5_clk.common.hw,
482 [CLK_UART6] = &uart6_clk.common.hw,
483 [CLK_PWM0] = &pwm0_clk.common.hw,
484 [CLK_PWM1] = &pwm1_clk.common.hw,
485 [CLK_PWM2] = &pwm2_clk.common.hw,
486 [CLK_PWM3] = &pwm3_clk.common.hw,
487 [CLK_PWM4] = &pwm4_clk.common.hw,
488 [CLK_PWM5] = &pwm5_clk.common.hw,
489 [CLK_SENSOR0] = &sensor0_clk.common.hw,
490 [CLK_SENSOR1] = &sensor1_clk.common.hw,
491 [CLK_SD0] = &sd0_clk.common.hw,
492 [CLK_SD1] = &sd1_clk.common.hw,
493 [CLK_SD2] = &sd2_clk.common.hw,
494 [CLK_BISP] = &bisp_clk.common.hw,
495 [CLK_SPI0] = &spi0_clk.common.hw,
496 [CLK_SPI1] = &spi1_clk.common.hw,
497 [CLK_SPI2] = &spi2_clk.common.hw,
498 [CLK_SPI3] = &spi3_clk.common.hw,
499 [CLK_AHB] = &ahb_clk.common.hw,
500 [CLK_H] = &h_clk.common.hw,
501 [CLK_AHBPREDIV] = &ahbprediv_clk.common.hw,
502 [CLK_RMII_REF] = &rmii_ref_clk.common.hw,
503 [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw,
504 [CLK_HDMI] = &hdmi_clk.common.hw,
505 [CLK_VDE] = &vde_clk.common.hw,
506 [CLK_VCE] = &vce_clk.common.hw,
507 [CLK_SPDIF] = &spdif_clk.common.hw,
508 [CLK_NAND] = &nand_clk.common.hw,
509 [CLK_ECC] = &ecc_clk.common.hw,
510 [CLK_APB] = &apb_clk.common.hw,
511 [CLK_DMAC] = &dmac_clk.common.hw,
512 [CLK_GPIO] = &gpio_clk.common.hw,
513 },
514 .num = CLK_NR_CLKS,
515 };
516
517 static const struct owl_reset_map s500_resets[] = {
518 [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
519 [RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
520 [RESET_DDR] = { CMU_DEVRST0, BIT(2) },
521 [RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
522 [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
523 [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
524 [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
525 [RESET_DE] = { CMU_DEVRST0, BIT(7) },
526 [RESET_LCD] = { CMU_DEVRST0, BIT(8) },
527 [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
528 [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
529 [RESET_CSI] = { CMU_DEVRST0, BIT(11) },
530 [RESET_BISP] = { CMU_DEVRST0, BIT(12) },
531 [RESET_KEY] = { CMU_DEVRST0, BIT(14) },
532 [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
533 [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
534 [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
535 [RESET_VDE] = { CMU_DEVRST0, BIT(19) },
536 [RESET_VCE] = { CMU_DEVRST0, BIT(20) },
537 [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
538 [RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
539 [RESET_LENS] = { CMU_DEVRST0, BIT(26) },
540 [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
541 [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
542 [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
543 [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
544 [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
545 [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
546 [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
547 [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
548 [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
549 [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
550 [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
551 [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
552 [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
553 [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
554 [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
555 [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
556 [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
557 [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
558 [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
559 [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
560 [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
561 [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
562 [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
563 [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
564 [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
565 [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
566 [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
567 [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
568 [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
569 [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
570 [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
571 [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
572 };
573
574 static struct owl_clk_desc s500_clk_desc = {
575 .clks = s500_clks,
576 .num_clks = ARRAY_SIZE(s500_clks),
577
578 .hw_clks = &s500_hw_clks,
579
580 .resets = s500_resets,
581 .num_resets = ARRAY_SIZE(s500_resets),
582 };
583
s500_clk_probe(struct platform_device * pdev)584 static int s500_clk_probe(struct platform_device *pdev)
585 {
586 struct owl_clk_desc *desc;
587 struct owl_reset *reset;
588 int ret;
589
590 desc = &s500_clk_desc;
591 owl_clk_regmap_init(pdev, desc);
592
593 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
594 if (!reset)
595 return -ENOMEM;
596
597 reset->rcdev.of_node = pdev->dev.of_node;
598 reset->rcdev.ops = &owl_reset_ops;
599 reset->rcdev.nr_resets = desc->num_resets;
600 reset->reset_map = desc->resets;
601 reset->regmap = desc->regmap;
602
603 ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
604 if (ret)
605 dev_err(&pdev->dev, "Failed to register reset controller\n");
606
607 return owl_clk_probe(&pdev->dev, desc->hw_clks);
608 }
609
610 static const struct of_device_id s500_clk_of_match[] = {
611 { .compatible = "actions,s500-cmu", },
612 { /* sentinel */ }
613 };
614
615 static struct platform_driver s500_clk_driver = {
616 .probe = s500_clk_probe,
617 .driver = {
618 .name = "s500-cmu",
619 .of_match_table = s500_clk_of_match,
620 },
621 };
622
s500_clk_init(void)623 static int __init s500_clk_init(void)
624 {
625 return platform_driver_register(&s500_clk_driver);
626 }
627 core_initcall(s500_clk_init);
628