1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Russell King
4 * Rewritten from the dovefb driver, and Armada510 manuals.
5 */
6
7 #include <linux/bitfield.h>
8
9 #include <drm/armada_drm.h>
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_atomic_uapi.h>
13 #include <drm/drm_fourcc.h>
14 #include <drm/drm_plane_helper.h>
15
16 #include "armada_crtc.h"
17 #include "armada_drm.h"
18 #include "armada_fb.h"
19 #include "armada_gem.h"
20 #include "armada_hw.h"
21 #include "armada_ioctlP.h"
22 #include "armada_plane.h"
23 #include "armada_trace.h"
24
25 #define DEFAULT_BRIGHTNESS 0
26 #define DEFAULT_CONTRAST 0x4000
27 #define DEFAULT_SATURATION 0x4000
28 #define DEFAULT_ENCODING DRM_COLOR_YCBCR_BT601
29
30 struct armada_overlay_state {
31 struct armada_plane_state base;
32 u32 colorkey_yr;
33 u32 colorkey_ug;
34 u32 colorkey_vb;
35 u32 colorkey_mode;
36 u32 colorkey_enable;
37 s16 brightness;
38 u16 contrast;
39 u16 saturation;
40 };
41 #define drm_to_overlay_state(s) \
42 container_of(s, struct armada_overlay_state, base.base)
43
armada_spu_contrast(struct drm_plane_state * state)44 static inline u32 armada_spu_contrast(struct drm_plane_state *state)
45 {
46 return drm_to_overlay_state(state)->brightness << 16 |
47 drm_to_overlay_state(state)->contrast;
48 }
49
armada_spu_saturation(struct drm_plane_state * state)50 static inline u32 armada_spu_saturation(struct drm_plane_state *state)
51 {
52 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
53 return drm_to_overlay_state(state)->saturation << 16;
54 }
55
armada_csc(struct drm_plane_state * state)56 static inline u32 armada_csc(struct drm_plane_state *state)
57 {
58 /*
59 * The CFG_CSC_RGB_* settings control the output of the colour space
60 * converter, setting the range of output values it produces. Since
61 * we will be blending with the full-range graphics, we need to
62 * produce full-range RGB output from the conversion.
63 */
64 return CFG_CSC_RGB_COMPUTER |
65 (state->color_encoding == DRM_COLOR_YCBCR_BT709 ?
66 CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601);
67 }
68
69 /* === Plane support === */
armada_drm_overlay_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)70 static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
71 struct drm_plane_state *old_state)
72 {
73 struct drm_plane_state *state = plane->state;
74 struct armada_crtc *dcrtc;
75 struct armada_regs *regs;
76 unsigned int idx;
77 u32 cfg, cfg_mask, val;
78
79 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
80
81 if (!state->fb || WARN_ON(!state->crtc))
82 return;
83
84 DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
85 plane->base.id, plane->name,
86 state->crtc->base.id, state->crtc->name,
87 state->fb->base.id,
88 old_state->visible, state->visible);
89
90 dcrtc = drm_to_armada_crtc(state->crtc);
91 regs = dcrtc->regs + dcrtc->regs_idx;
92
93 idx = 0;
94 if (!old_state->visible && state->visible)
95 armada_reg_queue_mod(regs, idx,
96 0, CFG_PDWN16x66 | CFG_PDWN32x66,
97 LCD_SPU_SRAM_PARA1);
98 val = armada_src_hw(state);
99 if (armada_src_hw(old_state) != val)
100 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
101 val = armada_dst_yx(state);
102 if (armada_dst_yx(old_state) != val)
103 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
104 val = armada_dst_hw(state);
105 if (armada_dst_hw(old_state) != val)
106 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
107 /* FIXME: overlay on an interlaced display */
108 if (old_state->src.x1 != state->src.x1 ||
109 old_state->src.y1 != state->src.y1 ||
110 old_state->fb != state->fb ||
111 state->crtc->state->mode_changed) {
112 const struct drm_format_info *format;
113 u16 src_x;
114
115 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
116 LCD_SPU_DMA_START_ADDR_Y0);
117 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1),
118 LCD_SPU_DMA_START_ADDR_U0);
119 armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2),
120 LCD_SPU_DMA_START_ADDR_V0);
121 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),
122 LCD_SPU_DMA_START_ADDR_Y1);
123 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1),
124 LCD_SPU_DMA_START_ADDR_U1);
125 armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2),
126 LCD_SPU_DMA_START_ADDR_V1);
127
128 val = armada_pitch(state, 0) << 16 | armada_pitch(state, 0);
129 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
130 val = armada_pitch(state, 1) << 16 | armada_pitch(state, 2);
131 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
132
133 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
134 CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) |
135 CFG_CBSH_ENA;
136 if (state->visible)
137 cfg |= CFG_DMA_ENA;
138
139 /*
140 * Shifting a YUV packed format image by one pixel causes the
141 * U/V planes to swap. Compensate for it by also toggling
142 * the UV swap.
143 */
144 format = state->fb->format;
145 src_x = state->src.x1 >> 16;
146 if (format->num_planes == 1 && src_x & (format->hsub - 1))
147 cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
148 if (to_armada_plane_state(state)->interlace)
149 cfg |= CFG_DMA_FTOGGLE;
150 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
151 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
152 CFG_SWAPYU | CFG_YUV2RGB) |
153 CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |
154 CFG_DMA_ENA;
155 } else if (old_state->visible != state->visible) {
156 cfg = state->visible ? CFG_DMA_ENA : 0;
157 cfg_mask = CFG_DMA_ENA;
158 } else {
159 cfg = cfg_mask = 0;
160 }
161 if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||
162 drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {
163 cfg_mask |= CFG_DMA_HSMOOTH;
164 if (drm_rect_width(&state->src) >> 16 !=
165 drm_rect_width(&state->dst))
166 cfg |= CFG_DMA_HSMOOTH;
167 }
168
169 if (cfg_mask)
170 armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
171 LCD_SPU_DMA_CTRL0);
172
173 val = armada_spu_contrast(state);
174 if ((!old_state->visible && state->visible) ||
175 armada_spu_contrast(old_state) != val)
176 armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);
177 val = armada_spu_saturation(state);
178 if ((!old_state->visible && state->visible) ||
179 armada_spu_saturation(old_state) != val)
180 armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);
181 if (!old_state->visible && state->visible)
182 armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);
183 val = armada_csc(state);
184 if ((!old_state->visible && state->visible) ||
185 armada_csc(old_state) != val)
186 armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK,
187 LCD_SPU_IOPAD_CONTROL);
188 val = drm_to_overlay_state(state)->colorkey_yr;
189 if ((!old_state->visible && state->visible) ||
190 drm_to_overlay_state(old_state)->colorkey_yr != val)
191 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);
192 val = drm_to_overlay_state(state)->colorkey_ug;
193 if ((!old_state->visible && state->visible) ||
194 drm_to_overlay_state(old_state)->colorkey_ug != val)
195 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);
196 val = drm_to_overlay_state(state)->colorkey_vb;
197 if ((!old_state->visible && state->visible) ||
198 drm_to_overlay_state(old_state)->colorkey_vb != val)
199 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);
200 val = drm_to_overlay_state(state)->colorkey_mode;
201 if ((!old_state->visible && state->visible) ||
202 drm_to_overlay_state(old_state)->colorkey_mode != val)
203 armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK |
204 CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
205 LCD_SPU_DMA_CTRL1);
206 val = drm_to_overlay_state(state)->colorkey_enable;
207 if (((!old_state->visible && state->visible) ||
208 drm_to_overlay_state(old_state)->colorkey_enable != val) &&
209 dcrtc->variant->has_spu_adv_reg)
210 armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY |
211 ADV_VIDCOLORKEY, LCD_SPU_ADV_REG);
212
213 dcrtc->regs_idx += idx;
214 }
215
armada_drm_overlay_plane_atomic_disable(struct drm_plane * plane,struct drm_plane_state * old_state)216 static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane,
217 struct drm_plane_state *old_state)
218 {
219 struct armada_crtc *dcrtc;
220 struct armada_regs *regs;
221 unsigned int idx = 0;
222
223 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
224
225 if (!old_state->crtc)
226 return;
227
228 DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
229 plane->base.id, plane->name,
230 old_state->crtc->base.id, old_state->crtc->name,
231 old_state->fb->base.id);
232
233 dcrtc = drm_to_armada_crtc(old_state->crtc);
234 regs = dcrtc->regs + dcrtc->regs_idx;
235
236 /* Disable plane and power down the YUV FIFOs */
237 armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0);
238 armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0,
239 LCD_SPU_SRAM_PARA1);
240
241 dcrtc->regs_idx += idx;
242 }
243
244 static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = {
245 .prepare_fb = armada_drm_plane_prepare_fb,
246 .cleanup_fb = armada_drm_plane_cleanup_fb,
247 .atomic_check = armada_drm_plane_atomic_check,
248 .atomic_update = armada_drm_overlay_plane_atomic_update,
249 .atomic_disable = armada_drm_overlay_plane_atomic_disable,
250 };
251
252 static int
armada_overlay_plane_update(struct drm_plane * plane,struct drm_crtc * crtc,struct drm_framebuffer * fb,int crtc_x,int crtc_y,unsigned crtc_w,unsigned crtc_h,uint32_t src_x,uint32_t src_y,uint32_t src_w,uint32_t src_h,struct drm_modeset_acquire_ctx * ctx)253 armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
254 struct drm_framebuffer *fb,
255 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
256 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
257 struct drm_modeset_acquire_ctx *ctx)
258 {
259 struct drm_atomic_state *state;
260 struct drm_plane_state *plane_state;
261 int ret = 0;
262
263 trace_armada_ovl_plane_update(plane, crtc, fb,
264 crtc_x, crtc_y, crtc_w, crtc_h,
265 src_x, src_y, src_w, src_h);
266
267 state = drm_atomic_state_alloc(plane->dev);
268 if (!state)
269 return -ENOMEM;
270
271 state->acquire_ctx = ctx;
272 plane_state = drm_atomic_get_plane_state(state, plane);
273 if (IS_ERR(plane_state)) {
274 ret = PTR_ERR(plane_state);
275 goto fail;
276 }
277
278 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
279 if (ret != 0)
280 goto fail;
281
282 drm_atomic_set_fb_for_plane(plane_state, fb);
283 plane_state->crtc_x = crtc_x;
284 plane_state->crtc_y = crtc_y;
285 plane_state->crtc_h = crtc_h;
286 plane_state->crtc_w = crtc_w;
287 plane_state->src_x = src_x;
288 plane_state->src_y = src_y;
289 plane_state->src_h = src_h;
290 plane_state->src_w = src_w;
291
292 ret = drm_atomic_nonblocking_commit(state);
293 fail:
294 drm_atomic_state_put(state);
295 return ret;
296 }
297
armada_ovl_plane_destroy(struct drm_plane * plane)298 static void armada_ovl_plane_destroy(struct drm_plane *plane)
299 {
300 drm_plane_cleanup(plane);
301 kfree(plane);
302 }
303
armada_overlay_reset(struct drm_plane * plane)304 static void armada_overlay_reset(struct drm_plane *plane)
305 {
306 struct armada_overlay_state *state;
307
308 if (plane->state)
309 __drm_atomic_helper_plane_destroy_state(plane->state);
310 kfree(plane->state);
311 plane->state = NULL;
312
313 state = kzalloc(sizeof(*state), GFP_KERNEL);
314 if (state) {
315 state->colorkey_yr = 0xfefefe00;
316 state->colorkey_ug = 0x01010100;
317 state->colorkey_vb = 0x01010100;
318 state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
319 CFG_ALPHAM_GRA | CFG_ALPHA(0);
320 state->colorkey_enable = ADV_GRACOLORKEY;
321 state->brightness = DEFAULT_BRIGHTNESS;
322 state->contrast = DEFAULT_CONTRAST;
323 state->saturation = DEFAULT_SATURATION;
324 __drm_atomic_helper_plane_reset(plane, &state->base.base);
325 state->base.base.color_encoding = DEFAULT_ENCODING;
326 state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
327 }
328 }
329
330 struct drm_plane_state *
armada_overlay_duplicate_state(struct drm_plane * plane)331 armada_overlay_duplicate_state(struct drm_plane *plane)
332 {
333 struct armada_overlay_state *state;
334
335 if (WARN_ON(!plane->state))
336 return NULL;
337
338 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL);
339 if (state)
340 __drm_atomic_helper_plane_duplicate_state(plane,
341 &state->base.base);
342 return &state->base.base;
343 }
344
armada_overlay_set_property(struct drm_plane * plane,struct drm_plane_state * state,struct drm_property * property,uint64_t val)345 static int armada_overlay_set_property(struct drm_plane *plane,
346 struct drm_plane_state *state, struct drm_property *property,
347 uint64_t val)
348 {
349 struct armada_private *priv = drm_to_armada_dev(plane->dev);
350
351 #define K2R(val) (((val) >> 0) & 0xff)
352 #define K2G(val) (((val) >> 8) & 0xff)
353 #define K2B(val) (((val) >> 16) & 0xff)
354 if (property == priv->colorkey_prop) {
355 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
356 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val));
357 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val));
358 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val));
359 #undef CCC
360 } else if (property == priv->colorkey_min_prop) {
361 drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000;
362 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16;
363 drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000;
364 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16;
365 drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000;
366 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16;
367 } else if (property == priv->colorkey_max_prop) {
368 drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000;
369 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24;
370 drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000;
371 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24;
372 drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000;
373 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24;
374 } else if (property == priv->colorkey_val_prop) {
375 drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00;
376 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8;
377 drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00;
378 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8;
379 drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00;
380 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8;
381 } else if (property == priv->colorkey_alpha_prop) {
382 drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff;
383 drm_to_overlay_state(state)->colorkey_yr |= K2R(val);
384 drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff;
385 drm_to_overlay_state(state)->colorkey_ug |= K2G(val);
386 drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff;
387 drm_to_overlay_state(state)->colorkey_vb |= K2B(val);
388 } else if (property == priv->colorkey_mode_prop) {
389 if (val == CKMODE_DISABLE) {
390 drm_to_overlay_state(state)->colorkey_mode =
391 CFG_CKMODE(CKMODE_DISABLE) |
392 CFG_ALPHAM_CFG | CFG_ALPHA(255);
393 drm_to_overlay_state(state)->colorkey_enable = 0;
394 } else {
395 drm_to_overlay_state(state)->colorkey_mode =
396 CFG_CKMODE(val) |
397 CFG_ALPHAM_GRA | CFG_ALPHA(0);
398 drm_to_overlay_state(state)->colorkey_enable =
399 ADV_GRACOLORKEY;
400 }
401 } else if (property == priv->brightness_prop) {
402 drm_to_overlay_state(state)->brightness = val - 256;
403 } else if (property == priv->contrast_prop) {
404 drm_to_overlay_state(state)->contrast = val;
405 } else if (property == priv->saturation_prop) {
406 drm_to_overlay_state(state)->saturation = val;
407 } else {
408 return -EINVAL;
409 }
410 return 0;
411 }
412
armada_overlay_get_property(struct drm_plane * plane,const struct drm_plane_state * state,struct drm_property * property,uint64_t * val)413 static int armada_overlay_get_property(struct drm_plane *plane,
414 const struct drm_plane_state *state, struct drm_property *property,
415 uint64_t *val)
416 {
417 struct armada_private *priv = drm_to_armada_dev(plane->dev);
418
419 #define C2K(c,s) (((c) >> (s)) & 0xff)
420 #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16)
421 if (property == priv->colorkey_prop) {
422 /* Do best-efforts here for this property */
423 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
424 drm_to_overlay_state(state)->colorkey_ug,
425 drm_to_overlay_state(state)->colorkey_vb, 16);
426 /* If min != max, or min != val, error out */
427 if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
428 drm_to_overlay_state(state)->colorkey_ug,
429 drm_to_overlay_state(state)->colorkey_vb, 24) ||
430 *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
431 drm_to_overlay_state(state)->colorkey_ug,
432 drm_to_overlay_state(state)->colorkey_vb, 8))
433 return -EINVAL;
434 } else if (property == priv->colorkey_min_prop) {
435 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
436 drm_to_overlay_state(state)->colorkey_ug,
437 drm_to_overlay_state(state)->colorkey_vb, 16);
438 } else if (property == priv->colorkey_max_prop) {
439 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
440 drm_to_overlay_state(state)->colorkey_ug,
441 drm_to_overlay_state(state)->colorkey_vb, 24);
442 } else if (property == priv->colorkey_val_prop) {
443 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
444 drm_to_overlay_state(state)->colorkey_ug,
445 drm_to_overlay_state(state)->colorkey_vb, 8);
446 } else if (property == priv->colorkey_alpha_prop) {
447 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
448 drm_to_overlay_state(state)->colorkey_ug,
449 drm_to_overlay_state(state)->colorkey_vb, 0);
450 } else if (property == priv->colorkey_mode_prop) {
451 *val = FIELD_GET(CFG_CKMODE_MASK,
452 drm_to_overlay_state(state)->colorkey_mode);
453 } else if (property == priv->brightness_prop) {
454 *val = drm_to_overlay_state(state)->brightness + 256;
455 } else if (property == priv->contrast_prop) {
456 *val = drm_to_overlay_state(state)->contrast;
457 } else if (property == priv->saturation_prop) {
458 *val = drm_to_overlay_state(state)->saturation;
459 } else {
460 return -EINVAL;
461 }
462 return 0;
463 }
464
465 static const struct drm_plane_funcs armada_ovl_plane_funcs = {
466 .update_plane = armada_overlay_plane_update,
467 .disable_plane = drm_atomic_helper_disable_plane,
468 .destroy = armada_ovl_plane_destroy,
469 .reset = armada_overlay_reset,
470 .atomic_duplicate_state = armada_overlay_duplicate_state,
471 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
472 .atomic_set_property = armada_overlay_set_property,
473 .atomic_get_property = armada_overlay_get_property,
474 };
475
476 static const uint32_t armada_ovl_formats[] = {
477 DRM_FORMAT_UYVY,
478 DRM_FORMAT_YUYV,
479 DRM_FORMAT_YUV420,
480 DRM_FORMAT_YVU420,
481 DRM_FORMAT_YUV422,
482 DRM_FORMAT_YVU422,
483 DRM_FORMAT_VYUY,
484 DRM_FORMAT_YVYU,
485 DRM_FORMAT_ARGB8888,
486 DRM_FORMAT_ABGR8888,
487 DRM_FORMAT_XRGB8888,
488 DRM_FORMAT_XBGR8888,
489 DRM_FORMAT_RGB888,
490 DRM_FORMAT_BGR888,
491 DRM_FORMAT_ARGB1555,
492 DRM_FORMAT_ABGR1555,
493 DRM_FORMAT_RGB565,
494 DRM_FORMAT_BGR565,
495 };
496
497 static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
498 { CKMODE_DISABLE, "disabled" },
499 { CKMODE_Y, "Y component" },
500 { CKMODE_U, "U component" },
501 { CKMODE_V, "V component" },
502 { CKMODE_RGB, "RGB" },
503 { CKMODE_R, "R component" },
504 { CKMODE_G, "G component" },
505 { CKMODE_B, "B component" },
506 };
507
armada_overlay_create_properties(struct drm_device * dev)508 static int armada_overlay_create_properties(struct drm_device *dev)
509 {
510 struct armada_private *priv = drm_to_armada_dev(dev);
511
512 if (priv->colorkey_prop)
513 return 0;
514
515 priv->colorkey_prop = drm_property_create_range(dev, 0,
516 "colorkey", 0, 0xffffff);
517 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
518 "colorkey_min", 0, 0xffffff);
519 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
520 "colorkey_max", 0, 0xffffff);
521 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
522 "colorkey_val", 0, 0xffffff);
523 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
524 "colorkey_alpha", 0, 0xffffff);
525 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
526 "colorkey_mode",
527 armada_drm_colorkey_enum_list,
528 ARRAY_SIZE(armada_drm_colorkey_enum_list));
529 priv->brightness_prop = drm_property_create_range(dev, 0,
530 "brightness", 0, 256 + 255);
531 priv->contrast_prop = drm_property_create_range(dev, 0,
532 "contrast", 0, 0x7fff);
533 priv->saturation_prop = drm_property_create_range(dev, 0,
534 "saturation", 0, 0x7fff);
535
536 if (!priv->colorkey_prop)
537 return -ENOMEM;
538
539 return 0;
540 }
541
armada_overlay_plane_create(struct drm_device * dev,unsigned long crtcs)542 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
543 {
544 struct armada_private *priv = drm_to_armada_dev(dev);
545 struct drm_mode_object *mobj;
546 struct drm_plane *overlay;
547 int ret;
548
549 ret = armada_overlay_create_properties(dev);
550 if (ret)
551 return ret;
552
553 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
554 if (!overlay)
555 return -ENOMEM;
556
557 drm_plane_helper_add(overlay, &armada_overlay_plane_helper_funcs);
558
559 ret = drm_universal_plane_init(dev, overlay, crtcs,
560 &armada_ovl_plane_funcs,
561 armada_ovl_formats,
562 ARRAY_SIZE(armada_ovl_formats),
563 NULL,
564 DRM_PLANE_TYPE_OVERLAY, NULL);
565 if (ret) {
566 kfree(overlay);
567 return ret;
568 }
569
570 mobj = &overlay->base;
571 drm_object_attach_property(mobj, priv->colorkey_prop,
572 0x0101fe);
573 drm_object_attach_property(mobj, priv->colorkey_min_prop,
574 0x0101fe);
575 drm_object_attach_property(mobj, priv->colorkey_max_prop,
576 0x0101fe);
577 drm_object_attach_property(mobj, priv->colorkey_val_prop,
578 0x0101fe);
579 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
580 0x000000);
581 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
582 CKMODE_RGB);
583 drm_object_attach_property(mobj, priv->brightness_prop,
584 256 + DEFAULT_BRIGHTNESS);
585 drm_object_attach_property(mobj, priv->contrast_prop,
586 DEFAULT_CONTRAST);
587 drm_object_attach_property(mobj, priv->saturation_prop,
588 DEFAULT_SATURATION);
589
590 ret = drm_plane_create_color_properties(overlay,
591 BIT(DRM_COLOR_YCBCR_BT601) |
592 BIT(DRM_COLOR_YCBCR_BT709),
593 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
594 DEFAULT_ENCODING,
595 DRM_COLOR_YCBCR_LIMITED_RANGE);
596
597 return ret;
598 }
599