1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i.MX8 NWL MIPI DSI host driver
4 *
5 * Copyright (C) 2017 NXP
6 * Copyright (C) 2020 Purism SPC
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/math64.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/mux/consumer.h>
16 #include <linux/of.h>
17 #include <linux/of_platform.h>
18 #include <linux/phy/phy.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 #include <linux/sys_soc.h>
22 #include <linux/time64.h>
23
24 #include <drm/drm_atomic_state_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_mipi_dsi.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_panel.h>
29 #include <drm/drm_print.h>
30
31 #include <video/mipi_display.h>
32
33 #include "nwl-dsi.h"
34
35 #define DRV_NAME "nwl-dsi"
36
37 /* i.MX8 NWL quirks */
38 /* i.MX8MQ errata E11418 */
39 #define E11418_HS_MODE_QUIRK BIT(0)
40
41 #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
42
43 enum transfer_direction {
44 DSI_PACKET_SEND,
45 DSI_PACKET_RECEIVE,
46 };
47
48 #define NWL_DSI_ENDPOINT_LCDIF 0
49 #define NWL_DSI_ENDPOINT_DCSS 1
50
51 struct nwl_dsi_plat_clk_config {
52 const char *id;
53 struct clk *clk;
54 bool present;
55 };
56
57 struct nwl_dsi_transfer {
58 const struct mipi_dsi_msg *msg;
59 struct mipi_dsi_packet packet;
60 struct completion completed;
61
62 int status; /* status of transmission */
63 enum transfer_direction direction;
64 bool need_bta;
65 u8 cmd;
66 u16 rx_word_count;
67 size_t tx_len; /* in bytes */
68 size_t rx_len; /* in bytes */
69 };
70
71 struct nwl_dsi {
72 struct drm_bridge bridge;
73 struct mipi_dsi_host dsi_host;
74 struct drm_bridge *panel_bridge;
75 struct device *dev;
76 struct phy *phy;
77 union phy_configure_opts phy_cfg;
78 unsigned int quirks;
79
80 struct regmap *regmap;
81 int irq;
82 /*
83 * The DSI host controller needs this reset sequence according to NWL:
84 * 1. Deassert pclk reset to get access to DSI regs
85 * 2. Configure DSI Host and DPHY and enable DPHY
86 * 3. Deassert ESC and BYTE resets to allow host TX operations)
87 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
88 * 5. Deassert DPI reset so DPI receives pixels and starts sending
89 * DSI data
90 *
91 * TODO: Since panel_bridges do their DSI setup in enable we
92 * currently have 4. and 5. swapped.
93 */
94 struct reset_control *rst_byte;
95 struct reset_control *rst_esc;
96 struct reset_control *rst_dpi;
97 struct reset_control *rst_pclk;
98 struct mux_control *mux;
99
100 /* DSI clocks */
101 struct clk *phy_ref_clk;
102 struct clk *rx_esc_clk;
103 struct clk *tx_esc_clk;
104 struct clk *core_clk;
105 /*
106 * hardware bug: the i.MX8MQ needs this clock on during reset
107 * even when not using LCDIF.
108 */
109 struct clk *lcdif_clk;
110
111 /* dsi lanes */
112 u32 lanes;
113 enum mipi_dsi_pixel_format format;
114 struct drm_display_mode mode;
115 unsigned long dsi_mode_flags;
116 int error;
117
118 struct nwl_dsi_transfer *xfer;
119 };
120
121 static const struct regmap_config nwl_dsi_regmap_config = {
122 .reg_bits = 16,
123 .val_bits = 32,
124 .reg_stride = 4,
125 .max_register = NWL_DSI_IRQ_MASK2,
126 .name = DRV_NAME,
127 };
128
bridge_to_dsi(struct drm_bridge * bridge)129 static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
130 {
131 return container_of(bridge, struct nwl_dsi, bridge);
132 }
133
nwl_dsi_clear_error(struct nwl_dsi * dsi)134 static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
135 {
136 int ret = dsi->error;
137
138 dsi->error = 0;
139 return ret;
140 }
141
nwl_dsi_write(struct nwl_dsi * dsi,unsigned int reg,u32 val)142 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
143 {
144 int ret;
145
146 if (dsi->error)
147 return;
148
149 ret = regmap_write(dsi->regmap, reg, val);
150 if (ret < 0) {
151 DRM_DEV_ERROR(dsi->dev,
152 "Failed to write NWL DSI reg 0x%x: %d\n", reg,
153 ret);
154 dsi->error = ret;
155 }
156 }
157
nwl_dsi_read(struct nwl_dsi * dsi,u32 reg)158 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
159 {
160 unsigned int val;
161 int ret;
162
163 if (dsi->error)
164 return 0;
165
166 ret = regmap_read(dsi->regmap, reg, &val);
167 if (ret < 0) {
168 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
169 reg, ret);
170 dsi->error = ret;
171 }
172 return val;
173 }
174
nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)175 static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
176 {
177 switch (format) {
178 case MIPI_DSI_FMT_RGB565:
179 return NWL_DSI_PIXEL_FORMAT_16;
180 case MIPI_DSI_FMT_RGB666:
181 return NWL_DSI_PIXEL_FORMAT_18L;
182 case MIPI_DSI_FMT_RGB666_PACKED:
183 return NWL_DSI_PIXEL_FORMAT_18;
184 case MIPI_DSI_FMT_RGB888:
185 return NWL_DSI_PIXEL_FORMAT_24;
186 default:
187 return -EINVAL;
188 }
189 }
190
191 /*
192 * ps2bc - Picoseconds to byte clock cycles
193 */
ps2bc(struct nwl_dsi * dsi,unsigned long long ps)194 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
195 {
196 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
197
198 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
199 dsi->lanes * 8ULL * NSEC_PER_SEC);
200 }
201
202 /*
203 * ui2bc - UI time periods to byte clock cycles
204 */
ui2bc(struct nwl_dsi * dsi,unsigned long long ui)205 static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
206 {
207 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
208
209 return DIV64_U64_ROUND_UP(ui * dsi->lanes,
210 dsi->mode.clock * 1000 * bpp);
211 }
212
213 /*
214 * us2bc - micro seconds to lp clock cycles
215 */
us2lp(u32 lp_clk_rate,unsigned long us)216 static u32 us2lp(u32 lp_clk_rate, unsigned long us)
217 {
218 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
219 }
220
nwl_dsi_config_host(struct nwl_dsi * dsi)221 static int nwl_dsi_config_host(struct nwl_dsi *dsi)
222 {
223 u32 cycles;
224 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
225
226 if (dsi->lanes < 1 || dsi->lanes > 4)
227 return -EINVAL;
228
229 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
230 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
231
232 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
233 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
234 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
235 } else {
236 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
237 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
238 }
239
240 /* values in byte clock cycles */
241 cycles = ui2bc(dsi, cfg->clk_pre);
242 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
243 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
244 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
245 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
246 cycles += ui2bc(dsi, cfg->clk_pre);
247 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
248 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
249 cycles = ps2bc(dsi, cfg->hs_exit);
250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
251 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
252
253 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
254 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
255 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
256 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
257 /* In LP clock cycles */
258 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
259 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
260 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
261
262 return nwl_dsi_clear_error(dsi);
263 }
264
nwl_dsi_config_dpi(struct nwl_dsi * dsi)265 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
266 {
267 u32 mode;
268 int color_format;
269 bool burst_mode;
270 int hfront_porch, hback_porch, vfront_porch, vback_porch;
271 int hsync_len, vsync_len;
272
273 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
274 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
275 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
276
277 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
278 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
279 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
280
281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
283 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
284 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
285 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
286 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
287 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
289 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
290
291 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
292 if (color_format < 0) {
293 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
294 dsi->format);
295 return color_format;
296 }
297 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
298
299 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
300 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
301 /*
302 * Adjusting input polarity based on the video mode results in
303 * a black screen so always pick active low:
304 */
305 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
306 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
307 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
308 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
309
310 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
311 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
312
313 if (burst_mode) {
314 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
315 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
316 } else {
317 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
318 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
319 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
320 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
321 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
322 dsi->mode.hdisplay);
323 }
324
325 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
326 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
327 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
328
329 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
330 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
331 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
332 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
333
334 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
335 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
336 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
337 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
338
339 return nwl_dsi_clear_error(dsi);
340 }
341
nwl_dsi_init_interrupts(struct nwl_dsi * dsi)342 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
343 {
344 u32 irq_enable;
345
346 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
347 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
348
349 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
350 NWL_DSI_RX_PKT_HDR_RCVD_MASK |
351 NWL_DSI_TX_FIFO_OVFLW_MASK |
352 NWL_DSI_HS_TX_TIMEOUT_MASK);
353
354 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
355
356 return nwl_dsi_clear_error(dsi);
357 }
358
nwl_dsi_host_attach(struct mipi_dsi_host * dsi_host,struct mipi_dsi_device * device)359 static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
360 struct mipi_dsi_device *device)
361 {
362 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
363 struct device *dev = dsi->dev;
364
365 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
366 device->format, device->mode_flags);
367
368 if (device->lanes < 1 || device->lanes > 4)
369 return -EINVAL;
370
371 dsi->lanes = device->lanes;
372 dsi->format = device->format;
373 dsi->dsi_mode_flags = device->mode_flags;
374
375 return 0;
376 }
377
nwl_dsi_read_packet(struct nwl_dsi * dsi,u32 status)378 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
379 {
380 struct device *dev = dsi->dev;
381 struct nwl_dsi_transfer *xfer = dsi->xfer;
382 int err;
383 u8 *payload = xfer->msg->rx_buf;
384 u32 val;
385 u16 word_count;
386 u8 channel;
387 u8 data_type;
388
389 xfer->status = 0;
390
391 if (xfer->rx_word_count == 0) {
392 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
393 return false;
394 /* Get the RX header and parse it */
395 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
396 err = nwl_dsi_clear_error(dsi);
397 if (err)
398 xfer->status = err;
399 word_count = NWL_DSI_WC(val);
400 channel = NWL_DSI_RX_VC(val);
401 data_type = NWL_DSI_RX_DT(val);
402
403 if (channel != xfer->msg->channel) {
404 DRM_DEV_ERROR(dev,
405 "[%02X] Channel mismatch (%u != %u)\n",
406 xfer->cmd, channel, xfer->msg->channel);
407 xfer->status = -EINVAL;
408 return true;
409 }
410
411 switch (data_type) {
412 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
413 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
414 if (xfer->msg->rx_len > 1) {
415 /* read second byte */
416 payload[1] = word_count >> 8;
417 ++xfer->rx_len;
418 }
419 fallthrough;
420 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
421 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
422 if (xfer->msg->rx_len > 0) {
423 /* read first byte */
424 payload[0] = word_count & 0xff;
425 ++xfer->rx_len;
426 }
427 xfer->status = xfer->rx_len;
428 return true;
429 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
430 word_count &= 0xff;
431 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
432 xfer->cmd, word_count);
433 xfer->status = -EPROTO;
434 return true;
435 }
436
437 if (word_count > xfer->msg->rx_len) {
438 DRM_DEV_ERROR(dev,
439 "[%02X] Receive buffer too small: %zu (< %u)\n",
440 xfer->cmd, xfer->msg->rx_len, word_count);
441 xfer->status = -EINVAL;
442 return true;
443 }
444
445 xfer->rx_word_count = word_count;
446 } else {
447 /* Set word_count from previous header read */
448 word_count = xfer->rx_word_count;
449 }
450
451 /* If RX payload is not yet received, wait for it */
452 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
453 return false;
454
455 /* Read the RX payload */
456 while (word_count >= 4) {
457 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
458 payload[0] = (val >> 0) & 0xff;
459 payload[1] = (val >> 8) & 0xff;
460 payload[2] = (val >> 16) & 0xff;
461 payload[3] = (val >> 24) & 0xff;
462 payload += 4;
463 xfer->rx_len += 4;
464 word_count -= 4;
465 }
466
467 if (word_count > 0) {
468 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
469 switch (word_count) {
470 case 3:
471 payload[2] = (val >> 16) & 0xff;
472 ++xfer->rx_len;
473 fallthrough;
474 case 2:
475 payload[1] = (val >> 8) & 0xff;
476 ++xfer->rx_len;
477 fallthrough;
478 case 1:
479 payload[0] = (val >> 0) & 0xff;
480 ++xfer->rx_len;
481 break;
482 }
483 }
484
485 xfer->status = xfer->rx_len;
486 err = nwl_dsi_clear_error(dsi);
487 if (err)
488 xfer->status = err;
489
490 return true;
491 }
492
nwl_dsi_finish_transmission(struct nwl_dsi * dsi,u32 status)493 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
494 {
495 struct nwl_dsi_transfer *xfer = dsi->xfer;
496 bool end_packet = false;
497
498 if (!xfer)
499 return;
500
501 if (xfer->direction == DSI_PACKET_SEND &&
502 status & NWL_DSI_TX_PKT_DONE) {
503 xfer->status = xfer->tx_len;
504 end_packet = true;
505 } else if (status & NWL_DSI_DPHY_DIRECTION &&
506 ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
507 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
508 end_packet = nwl_dsi_read_packet(dsi, status);
509 }
510
511 if (end_packet)
512 complete(&xfer->completed);
513 }
514
nwl_dsi_begin_transmission(struct nwl_dsi * dsi)515 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
516 {
517 struct nwl_dsi_transfer *xfer = dsi->xfer;
518 struct mipi_dsi_packet *pkt = &xfer->packet;
519 const u8 *payload;
520 size_t length;
521 u16 word_count;
522 u8 hs_mode;
523 u32 val;
524 u32 hs_workaround = 0;
525
526 /* Send the payload, if any */
527 length = pkt->payload_length;
528 payload = pkt->payload;
529
530 while (length >= 4) {
531 val = *(u32 *)payload;
532 hs_workaround |= !(val & 0xFFFF00);
533 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
534 payload += 4;
535 length -= 4;
536 }
537 /* Send the rest of the payload */
538 val = 0;
539 switch (length) {
540 case 3:
541 val |= payload[2] << 16;
542 fallthrough;
543 case 2:
544 val |= payload[1] << 8;
545 hs_workaround |= !(val & 0xFFFF00);
546 fallthrough;
547 case 1:
548 val |= payload[0];
549 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
550 break;
551 }
552 xfer->tx_len = pkt->payload_length;
553
554 /*
555 * Send the header
556 * header[0] = Virtual Channel + Data Type
557 * header[1] = Word Count LSB (LP) or first param (SP)
558 * header[2] = Word Count MSB (LP) or second param (SP)
559 */
560 word_count = pkt->header[1] | (pkt->header[2] << 8);
561 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
562 DRM_DEV_DEBUG_DRIVER(dsi->dev,
563 "Using hs mode workaround for cmd 0x%x\n",
564 xfer->cmd);
565 hs_mode = 1;
566 } else {
567 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
568 }
569 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
570 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
571 NWL_DSI_BTA_TX(xfer->need_bta);
572 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
573
574 /* Send packet command */
575 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
576 }
577
nwl_dsi_host_transfer(struct mipi_dsi_host * dsi_host,const struct mipi_dsi_msg * msg)578 static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
579 const struct mipi_dsi_msg *msg)
580 {
581 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
582 struct nwl_dsi_transfer xfer;
583 ssize_t ret = 0;
584
585 /* Create packet to be sent */
586 dsi->xfer = &xfer;
587 ret = mipi_dsi_create_packet(&xfer.packet, msg);
588 if (ret < 0) {
589 dsi->xfer = NULL;
590 return ret;
591 }
592
593 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
594 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
595 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
596 msg->type & MIPI_DSI_DCS_READ) &&
597 msg->rx_len > 0 && msg->rx_buf)
598 xfer.direction = DSI_PACKET_RECEIVE;
599 else
600 xfer.direction = DSI_PACKET_SEND;
601
602 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
603 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
604 xfer.msg = msg;
605 xfer.status = -ETIMEDOUT;
606 xfer.rx_word_count = 0;
607 xfer.rx_len = 0;
608 xfer.cmd = 0x00;
609 if (msg->tx_len > 0)
610 xfer.cmd = ((u8 *)(msg->tx_buf))[0];
611 init_completion(&xfer.completed);
612
613 ret = clk_prepare_enable(dsi->rx_esc_clk);
614 if (ret < 0) {
615 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
616 ret);
617 return ret;
618 }
619 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
620 clk_get_rate(dsi->rx_esc_clk));
621
622 /* Initiate the DSI packet transmision */
623 nwl_dsi_begin_transmission(dsi);
624
625 if (!wait_for_completion_timeout(&xfer.completed,
626 NWL_DSI_MIPI_FIFO_TIMEOUT)) {
627 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
628 xfer.cmd);
629 ret = -ETIMEDOUT;
630 } else {
631 ret = xfer.status;
632 }
633
634 clk_disable_unprepare(dsi->rx_esc_clk);
635
636 return ret;
637 }
638
639 static const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
640 .attach = nwl_dsi_host_attach,
641 .transfer = nwl_dsi_host_transfer,
642 };
643
nwl_dsi_irq_handler(int irq,void * data)644 static irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
645 {
646 u32 irq_status;
647 struct nwl_dsi *dsi = data;
648
649 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
650
651 if (irq_status & NWL_DSI_TX_FIFO_OVFLW)
652 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
653
654 if (irq_status & NWL_DSI_HS_TX_TIMEOUT)
655 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
656
657 if (irq_status & NWL_DSI_TX_PKT_DONE ||
658 irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
659 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
660 nwl_dsi_finish_transmission(dsi, irq_status);
661
662 return IRQ_HANDLED;
663 }
664
nwl_dsi_enable(struct nwl_dsi * dsi)665 static int nwl_dsi_enable(struct nwl_dsi *dsi)
666 {
667 struct device *dev = dsi->dev;
668 union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
669 int ret;
670
671 if (!dsi->lanes) {
672 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
673 return -EINVAL;
674 }
675
676 ret = phy_init(dsi->phy);
677 if (ret < 0) {
678 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
679 return ret;
680 }
681
682 ret = phy_configure(dsi->phy, phy_cfg);
683 if (ret < 0) {
684 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
685 goto uninit_phy;
686 }
687
688 ret = clk_prepare_enable(dsi->tx_esc_clk);
689 if (ret < 0) {
690 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
691 ret);
692 goto uninit_phy;
693 }
694 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
695 clk_get_rate(dsi->tx_esc_clk));
696
697 ret = nwl_dsi_config_host(dsi);
698 if (ret < 0) {
699 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
700 goto disable_clock;
701 }
702
703 ret = nwl_dsi_config_dpi(dsi);
704 if (ret < 0) {
705 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
706 goto disable_clock;
707 }
708
709 ret = phy_power_on(dsi->phy);
710 if (ret < 0) {
711 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
712 goto disable_clock;
713 }
714
715 ret = nwl_dsi_init_interrupts(dsi);
716 if (ret < 0)
717 goto power_off_phy;
718
719 return ret;
720
721 power_off_phy:
722 phy_power_off(dsi->phy);
723 disable_clock:
724 clk_disable_unprepare(dsi->tx_esc_clk);
725 uninit_phy:
726 phy_exit(dsi->phy);
727
728 return ret;
729 }
730
nwl_dsi_disable(struct nwl_dsi * dsi)731 static int nwl_dsi_disable(struct nwl_dsi *dsi)
732 {
733 struct device *dev = dsi->dev;
734
735 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
736
737 phy_power_off(dsi->phy);
738 phy_exit(dsi->phy);
739
740 /* Disabling the clock before the phy breaks enabling dsi again */
741 clk_disable_unprepare(dsi->tx_esc_clk);
742
743 return 0;
744 }
745
746 static void
nwl_dsi_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)747 nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
748 struct drm_bridge_state *old_bridge_state)
749 {
750 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
751 int ret;
752
753 nwl_dsi_disable(dsi);
754
755 ret = reset_control_assert(dsi->rst_dpi);
756 if (ret < 0) {
757 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
758 return;
759 }
760 ret = reset_control_assert(dsi->rst_byte);
761 if (ret < 0) {
762 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
763 return;
764 }
765 ret = reset_control_assert(dsi->rst_esc);
766 if (ret < 0) {
767 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
768 return;
769 }
770 ret = reset_control_assert(dsi->rst_pclk);
771 if (ret < 0) {
772 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
773 return;
774 }
775
776 clk_disable_unprepare(dsi->core_clk);
777 clk_disable_unprepare(dsi->lcdif_clk);
778
779 pm_runtime_put(dsi->dev);
780 }
781
nwl_dsi_get_dphy_params(struct nwl_dsi * dsi,const struct drm_display_mode * mode,union phy_configure_opts * phy_opts)782 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
783 const struct drm_display_mode *mode,
784 union phy_configure_opts *phy_opts)
785 {
786 unsigned long rate;
787 int ret;
788
789 if (dsi->lanes < 1 || dsi->lanes > 4)
790 return -EINVAL;
791
792 /*
793 * So far the DPHY spec minimal timings work for both mixel
794 * dphy and nwl dsi host
795 */
796 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,
797 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
798 &phy_opts->mipi_dphy);
799 if (ret < 0)
800 return ret;
801
802 rate = clk_get_rate(dsi->tx_esc_clk);
803 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
804 phy_opts->mipi_dphy.lp_clk_rate = rate;
805
806 return 0;
807 }
808
809 static enum drm_mode_status
nwl_dsi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)810 nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
811 const struct drm_display_info *info,
812 const struct drm_display_mode *mode)
813 {
814 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
815 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
816
817 if (mode->clock * bpp > 15000000 * dsi->lanes)
818 return MODE_CLOCK_HIGH;
819
820 if (mode->clock * bpp < 80000 * dsi->lanes)
821 return MODE_CLOCK_LOW;
822
823 return MODE_OK;
824 }
825
nwl_dsi_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)826 static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge,
827 struct drm_bridge_state *bridge_state,
828 struct drm_crtc_state *crtc_state,
829 struct drm_connector_state *conn_state)
830 {
831 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
832
833 /* At least LCDIF + NWL needs active high sync */
834 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
835 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
836
837 /* Do a full modeset if crtc_state->active is changed to be true. */
838 if (crtc_state->active_changed && crtc_state->active)
839 crtc_state->mode_changed = true;
840
841 return 0;
842 }
843
844 static void
nwl_dsi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)845 nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
846 const struct drm_display_mode *mode,
847 const struct drm_display_mode *adjusted_mode)
848 {
849 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
850 struct device *dev = dsi->dev;
851 union phy_configure_opts new_cfg;
852 unsigned long phy_ref_rate;
853 int ret;
854
855 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
856 if (ret < 0)
857 return;
858
859 /*
860 * If hs clock is unchanged, we're all good - all parameters are
861 * derived from it atm.
862 */
863 if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)
864 return;
865
866 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
867 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
868 /* Save the new desired phy config */
869 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
870
871 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));
872 drm_mode_debug_printmodeline(adjusted_mode);
873 }
874
875 static void
nwl_dsi_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)876 nwl_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
877 struct drm_bridge_state *old_bridge_state)
878 {
879 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
880 int ret;
881
882 pm_runtime_get_sync(dsi->dev);
883
884 if (clk_prepare_enable(dsi->lcdif_clk) < 0)
885 return;
886 if (clk_prepare_enable(dsi->core_clk) < 0)
887 return;
888
889 /* Step 1 from DSI reset-out instructions */
890 ret = reset_control_deassert(dsi->rst_pclk);
891 if (ret < 0) {
892 DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret);
893 return;
894 }
895
896 /* Step 2 from DSI reset-out instructions */
897 nwl_dsi_enable(dsi);
898
899 /* Step 3 from DSI reset-out instructions */
900 ret = reset_control_deassert(dsi->rst_esc);
901 if (ret < 0) {
902 DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret);
903 return;
904 }
905 ret = reset_control_deassert(dsi->rst_byte);
906 if (ret < 0) {
907 DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret);
908 return;
909 }
910 }
911
912 static void
nwl_dsi_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)913 nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
914 struct drm_bridge_state *old_bridge_state)
915 {
916 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
917 int ret;
918
919 /* Step 5 from DSI reset-out instructions */
920 ret = reset_control_deassert(dsi->rst_dpi);
921 if (ret < 0)
922 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
923 }
924
nwl_dsi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)925 static int nwl_dsi_bridge_attach(struct drm_bridge *bridge,
926 enum drm_bridge_attach_flags flags)
927 {
928 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
929 struct drm_bridge *panel_bridge;
930 struct drm_panel *panel;
931 int ret;
932
933 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
934 &panel_bridge);
935 if (ret)
936 return ret;
937
938 if (panel) {
939 panel_bridge = drm_panel_bridge_add(panel);
940 if (IS_ERR(panel_bridge))
941 return PTR_ERR(panel_bridge);
942 }
943 dsi->panel_bridge = panel_bridge;
944
945 if (!dsi->panel_bridge)
946 return -EPROBE_DEFER;
947
948 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
949 flags);
950 }
951
nwl_dsi_bridge_detach(struct drm_bridge * bridge)952 static void nwl_dsi_bridge_detach(struct drm_bridge *bridge)
953 { struct nwl_dsi *dsi = bridge_to_dsi(bridge);
954
955 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);
956 }
957
958 static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
959 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
960 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
961 .atomic_reset = drm_atomic_helper_bridge_reset,
962 .atomic_check = nwl_dsi_bridge_atomic_check,
963 .atomic_pre_enable = nwl_dsi_bridge_atomic_pre_enable,
964 .atomic_enable = nwl_dsi_bridge_atomic_enable,
965 .atomic_disable = nwl_dsi_bridge_atomic_disable,
966 .mode_set = nwl_dsi_bridge_mode_set,
967 .mode_valid = nwl_dsi_bridge_mode_valid,
968 .attach = nwl_dsi_bridge_attach,
969 .detach = nwl_dsi_bridge_detach,
970 };
971
nwl_dsi_parse_dt(struct nwl_dsi * dsi)972 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
973 {
974 struct platform_device *pdev = to_platform_device(dsi->dev);
975 struct clk *clk;
976 void __iomem *base;
977 int ret;
978
979 dsi->phy = devm_phy_get(dsi->dev, "dphy");
980 if (IS_ERR(dsi->phy)) {
981 ret = PTR_ERR(dsi->phy);
982 if (ret != -EPROBE_DEFER)
983 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
984 return ret;
985 }
986
987 clk = devm_clk_get(dsi->dev, "lcdif");
988 if (IS_ERR(clk)) {
989 ret = PTR_ERR(clk);
990 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
991 ret);
992 return ret;
993 }
994 dsi->lcdif_clk = clk;
995
996 clk = devm_clk_get(dsi->dev, "core");
997 if (IS_ERR(clk)) {
998 ret = PTR_ERR(clk);
999 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
1000 ret);
1001 return ret;
1002 }
1003 dsi->core_clk = clk;
1004
1005 clk = devm_clk_get(dsi->dev, "phy_ref");
1006 if (IS_ERR(clk)) {
1007 ret = PTR_ERR(clk);
1008 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
1009 ret);
1010 return ret;
1011 }
1012 dsi->phy_ref_clk = clk;
1013
1014 clk = devm_clk_get(dsi->dev, "rx_esc");
1015 if (IS_ERR(clk)) {
1016 ret = PTR_ERR(clk);
1017 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
1018 ret);
1019 return ret;
1020 }
1021 dsi->rx_esc_clk = clk;
1022
1023 clk = devm_clk_get(dsi->dev, "tx_esc");
1024 if (IS_ERR(clk)) {
1025 ret = PTR_ERR(clk);
1026 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
1027 ret);
1028 return ret;
1029 }
1030 dsi->tx_esc_clk = clk;
1031
1032 dsi->mux = devm_mux_control_get(dsi->dev, NULL);
1033 if (IS_ERR(dsi->mux)) {
1034 ret = PTR_ERR(dsi->mux);
1035 if (ret != -EPROBE_DEFER)
1036 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
1037 return ret;
1038 }
1039
1040 base = devm_platform_ioremap_resource(pdev, 0);
1041 if (IS_ERR(base))
1042 return PTR_ERR(base);
1043
1044 dsi->regmap =
1045 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
1046 if (IS_ERR(dsi->regmap)) {
1047 ret = PTR_ERR(dsi->regmap);
1048 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
1049 ret);
1050 return ret;
1051 }
1052
1053 dsi->irq = platform_get_irq(pdev, 0);
1054 if (dsi->irq < 0) {
1055 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
1056 dsi->irq);
1057 return dsi->irq;
1058 }
1059
1060 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
1061 if (IS_ERR(dsi->rst_pclk)) {
1062 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
1063 PTR_ERR(dsi->rst_pclk));
1064 return PTR_ERR(dsi->rst_pclk);
1065 }
1066 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
1067 if (IS_ERR(dsi->rst_byte)) {
1068 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
1069 PTR_ERR(dsi->rst_byte));
1070 return PTR_ERR(dsi->rst_byte);
1071 }
1072 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
1073 if (IS_ERR(dsi->rst_esc)) {
1074 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
1075 PTR_ERR(dsi->rst_esc));
1076 return PTR_ERR(dsi->rst_esc);
1077 }
1078 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
1079 if (IS_ERR(dsi->rst_dpi)) {
1080 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
1081 PTR_ERR(dsi->rst_dpi));
1082 return PTR_ERR(dsi->rst_dpi);
1083 }
1084 return 0;
1085 }
1086
nwl_dsi_select_input(struct nwl_dsi * dsi)1087 static int nwl_dsi_select_input(struct nwl_dsi *dsi)
1088 {
1089 struct device_node *remote;
1090 u32 use_dcss = 1;
1091 int ret;
1092
1093 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1094 NWL_DSI_ENDPOINT_LCDIF);
1095 if (remote) {
1096 use_dcss = 0;
1097 } else {
1098 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1099 NWL_DSI_ENDPOINT_DCSS);
1100 if (!remote) {
1101 DRM_DEV_ERROR(dsi->dev,
1102 "No valid input endpoint found\n");
1103 return -EINVAL;
1104 }
1105 }
1106
1107 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
1108 (use_dcss) ? "DCSS" : "LCDIF");
1109 ret = mux_control_try_select(dsi->mux, use_dcss);
1110 if (ret < 0)
1111 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
1112
1113 of_node_put(remote);
1114 return ret;
1115 }
1116
nwl_dsi_deselect_input(struct nwl_dsi * dsi)1117 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
1118 {
1119 int ret;
1120
1121 ret = mux_control_deselect(dsi->mux);
1122 if (ret < 0)
1123 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
1124
1125 return ret;
1126 }
1127
1128 static const struct drm_bridge_timings nwl_dsi_timings = {
1129 .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1130 };
1131
1132 static const struct of_device_id nwl_dsi_dt_ids[] = {
1133 { .compatible = "fsl,imx8mq-nwl-dsi", },
1134 { /* sentinel */ }
1135 };
1136 MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids);
1137
1138 static const struct soc_device_attribute nwl_dsi_quirks_match[] = {
1139 { .soc_id = "i.MX8MQ", .revision = "2.0",
1140 .data = (void *)E11418_HS_MODE_QUIRK },
1141 { /* sentinel. */ },
1142 };
1143
nwl_dsi_probe(struct platform_device * pdev)1144 static int nwl_dsi_probe(struct platform_device *pdev)
1145 {
1146 struct device *dev = &pdev->dev;
1147 const struct soc_device_attribute *attr;
1148 struct nwl_dsi *dsi;
1149 int ret;
1150
1151 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1152 if (!dsi)
1153 return -ENOMEM;
1154
1155 dsi->dev = dev;
1156
1157 ret = nwl_dsi_parse_dt(dsi);
1158 if (ret)
1159 return ret;
1160
1161 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
1162 dev_name(dev), dsi);
1163 if (ret < 0) {
1164 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
1165 ret);
1166 return ret;
1167 }
1168
1169 dsi->dsi_host.ops = &nwl_dsi_host_ops;
1170 dsi->dsi_host.dev = dev;
1171 ret = mipi_dsi_host_register(&dsi->dsi_host);
1172 if (ret) {
1173 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1174 return ret;
1175 }
1176
1177 attr = soc_device_match(nwl_dsi_quirks_match);
1178 if (attr)
1179 dsi->quirks = (uintptr_t)attr->data;
1180
1181 dsi->bridge.driver_private = dsi;
1182 dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
1183 dsi->bridge.of_node = dev->of_node;
1184 dsi->bridge.timings = &nwl_dsi_timings;
1185
1186 dev_set_drvdata(dev, dsi);
1187 pm_runtime_enable(dev);
1188
1189 ret = nwl_dsi_select_input(dsi);
1190 if (ret < 0) {
1191 pm_runtime_disable(dev);
1192 mipi_dsi_host_unregister(&dsi->dsi_host);
1193 return ret;
1194 }
1195
1196 drm_bridge_add(&dsi->bridge);
1197 return 0;
1198 }
1199
nwl_dsi_remove(struct platform_device * pdev)1200 static int nwl_dsi_remove(struct platform_device *pdev)
1201 {
1202 struct nwl_dsi *dsi = platform_get_drvdata(pdev);
1203
1204 nwl_dsi_deselect_input(dsi);
1205 mipi_dsi_host_unregister(&dsi->dsi_host);
1206 drm_bridge_remove(&dsi->bridge);
1207 pm_runtime_disable(&pdev->dev);
1208 return 0;
1209 }
1210
1211 static struct platform_driver nwl_dsi_driver = {
1212 .probe = nwl_dsi_probe,
1213 .remove = nwl_dsi_remove,
1214 .driver = {
1215 .of_match_table = nwl_dsi_dt_ids,
1216 .name = DRV_NAME,
1217 },
1218 };
1219
1220 module_platform_driver(nwl_dsi_driver);
1221
1222 MODULE_AUTHOR("NXP Semiconductor");
1223 MODULE_AUTHOR("Purism SPC");
1224 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");
1225 MODULE_LICENSE("GPL"); /* GPLv2 or later */
1226