1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/math64.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/phy/phy.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18
19 #include <video/mipi_display.h>
20
21 #include <drm/bridge/dw_mipi_dsi.h>
22 #include <drm/drm_mipi_dsi.h>
23 #include <drm/drm_of.h>
24 #include <drm/drm_simple_kms_helper.h>
25
26 #include "rockchip_drm_drv.h"
27 #include "rockchip_drm_vop.h"
28
29 #define DSI_PHY_RSTZ 0xa0
30 #define PHY_DISFORCEPLL 0
31 #define PHY_ENFORCEPLL BIT(3)
32 #define PHY_DISABLECLK 0
33 #define PHY_ENABLECLK BIT(2)
34 #define PHY_RSTZ 0
35 #define PHY_UNRSTZ BIT(1)
36 #define PHY_SHUTDOWNZ 0
37 #define PHY_UNSHUTDOWNZ BIT(0)
38
39 #define DSI_PHY_IF_CFG 0xa4
40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
41 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
42
43 #define DSI_PHY_STATUS 0xb0
44 #define LOCK BIT(0)
45 #define STOP_STATE_CLK_LANE BIT(2)
46
47 #define DSI_PHY_TST_CTRL0 0xb4
48 #define PHY_TESTCLK BIT(1)
49 #define PHY_UNTESTCLK 0
50 #define PHY_TESTCLR BIT(0)
51 #define PHY_UNTESTCLR 0
52
53 #define DSI_PHY_TST_CTRL1 0xb8
54 #define PHY_TESTEN BIT(16)
55 #define PHY_UNTESTEN 0
56 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
57 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
58
59 #define DSI_INT_ST0 0xbc
60 #define DSI_INT_ST1 0xc0
61 #define DSI_INT_MSK0 0xc4
62 #define DSI_INT_MSK1 0xc8
63
64 #define PHY_STATUS_TIMEOUT_US 10000
65 #define CMD_PKT_STATUS_TIMEOUT_US 20000
66
67 #define BYPASS_VCO_RANGE BIT(7)
68 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
69 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
70 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
71 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
72 #define REF_BIAS_CUR_SEL BIT(0)
73
74 #define CP_CURRENT_3UA 0x1
75 #define CP_CURRENT_4_5UA 0x2
76 #define CP_CURRENT_7_5UA 0x6
77 #define CP_CURRENT_6UA 0x9
78 #define CP_CURRENT_12UA 0xb
79 #define CP_CURRENT_SEL(val) ((val) & 0xf)
80 #define CP_PROGRAM_EN BIT(7)
81
82 #define LPF_RESISTORS_15_5KOHM 0x1
83 #define LPF_RESISTORS_13KOHM 0x2
84 #define LPF_RESISTORS_11_5KOHM 0x4
85 #define LPF_RESISTORS_10_5KOHM 0x8
86 #define LPF_RESISTORS_8KOHM 0x10
87 #define LPF_PROGRAM_EN BIT(6)
88 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
89
90 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
91
92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
93 #define LOW_PROGRAM_EN 0
94 #define HIGH_PROGRAM_EN BIT(7)
95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
97 #define PLL_LOOP_DIV_EN BIT(5)
98 #define PLL_INPUT_DIV_EN BIT(4)
99
100 #define POWER_CONTROL BIT(6)
101 #define INTERNAL_REG_CURRENT BIT(3)
102 #define BIAS_BLOCK_ON BIT(2)
103 #define BANDGAP_ON BIT(0)
104
105 #define TER_RESISTOR_HIGH BIT(7)
106 #define TER_RESISTOR_LOW 0
107 #define LEVEL_SHIFTERS_ON BIT(6)
108 #define TER_CAL_DONE BIT(5)
109 #define SETRD_MAX (0x7 << 2)
110 #define POWER_MANAGE BIT(1)
111 #define TER_RESISTORS_ON BIT(0)
112
113 #define BIASEXTR_SEL(val) ((val) & 0x7)
114 #define BANDGAP_SEL(val) ((val) & 0x7)
115 #define TLP_PROGRAM_EN BIT(7)
116 #define THS_PRE_PROGRAM_EN BIT(7)
117 #define THS_ZERO_PROGRAM_EN BIT(6)
118
119 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
120 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
121 #define PLL_LPF_AND_CP_CONTROL 0x12
122 #define PLL_INPUT_DIVIDER_RATIO 0x17
123 #define PLL_LOOP_DIVIDER_RATIO 0x18
124 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
125 #define BANDGAP_AND_BIAS_CONTROL 0x20
126 #define TERMINATION_RESISTER_CONTROL 0x21
127 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
128 #define HS_RX_CONTROL_OF_LANE_0 0x44
129 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
130 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
131 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
132 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
133 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
134 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
135 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
136 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
137 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
138 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
139 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
140
141 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
142 #define DW_MIPI_NEEDS_GRF_CLK BIT(1)
143
144 #define PX30_GRF_PD_VO_CON1 0x0438
145 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
146 #define PX30_DSI_FORCERXMODE BIT(6)
147 #define PX30_DSI_TURNDISABLE BIT(5)
148 #define PX30_DSI_LCDC_SEL BIT(0)
149
150 #define RK3288_GRF_SOC_CON6 0x025c
151 #define RK3288_DSI0_LCDC_SEL BIT(6)
152 #define RK3288_DSI1_LCDC_SEL BIT(9)
153
154 #define RK3399_GRF_SOC_CON20 0x6250
155 #define RK3399_DSI0_LCDC_SEL BIT(0)
156 #define RK3399_DSI1_LCDC_SEL BIT(4)
157
158 #define RK3399_GRF_SOC_CON22 0x6258
159 #define RK3399_DSI0_TURNREQUEST (0xf << 12)
160 #define RK3399_DSI0_TURNDISABLE (0xf << 8)
161 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
162 #define RK3399_DSI0_FORCERXMODE (0xf << 0)
163
164 #define RK3399_GRF_SOC_CON23 0x625c
165 #define RK3399_DSI1_TURNDISABLE (0xf << 12)
166 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
167 #define RK3399_DSI1_FORCERXMODE (0xf << 4)
168 #define RK3399_DSI1_ENABLE (0xf << 0)
169
170 #define RK3399_GRF_SOC_CON24 0x6260
171 #define RK3399_TXRX_MASTERSLAVEZ BIT(7)
172 #define RK3399_TXRX_ENABLECLK BIT(6)
173 #define RK3399_TXRX_BASEDIR BIT(5)
174
175 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
176
177 #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
178
179 enum {
180 BANDGAP_97_07,
181 BANDGAP_98_05,
182 BANDGAP_99_02,
183 BANDGAP_100_00,
184 BANDGAP_93_17,
185 BANDGAP_94_15,
186 BANDGAP_95_12,
187 BANDGAP_96_10,
188 };
189
190 enum {
191 BIASEXTR_87_1,
192 BIASEXTR_91_5,
193 BIASEXTR_95_9,
194 BIASEXTR_100,
195 BIASEXTR_105_94,
196 BIASEXTR_111_88,
197 BIASEXTR_118_8,
198 BIASEXTR_127_7,
199 };
200
201 struct rockchip_dw_dsi_chip_data {
202 u32 reg;
203
204 u32 lcdsel_grf_reg;
205 u32 lcdsel_big;
206 u32 lcdsel_lit;
207
208 u32 enable_grf_reg;
209 u32 enable;
210
211 u32 lanecfg1_grf_reg;
212 u32 lanecfg1;
213 u32 lanecfg2_grf_reg;
214 u32 lanecfg2;
215
216 unsigned int flags;
217 unsigned int max_data_lanes;
218 };
219
220 struct dw_mipi_dsi_rockchip {
221 struct device *dev;
222 struct drm_encoder encoder;
223 void __iomem *base;
224
225 struct regmap *grf_regmap;
226 struct clk *pllref_clk;
227 struct clk *grf_clk;
228 struct clk *phy_cfg_clk;
229
230 /* dual-channel */
231 bool is_slave;
232 struct dw_mipi_dsi_rockchip *slave;
233
234 /* optional external dphy */
235 struct phy *phy;
236 union phy_configure_opts phy_opts;
237
238 unsigned int lane_mbps; /* per lane */
239 u16 input_div;
240 u16 feedback_div;
241 u32 format;
242
243 struct dw_mipi_dsi *dmd;
244 const struct rockchip_dw_dsi_chip_data *cdata;
245 struct dw_mipi_dsi_plat_data pdata;
246
247 bool dsi_bound;
248 };
249
250 struct dphy_pll_parameter_map {
251 unsigned int max_mbps;
252 u8 hsfreqrange;
253 u8 icpctrl;
254 u8 lpfctrl;
255 };
256
257 /* The table is based on 27MHz DPHY pll reference clock. */
258 static const struct dphy_pll_parameter_map dppa_map[] = {
259 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
260 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
261 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
262 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
263 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
264 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
265 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
266 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
267 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
268 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
269 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
270 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
271 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
272 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
273 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
274 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
275 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
276 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
277 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
278 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
279 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
280 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
281 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
282 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
283 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
284 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
285 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
286 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
287 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
288 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
289 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
290 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
291 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
292 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
293 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
294 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
295 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
296 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
297 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
298 };
299
max_mbps_to_parameter(unsigned int max_mbps)300 static int max_mbps_to_parameter(unsigned int max_mbps)
301 {
302 int i;
303
304 for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
305 if (dppa_map[i].max_mbps >= max_mbps)
306 return i;
307
308 return -EINVAL;
309 }
310
dsi_write(struct dw_mipi_dsi_rockchip * dsi,u32 reg,u32 val)311 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
312 {
313 writel(val, dsi->base + reg);
314 }
315
dsi_read(struct dw_mipi_dsi_rockchip * dsi,u32 reg)316 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
317 {
318 return readl(dsi->base + reg);
319 }
320
dsi_set(struct dw_mipi_dsi_rockchip * dsi,u32 reg,u32 mask)321 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
322 {
323 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
324 }
325
dsi_update_bits(struct dw_mipi_dsi_rockchip * dsi,u32 reg,u32 mask,u32 val)326 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
327 u32 mask, u32 val)
328 {
329 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
330 }
331
dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip * dsi,u8 test_code,u8 test_data)332 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
333 u8 test_code,
334 u8 test_data)
335 {
336 /*
337 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
338 * is latched internally as the current test code. Test data is
339 * programmed internally by rising edge on TESTCLK.
340 */
341 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
342
343 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
344 PHY_TESTDIN(test_code));
345
346 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
347
348 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
349 PHY_TESTDIN(test_data));
350
351 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
352 }
353
354 /**
355 * ns2bc - Nanoseconds to byte clock cycles
356 */
ns2bc(struct dw_mipi_dsi_rockchip * dsi,int ns)357 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
358 {
359 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
360 }
361
362 /**
363 * ns2ui - Nanoseconds to UI time periods
364 */
ns2ui(struct dw_mipi_dsi_rockchip * dsi,int ns)365 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
366 {
367 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
368 }
369
dw_mipi_dsi_phy_init(void * priv_data)370 static int dw_mipi_dsi_phy_init(void *priv_data)
371 {
372 struct dw_mipi_dsi_rockchip *dsi = priv_data;
373 int ret, i, vco;
374
375 if (dsi->phy)
376 return 0;
377
378 /*
379 * Get vco from frequency(lane_mbps)
380 * vco frequency table
381 * 000 - between 80 and 200 MHz
382 * 001 - between 200 and 300 MHz
383 * 010 - between 300 and 500 MHz
384 * 011 - between 500 and 700 MHz
385 * 100 - between 700 and 900 MHz
386 * 101 - between 900 and 1100 MHz
387 * 110 - between 1100 and 1300 MHz
388 * 111 - between 1300 and 1500 MHz
389 */
390 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
391
392 i = max_mbps_to_parameter(dsi->lane_mbps);
393 if (i < 0) {
394 DRM_DEV_ERROR(dsi->dev,
395 "failed to get parameter for %dmbps clock\n",
396 dsi->lane_mbps);
397 return i;
398 }
399
400 ret = clk_prepare_enable(dsi->phy_cfg_clk);
401 if (ret) {
402 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
403 return ret;
404 }
405
406 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
407 BYPASS_VCO_RANGE |
408 VCO_RANGE_CON_SEL(vco) |
409 VCO_IN_CAP_CON_LOW |
410 REF_BIAS_CUR_SEL);
411
412 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
413 CP_CURRENT_SEL(dppa_map[i].icpctrl));
414 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
415 CP_PROGRAM_EN | LPF_PROGRAM_EN |
416 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
417
418 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
419 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
420
421 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
422 INPUT_DIVIDER(dsi->input_div));
423 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
424 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
425 LOW_PROGRAM_EN);
426 /*
427 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
428 * to make the configured LSB effective according to IP simulation
429 * and lab test results.
430 * Only in this way can we get correct mipi phy pll frequency.
431 */
432 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
433 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
434 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
435 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
436 HIGH_PROGRAM_EN);
437 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
438 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
439
440 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
441 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
442 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
443 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
444
445 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
446 POWER_CONTROL | INTERNAL_REG_CURRENT |
447 BIAS_BLOCK_ON | BANDGAP_ON);
448
449 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
450 TER_RESISTOR_LOW | TER_CAL_DONE |
451 SETRD_MAX | TER_RESISTORS_ON);
452 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
453 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
454 SETRD_MAX | POWER_MANAGE |
455 TER_RESISTORS_ON);
456
457 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
458 TLP_PROGRAM_EN | ns2bc(dsi, 500));
459 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
460 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
461 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
462 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
463 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
464 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
465 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
466 BIT(5) | ns2bc(dsi, 100));
467 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
468 BIT(5) | (ns2bc(dsi, 60) + 7));
469
470 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
471 TLP_PROGRAM_EN | ns2bc(dsi, 500));
472 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
473 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
474 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
475 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
476 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
477 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
478 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
479 BIT(5) | ns2bc(dsi, 100));
480
481 clk_disable_unprepare(dsi->phy_cfg_clk);
482
483 return ret;
484 }
485
dw_mipi_dsi_phy_power_on(void * priv_data)486 static void dw_mipi_dsi_phy_power_on(void *priv_data)
487 {
488 struct dw_mipi_dsi_rockchip *dsi = priv_data;
489 int ret;
490
491 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
492 if (ret) {
493 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
494 return;
495 }
496
497 phy_configure(dsi->phy, &dsi->phy_opts);
498 phy_power_on(dsi->phy);
499 }
500
dw_mipi_dsi_phy_power_off(void * priv_data)501 static void dw_mipi_dsi_phy_power_off(void *priv_data)
502 {
503 struct dw_mipi_dsi_rockchip *dsi = priv_data;
504
505 phy_power_off(dsi->phy);
506 }
507
508 static int
dw_mipi_dsi_get_lane_mbps(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format,unsigned int * lane_mbps)509 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
510 unsigned long mode_flags, u32 lanes, u32 format,
511 unsigned int *lane_mbps)
512 {
513 struct dw_mipi_dsi_rockchip *dsi = priv_data;
514 int bpp;
515 unsigned long mpclk, tmp;
516 unsigned int target_mbps = 1000;
517 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
518 unsigned long best_freq = 0;
519 unsigned long fvco_min, fvco_max, fin, fout;
520 unsigned int min_prediv, max_prediv;
521 unsigned int _prediv, best_prediv;
522 unsigned long _fbdiv, best_fbdiv;
523 unsigned long min_delta = ULONG_MAX;
524
525 dsi->format = format;
526 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
527 if (bpp < 0) {
528 DRM_DEV_ERROR(dsi->dev,
529 "failed to get bpp for pixel format %d\n",
530 dsi->format);
531 return bpp;
532 }
533
534 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
535 if (mpclk) {
536 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
537 tmp = mpclk * (bpp / lanes) * 10 / 8;
538 if (tmp < max_mbps)
539 target_mbps = tmp;
540 else
541 DRM_DEV_ERROR(dsi->dev,
542 "DPHY clock frequency is out of range\n");
543 }
544
545 /* for external phy only a the mipi_dphy_config is necessary */
546 if (dsi->phy) {
547 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
548 bpp, lanes,
549 &dsi->phy_opts.mipi_dphy);
550 dsi->lane_mbps = target_mbps;
551 *lane_mbps = dsi->lane_mbps;
552
553 return 0;
554 }
555
556 fin = clk_get_rate(dsi->pllref_clk);
557 fout = target_mbps * USEC_PER_SEC;
558
559 /* constraint: 5Mhz <= Fref / N <= 40MHz */
560 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
561 max_prediv = fin / (5 * USEC_PER_SEC);
562
563 /* constraint: 80MHz <= Fvco <= 1500Mhz */
564 fvco_min = 80 * USEC_PER_SEC;
565 fvco_max = 1500 * USEC_PER_SEC;
566
567 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
568 u64 tmp;
569 u32 delta;
570 /* Fvco = Fref * M / N */
571 tmp = (u64)fout * _prediv;
572 do_div(tmp, fin);
573 _fbdiv = tmp;
574 /*
575 * Due to the use of a "by 2 pre-scaler," the range of the
576 * feedback multiplication value M is limited to even division
577 * numbers, and m must be greater than 6, not bigger than 512.
578 */
579 if (_fbdiv < 6 || _fbdiv > 512)
580 continue;
581
582 _fbdiv += _fbdiv % 2;
583
584 tmp = (u64)_fbdiv * fin;
585 do_div(tmp, _prediv);
586 if (tmp < fvco_min || tmp > fvco_max)
587 continue;
588
589 delta = abs(fout - tmp);
590 if (delta < min_delta) {
591 best_prediv = _prediv;
592 best_fbdiv = _fbdiv;
593 min_delta = delta;
594 best_freq = tmp;
595 }
596 }
597
598 if (best_freq) {
599 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
600 *lane_mbps = dsi->lane_mbps;
601 dsi->input_div = best_prediv;
602 dsi->feedback_div = best_fbdiv;
603 } else {
604 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
605 return -EINVAL;
606 }
607
608 return 0;
609 }
610
611 struct hstt {
612 unsigned int maxfreq;
613 struct dw_mipi_dsi_dphy_timing timing;
614 };
615
616 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \
617 { \
618 .maxfreq = _maxfreq, \
619 .timing = { \
620 .clk_lp2hs = _c_lp2hs, \
621 .clk_hs2lp = _c_hs2lp, \
622 .data_lp2hs = _d_lp2hs, \
623 .data_hs2lp = _d_hs2lp, \
624 } \
625 }
626
627 /* Table A-3 High-Speed Transition Times */
628 struct hstt hstt_table[] = {
629 HSTT( 90, 32, 20, 26, 13),
630 HSTT( 100, 35, 23, 28, 14),
631 HSTT( 110, 32, 22, 26, 13),
632 HSTT( 130, 31, 20, 27, 13),
633 HSTT( 140, 33, 22, 26, 14),
634 HSTT( 150, 33, 21, 26, 14),
635 HSTT( 170, 32, 20, 27, 13),
636 HSTT( 180, 36, 23, 30, 15),
637 HSTT( 200, 40, 22, 33, 15),
638 HSTT( 220, 40, 22, 33, 15),
639 HSTT( 240, 44, 24, 36, 16),
640 HSTT( 250, 48, 24, 38, 17),
641 HSTT( 270, 48, 24, 38, 17),
642 HSTT( 300, 50, 27, 41, 18),
643 HSTT( 330, 56, 28, 45, 18),
644 HSTT( 360, 59, 28, 48, 19),
645 HSTT( 400, 61, 30, 50, 20),
646 HSTT( 450, 67, 31, 55, 21),
647 HSTT( 500, 73, 31, 59, 22),
648 HSTT( 550, 79, 36, 63, 24),
649 HSTT( 600, 83, 37, 68, 25),
650 HSTT( 650, 90, 38, 73, 27),
651 HSTT( 700, 95, 40, 77, 28),
652 HSTT( 750, 102, 40, 84, 28),
653 HSTT( 800, 106, 42, 87, 30),
654 HSTT( 850, 113, 44, 93, 31),
655 HSTT( 900, 118, 47, 98, 32),
656 HSTT( 950, 124, 47, 102, 34),
657 HSTT(1000, 130, 49, 107, 35),
658 HSTT(1050, 135, 51, 111, 37),
659 HSTT(1100, 139, 51, 114, 38),
660 HSTT(1150, 146, 54, 120, 40),
661 HSTT(1200, 153, 57, 125, 41),
662 HSTT(1250, 158, 58, 130, 42),
663 HSTT(1300, 163, 58, 135, 44),
664 HSTT(1350, 168, 60, 140, 45),
665 HSTT(1400, 172, 64, 144, 47),
666 HSTT(1450, 176, 65, 148, 48),
667 HSTT(1500, 181, 66, 153, 50)
668 };
669
670 static int
dw_mipi_dsi_phy_get_timing(void * priv_data,unsigned int lane_mbps,struct dw_mipi_dsi_dphy_timing * timing)671 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
672 struct dw_mipi_dsi_dphy_timing *timing)
673 {
674 int i;
675
676 for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
677 if (lane_mbps < hstt_table[i].maxfreq)
678 break;
679
680 if (i == ARRAY_SIZE(hstt_table))
681 i--;
682
683 *timing = hstt_table[i].timing;
684
685 return 0;
686 }
687
688 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
689 .init = dw_mipi_dsi_phy_init,
690 .power_on = dw_mipi_dsi_phy_power_on,
691 .power_off = dw_mipi_dsi_phy_power_off,
692 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
693 .get_timing = dw_mipi_dsi_phy_get_timing,
694 };
695
dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip * dsi)696 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
697 {
698 if (dsi->cdata->lanecfg1_grf_reg)
699 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
700 dsi->cdata->lanecfg1);
701
702 if (dsi->cdata->lanecfg2_grf_reg)
703 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
704 dsi->cdata->lanecfg2);
705
706 if (dsi->cdata->enable_grf_reg)
707 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
708 dsi->cdata->enable);
709 }
710
dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip * dsi,int mux)711 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
712 int mux)
713 {
714 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
715 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
716 }
717
718 static int
dw_mipi_dsi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)719 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
720 struct drm_crtc_state *crtc_state,
721 struct drm_connector_state *conn_state)
722 {
723 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
724 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
725
726 switch (dsi->format) {
727 case MIPI_DSI_FMT_RGB888:
728 s->output_mode = ROCKCHIP_OUT_MODE_P888;
729 break;
730 case MIPI_DSI_FMT_RGB666:
731 s->output_mode = ROCKCHIP_OUT_MODE_P666;
732 break;
733 case MIPI_DSI_FMT_RGB565:
734 s->output_mode = ROCKCHIP_OUT_MODE_P565;
735 break;
736 default:
737 WARN_ON(1);
738 return -EINVAL;
739 }
740
741 s->output_type = DRM_MODE_CONNECTOR_DSI;
742 if (dsi->slave)
743 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
744
745 return 0;
746 }
747
dw_mipi_dsi_encoder_enable(struct drm_encoder * encoder)748 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
749 {
750 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
751 int ret, mux;
752
753 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
754 &dsi->encoder);
755 if (mux < 0)
756 return;
757
758 /*
759 * For the RK3399, the clk of grf must be enabled before writing grf
760 * register. And for RK3288 or other soc, this grf_clk must be NULL,
761 * the clk_prepare_enable return true directly.
762 */
763 ret = clk_prepare_enable(dsi->grf_clk);
764 if (ret) {
765 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
766 return;
767 }
768
769 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
770 if (dsi->slave)
771 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
772
773 clk_disable_unprepare(dsi->grf_clk);
774 }
775
776 static const struct drm_encoder_helper_funcs
777 dw_mipi_dsi_encoder_helper_funcs = {
778 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
779 .enable = dw_mipi_dsi_encoder_enable,
780 };
781
rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip * dsi,struct drm_device * drm_dev)782 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
783 struct drm_device *drm_dev)
784 {
785 struct drm_encoder *encoder = &dsi->encoder;
786 int ret;
787
788 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
789 dsi->dev->of_node);
790
791 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
792 if (ret) {
793 DRM_ERROR("Failed to initialize encoder with drm\n");
794 return ret;
795 }
796
797 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
798
799 return 0;
800 }
801
802 static struct device
dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip * dsi)803 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
804 {
805 const struct of_device_id *match;
806 struct device_node *node = NULL, *local;
807
808 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
809
810 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
811 if (!local)
812 return NULL;
813
814 while ((node = of_find_compatible_node(node, NULL,
815 match->compatible))) {
816 struct device_node *remote;
817
818 /* found ourself */
819 if (node == dsi->dev->of_node)
820 continue;
821
822 remote = of_graph_get_remote_node(node, 1, 0);
823 if (!remote)
824 continue;
825
826 /* same display device in port1-ep0 for both */
827 if (remote == local) {
828 struct dw_mipi_dsi_rockchip *dsi2;
829 struct platform_device *pdev;
830
831 pdev = of_find_device_by_node(node);
832
833 /*
834 * we have found the second, so will either return it
835 * or return with an error. In any case won't need the
836 * nodes anymore nor continue the loop.
837 */
838 of_node_put(remote);
839 of_node_put(node);
840 of_node_put(local);
841
842 if (!pdev)
843 return ERR_PTR(-EPROBE_DEFER);
844
845 dsi2 = platform_get_drvdata(pdev);
846 if (!dsi2) {
847 platform_device_put(pdev);
848 return ERR_PTR(-EPROBE_DEFER);
849 }
850
851 return &pdev->dev;
852 }
853
854 of_node_put(remote);
855 }
856
857 of_node_put(local);
858
859 return NULL;
860 }
861
dw_mipi_dsi_rockchip_bind(struct device * dev,struct device * master,void * data)862 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
863 struct device *master,
864 void *data)
865 {
866 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
867 struct drm_device *drm_dev = data;
868 struct device *second;
869 bool master1, master2;
870 int ret;
871
872 second = dw_mipi_dsi_rockchip_find_second(dsi);
873 if (IS_ERR(second))
874 return PTR_ERR(second);
875
876 if (second) {
877 master1 = of_property_read_bool(dsi->dev->of_node,
878 "clock-master");
879 master2 = of_property_read_bool(second->of_node,
880 "clock-master");
881
882 if (master1 && master2) {
883 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
884 return -EINVAL;
885 }
886
887 if (!master1 && !master2) {
888 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
889 return -EINVAL;
890 }
891
892 /* we are the slave in dual-DSI */
893 if (!master1) {
894 dsi->is_slave = true;
895 return 0;
896 }
897
898 dsi->slave = dev_get_drvdata(second);
899 if (!dsi->slave) {
900 DRM_DEV_ERROR(dev, "could not get slaves data\n");
901 return -ENODEV;
902 }
903
904 dsi->slave->is_slave = true;
905 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
906 put_device(second);
907 }
908
909 pm_runtime_get_sync(dsi->dev);
910 if (dsi->slave)
911 pm_runtime_get_sync(dsi->slave->dev);
912
913 ret = clk_prepare_enable(dsi->pllref_clk);
914 if (ret) {
915 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
916 goto out_pm_runtime;
917 }
918
919 /*
920 * With the GRF clock running, write lane and dual-mode configurations
921 * that won't change immediately. If we waited until enable() to do
922 * this, things like panel preparation would not be able to send
923 * commands over DSI.
924 */
925 ret = clk_prepare_enable(dsi->grf_clk);
926 if (ret) {
927 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
928 goto out_pll_clk;
929 }
930
931 dw_mipi_dsi_rockchip_config(dsi);
932 if (dsi->slave)
933 dw_mipi_dsi_rockchip_config(dsi->slave);
934
935 clk_disable_unprepare(dsi->grf_clk);
936
937 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
938 if (ret) {
939 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
940 goto out_pll_clk;
941 }
942
943 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
944 if (ret) {
945 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
946 goto out_pll_clk;
947 }
948
949 dsi->dsi_bound = true;
950
951 return 0;
952
953 out_pll_clk:
954 clk_disable_unprepare(dsi->pllref_clk);
955 out_pm_runtime:
956 pm_runtime_put(dsi->dev);
957 if (dsi->slave)
958 pm_runtime_put(dsi->slave->dev);
959
960 return ret;
961 }
962
dw_mipi_dsi_rockchip_unbind(struct device * dev,struct device * master,void * data)963 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
964 struct device *master,
965 void *data)
966 {
967 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
968
969 if (dsi->is_slave)
970 return;
971
972 dsi->dsi_bound = false;
973
974 dw_mipi_dsi_unbind(dsi->dmd);
975
976 clk_disable_unprepare(dsi->pllref_clk);
977
978 pm_runtime_put(dsi->dev);
979 if (dsi->slave)
980 pm_runtime_put(dsi->slave->dev);
981 }
982
983 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
984 .bind = dw_mipi_dsi_rockchip_bind,
985 .unbind = dw_mipi_dsi_rockchip_unbind,
986 };
987
dw_mipi_dsi_rockchip_host_attach(void * priv_data,struct mipi_dsi_device * device)988 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
989 struct mipi_dsi_device *device)
990 {
991 struct dw_mipi_dsi_rockchip *dsi = priv_data;
992 struct device *second;
993 int ret;
994
995 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
996 if (ret) {
997 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
998 ret);
999 return ret;
1000 }
1001
1002 second = dw_mipi_dsi_rockchip_find_second(dsi);
1003 if (IS_ERR(second))
1004 return PTR_ERR(second);
1005 if (second) {
1006 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
1007 if (ret) {
1008 DRM_DEV_ERROR(second,
1009 "Failed to register component: %d\n",
1010 ret);
1011 return ret;
1012 }
1013 }
1014
1015 return 0;
1016 }
1017
dw_mipi_dsi_rockchip_host_detach(void * priv_data,struct mipi_dsi_device * device)1018 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
1019 struct mipi_dsi_device *device)
1020 {
1021 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1022 struct device *second;
1023
1024 second = dw_mipi_dsi_rockchip_find_second(dsi);
1025 if (second && !IS_ERR(second))
1026 component_del(second, &dw_mipi_dsi_rockchip_ops);
1027
1028 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1029
1030 return 0;
1031 }
1032
1033 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
1034 .attach = dw_mipi_dsi_rockchip_host_attach,
1035 .detach = dw_mipi_dsi_rockchip_host_detach,
1036 };
1037
dw_mipi_dsi_rockchip_resume(struct device * dev)1038 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev)
1039 {
1040 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1041 int ret;
1042
1043 /*
1044 * Re-configure DSI state, if we were previously initialized. We need
1045 * to do this before rockchip_drm_drv tries to re-enable() any panels.
1046 */
1047 if (dsi->dsi_bound) {
1048 ret = clk_prepare_enable(dsi->grf_clk);
1049 if (ret) {
1050 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1051 return ret;
1052 }
1053
1054 dw_mipi_dsi_rockchip_config(dsi);
1055 if (dsi->slave)
1056 dw_mipi_dsi_rockchip_config(dsi->slave);
1057
1058 clk_disable_unprepare(dsi->grf_clk);
1059 }
1060
1061 return 0;
1062 }
1063
1064 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = {
1065 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume)
1066 };
1067
dw_mipi_dsi_rockchip_probe(struct platform_device * pdev)1068 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1069 {
1070 struct device *dev = &pdev->dev;
1071 struct device_node *np = dev->of_node;
1072 struct dw_mipi_dsi_rockchip *dsi;
1073 struct resource *res;
1074 const struct rockchip_dw_dsi_chip_data *cdata =
1075 of_device_get_match_data(dev);
1076 int ret, i;
1077
1078 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1079 if (!dsi)
1080 return -ENOMEM;
1081
1082 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1083 dsi->base = devm_ioremap_resource(dev, res);
1084 if (IS_ERR(dsi->base)) {
1085 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1086 return PTR_ERR(dsi->base);
1087 }
1088
1089 i = 0;
1090 while (cdata[i].reg) {
1091 if (cdata[i].reg == res->start) {
1092 dsi->cdata = &cdata[i];
1093 break;
1094 }
1095
1096 i++;
1097 }
1098
1099 if (!dsi->cdata) {
1100 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1101 return -EINVAL;
1102 }
1103
1104 /* try to get a possible external dphy */
1105 dsi->phy = devm_phy_optional_get(dev, "dphy");
1106 if (IS_ERR(dsi->phy)) {
1107 ret = PTR_ERR(dsi->phy);
1108 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1109 return ret;
1110 }
1111
1112 dsi->pllref_clk = devm_clk_get(dev, "ref");
1113 if (IS_ERR(dsi->pllref_clk)) {
1114 if (dsi->phy) {
1115 /*
1116 * if external phy is present, pll will be
1117 * generated there.
1118 */
1119 dsi->pllref_clk = NULL;
1120 } else {
1121 ret = PTR_ERR(dsi->pllref_clk);
1122 DRM_DEV_ERROR(dev,
1123 "Unable to get pll reference clock: %d\n",
1124 ret);
1125 return ret;
1126 }
1127 }
1128
1129 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1130 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1131 if (IS_ERR(dsi->phy_cfg_clk)) {
1132 ret = PTR_ERR(dsi->phy_cfg_clk);
1133 DRM_DEV_ERROR(dev,
1134 "Unable to get phy_cfg_clk: %d\n", ret);
1135 return ret;
1136 }
1137 }
1138
1139 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1140 dsi->grf_clk = devm_clk_get(dev, "grf");
1141 if (IS_ERR(dsi->grf_clk)) {
1142 ret = PTR_ERR(dsi->grf_clk);
1143 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1144 return ret;
1145 }
1146 }
1147
1148 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1149 if (IS_ERR(dsi->grf_regmap)) {
1150 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
1151 return PTR_ERR(dsi->grf_regmap);
1152 }
1153
1154 dsi->dev = dev;
1155 dsi->pdata.base = dsi->base;
1156 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1157 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1158 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1159 dsi->pdata.priv_data = dsi;
1160 platform_set_drvdata(pdev, dsi);
1161
1162 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1163 if (IS_ERR(dsi->dmd)) {
1164 ret = PTR_ERR(dsi->dmd);
1165 if (ret != -EPROBE_DEFER)
1166 DRM_DEV_ERROR(dev,
1167 "Failed to probe dw_mipi_dsi: %d\n", ret);
1168 return ret;
1169 }
1170
1171 return 0;
1172 }
1173
dw_mipi_dsi_rockchip_remove(struct platform_device * pdev)1174 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1175 {
1176 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1177
1178 dw_mipi_dsi_remove(dsi->dmd);
1179
1180 return 0;
1181 }
1182
1183 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
1184 {
1185 .reg = 0xff450000,
1186 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1187 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1188 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1189 PX30_DSI_LCDC_SEL),
1190
1191 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1192 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1193 PX30_DSI_FORCERXMODE |
1194 PX30_DSI_FORCETXSTOPMODE),
1195
1196 .max_data_lanes = 4,
1197 },
1198 { /* sentinel */ }
1199 };
1200
1201 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1202 {
1203 .reg = 0xff960000,
1204 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1205 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1206 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1207
1208 .max_data_lanes = 4,
1209 },
1210 {
1211 .reg = 0xff964000,
1212 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1213 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1214 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1215
1216 .max_data_lanes = 4,
1217 },
1218 { /* sentinel */ }
1219 };
1220
1221 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1222 {
1223 .reg = 0xff960000,
1224 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1225 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1226 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1227 RK3399_DSI0_LCDC_SEL),
1228
1229 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1230 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1231 RK3399_DSI0_TURNDISABLE |
1232 RK3399_DSI0_FORCETXSTOPMODE |
1233 RK3399_DSI0_FORCERXMODE),
1234
1235 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1236 .max_data_lanes = 4,
1237 },
1238 {
1239 .reg = 0xff968000,
1240 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1241 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1242 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1243 RK3399_DSI1_LCDC_SEL),
1244
1245 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1246 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1247 RK3399_DSI1_FORCETXSTOPMODE |
1248 RK3399_DSI1_FORCERXMODE |
1249 RK3399_DSI1_ENABLE),
1250
1251 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1252 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1253 RK3399_TXRX_ENABLECLK,
1254 RK3399_TXRX_MASTERSLAVEZ |
1255 RK3399_TXRX_ENABLECLK |
1256 RK3399_TXRX_BASEDIR),
1257
1258 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1259 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1260
1261 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1262 .max_data_lanes = 4,
1263 },
1264 { /* sentinel */ }
1265 };
1266
1267 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1268 {
1269 .compatible = "rockchip,px30-mipi-dsi",
1270 .data = &px30_chip_data,
1271 }, {
1272 .compatible = "rockchip,rk3288-mipi-dsi",
1273 .data = &rk3288_chip_data,
1274 }, {
1275 .compatible = "rockchip,rk3399-mipi-dsi",
1276 .data = &rk3399_chip_data,
1277 },
1278 { /* sentinel */ }
1279 };
1280 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1281
1282 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1283 .probe = dw_mipi_dsi_rockchip_probe,
1284 .remove = dw_mipi_dsi_rockchip_remove,
1285 .driver = {
1286 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1287 .pm = &dw_mipi_dsi_rockchip_pm_ops,
1288 .name = "dw-mipi-dsi-rockchip",
1289 /*
1290 * For dual-DSI display, one DSI pokes at the other DSI's
1291 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not
1292 * safe for asynchronous probe.
1293 */
1294 .probe_type = PROBE_FORCE_SYNCHRONOUS,
1295 },
1296 };
1297