1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
4 *
5 * Copyright (c) 2010 Ericsson AB.
6 *
7 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
8 *
9 * JC42.4 compliant temperature sensors are typically used on memory modules.
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/slab.h>
16 #include <linux/jiffies.h>
17 #include <linux/i2c.h>
18 #include <linux/hwmon.h>
19 #include <linux/err.h>
20 #include <linux/mutex.h>
21 #include <linux/of.h>
22 #include <linux/regmap.h>
23
24 /* Addresses to scan */
25 static const unsigned short normal_i2c[] = {
26 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
27
28 /* JC42 registers. All registers are 16 bit. */
29 #define JC42_REG_CAP 0x00
30 #define JC42_REG_CONFIG 0x01
31 #define JC42_REG_TEMP_UPPER 0x02
32 #define JC42_REG_TEMP_LOWER 0x03
33 #define JC42_REG_TEMP_CRITICAL 0x04
34 #define JC42_REG_TEMP 0x05
35 #define JC42_REG_MANID 0x06
36 #define JC42_REG_DEVICEID 0x07
37 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
38
39 /* Status bits in temperature register */
40 #define JC42_ALARM_CRIT_BIT 15
41 #define JC42_ALARM_MAX_BIT 14
42 #define JC42_ALARM_MIN_BIT 13
43
44 /* Configuration register defines */
45 #define JC42_CFG_CRIT_ONLY (1 << 2)
46 #define JC42_CFG_TCRIT_LOCK (1 << 6)
47 #define JC42_CFG_EVENT_LOCK (1 << 7)
48 #define JC42_CFG_SHUTDOWN (1 << 8)
49 #define JC42_CFG_HYST_SHIFT 9
50 #define JC42_CFG_HYST_MASK (0x03 << 9)
51
52 /* Capabilities */
53 #define JC42_CAP_RANGE (1 << 2)
54
55 /* Manufacturer IDs */
56 #define ADT_MANID 0x11d4 /* Analog Devices */
57 #define ATMEL_MANID 0x001f /* Atmel */
58 #define ATMEL_MANID2 0x1114 /* Atmel */
59 #define MAX_MANID 0x004d /* Maxim */
60 #define IDT_MANID 0x00b3 /* IDT */
61 #define MCP_MANID 0x0054 /* Microchip */
62 #define NXP_MANID 0x1131 /* NXP Semiconductors */
63 #define ONS_MANID 0x1b09 /* ON Semiconductor */
64 #define STM_MANID 0x104a /* ST Microelectronics */
65 #define GT_MANID 0x1c68 /* Giantec */
66 #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
67
68 /* SMBUS register */
69 #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
70
71 /* Supported chips */
72
73 /* Analog Devices */
74 #define ADT7408_DEVID 0x0801
75 #define ADT7408_DEVID_MASK 0xffff
76
77 /* Atmel */
78 #define AT30TS00_DEVID 0x8201
79 #define AT30TS00_DEVID_MASK 0xffff
80
81 #define AT30TSE004_DEVID 0x2200
82 #define AT30TSE004_DEVID_MASK 0xffff
83
84 /* Giantec */
85 #define GT30TS00_DEVID 0x2200
86 #define GT30TS00_DEVID_MASK 0xff00
87
88 #define GT34TS02_DEVID 0x3300
89 #define GT34TS02_DEVID_MASK 0xff00
90
91 /* IDT */
92 #define TSE2004_DEVID 0x2200
93 #define TSE2004_DEVID_MASK 0xff00
94
95 #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
96 #define TS3000_DEVID_MASK 0xff00
97
98 #define TS3001_DEVID 0x3000
99 #define TS3001_DEVID_MASK 0xff00
100
101 /* Maxim */
102 #define MAX6604_DEVID 0x3e00
103 #define MAX6604_DEVID_MASK 0xffff
104
105 /* Microchip */
106 #define MCP9804_DEVID 0x0200
107 #define MCP9804_DEVID_MASK 0xfffc
108
109 #define MCP9808_DEVID 0x0400
110 #define MCP9808_DEVID_MASK 0xfffc
111
112 #define MCP98242_DEVID 0x2000
113 #define MCP98242_DEVID_MASK 0xfffc
114
115 #define MCP98243_DEVID 0x2100
116 #define MCP98243_DEVID_MASK 0xfffc
117
118 #define MCP98244_DEVID 0x2200
119 #define MCP98244_DEVID_MASK 0xfffc
120
121 #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
122 #define MCP9843_DEVID_MASK 0xfffe
123
124 /* NXP */
125 #define SE97_DEVID 0xa200
126 #define SE97_DEVID_MASK 0xfffc
127
128 #define SE98_DEVID 0xa100
129 #define SE98_DEVID_MASK 0xfffc
130
131 /* ON Semiconductor */
132 #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
133 #define CAT6095_DEVID_MASK 0xffe0
134
135 #define CAT34TS02C_DEVID 0x0a00
136 #define CAT34TS02C_DEVID_MASK 0xfff0
137
138 #define CAT34TS04_DEVID 0x2200
139 #define CAT34TS04_DEVID_MASK 0xfff0
140
141 /* ST Microelectronics */
142 #define STTS424_DEVID 0x0101
143 #define STTS424_DEVID_MASK 0xffff
144
145 #define STTS424E_DEVID 0x0000
146 #define STTS424E_DEVID_MASK 0xfffe
147
148 #define STTS2002_DEVID 0x0300
149 #define STTS2002_DEVID_MASK 0xffff
150
151 #define STTS2004_DEVID 0x2201
152 #define STTS2004_DEVID_MASK 0xffff
153
154 #define STTS3000_DEVID 0x0200
155 #define STTS3000_DEVID_MASK 0xffff
156
157 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
158
159 struct jc42_chips {
160 u16 manid;
161 u16 devid;
162 u16 devid_mask;
163 };
164
165 static struct jc42_chips jc42_chips[] = {
166 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
167 { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
168 { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
169 { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
170 { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
171 { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
172 { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
173 { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
174 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
175 { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
176 { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
177 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
178 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
179 { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
180 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
181 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
182 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
183 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
184 { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
185 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
186 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
187 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
188 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
189 { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
190 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
191 };
192
193 /* Each client has this additional data */
194 struct jc42_data {
195 struct mutex update_lock; /* protect register access */
196 struct regmap *regmap;
197 bool extended; /* true if extended range supported */
198 bool valid;
199 u16 orig_config; /* original configuration */
200 u16 config; /* current configuration */
201 };
202
203 #define JC42_TEMP_MIN_EXTENDED (-40000)
204 #define JC42_TEMP_MIN 0
205 #define JC42_TEMP_MAX 125000
206
jc42_temp_to_reg(long temp,bool extended)207 static u16 jc42_temp_to_reg(long temp, bool extended)
208 {
209 int ntemp = clamp_val(temp,
210 extended ? JC42_TEMP_MIN_EXTENDED :
211 JC42_TEMP_MIN, JC42_TEMP_MAX);
212
213 /* convert from 0.001 to 0.0625 resolution */
214 return (ntemp * 2 / 125) & 0x1fff;
215 }
216
jc42_temp_from_reg(s16 reg)217 static int jc42_temp_from_reg(s16 reg)
218 {
219 reg = sign_extend32(reg, 12);
220
221 /* convert from 0.0625 to 0.001 resolution */
222 return reg * 125 / 2;
223 }
224
jc42_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)225 static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
226 u32 attr, int channel, long *val)
227 {
228 struct jc42_data *data = dev_get_drvdata(dev);
229 unsigned int regval;
230 int ret, temp, hyst;
231
232 mutex_lock(&data->update_lock);
233
234 switch (attr) {
235 case hwmon_temp_input:
236 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
237 if (ret)
238 break;
239
240 *val = jc42_temp_from_reg(regval);
241 break;
242 case hwmon_temp_min:
243 ret = regmap_read(data->regmap, JC42_REG_TEMP_LOWER, ®val);
244 if (ret)
245 break;
246
247 *val = jc42_temp_from_reg(regval);
248 break;
249 case hwmon_temp_max:
250 ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val);
251 if (ret)
252 break;
253
254 *val = jc42_temp_from_reg(regval);
255 break;
256 case hwmon_temp_crit:
257 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
258 ®val);
259 if (ret)
260 break;
261
262 *val = jc42_temp_from_reg(regval);
263 break;
264 case hwmon_temp_max_hyst:
265 ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val);
266 if (ret)
267 break;
268
269 temp = jc42_temp_from_reg(regval);
270 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
271 >> JC42_CFG_HYST_SHIFT];
272 *val = temp - hyst;
273 break;
274 case hwmon_temp_crit_hyst:
275 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
276 ®val);
277 if (ret)
278 break;
279
280 temp = jc42_temp_from_reg(regval);
281 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
282 >> JC42_CFG_HYST_SHIFT];
283 *val = temp - hyst;
284 break;
285 case hwmon_temp_min_alarm:
286 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
287 if (ret)
288 break;
289
290 *val = (regval >> JC42_ALARM_MIN_BIT) & 1;
291 break;
292 case hwmon_temp_max_alarm:
293 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
294 if (ret)
295 break;
296
297 *val = (regval >> JC42_ALARM_MAX_BIT) & 1;
298 break;
299 case hwmon_temp_crit_alarm:
300 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
301 if (ret)
302 break;
303
304 *val = (regval >> JC42_ALARM_CRIT_BIT) & 1;
305 break;
306 default:
307 ret = -EOPNOTSUPP;
308 break;
309 }
310
311 mutex_unlock(&data->update_lock);
312
313 return ret;
314 }
315
jc42_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)316 static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
317 u32 attr, int channel, long val)
318 {
319 struct jc42_data *data = dev_get_drvdata(dev);
320 unsigned int regval;
321 int diff, hyst;
322 int ret;
323
324 mutex_lock(&data->update_lock);
325
326 switch (attr) {
327 case hwmon_temp_min:
328 ret = regmap_write(data->regmap, JC42_REG_TEMP_LOWER,
329 jc42_temp_to_reg(val, data->extended));
330 break;
331 case hwmon_temp_max:
332 ret = regmap_write(data->regmap, JC42_REG_TEMP_UPPER,
333 jc42_temp_to_reg(val, data->extended));
334 break;
335 case hwmon_temp_crit:
336 ret = regmap_write(data->regmap, JC42_REG_TEMP_CRITICAL,
337 jc42_temp_to_reg(val, data->extended));
338 break;
339 case hwmon_temp_crit_hyst:
340 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
341 ®val);
342 if (ret)
343 break;
344
345 /*
346 * JC42.4 compliant chips only support four hysteresis values.
347 * Pick best choice and go from there.
348 */
349 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
350 : JC42_TEMP_MIN) - 6000,
351 JC42_TEMP_MAX);
352 diff = jc42_temp_from_reg(regval) - val;
353 hyst = 0;
354 if (diff > 0) {
355 if (diff < 2250)
356 hyst = 1; /* 1.5 degrees C */
357 else if (diff < 4500)
358 hyst = 2; /* 3.0 degrees C */
359 else
360 hyst = 3; /* 6.0 degrees C */
361 }
362 data->config = (data->config & ~JC42_CFG_HYST_MASK) |
363 (hyst << JC42_CFG_HYST_SHIFT);
364 ret = regmap_write(data->regmap, JC42_REG_CONFIG,
365 data->config);
366 break;
367 default:
368 ret = -EOPNOTSUPP;
369 break;
370 }
371
372 mutex_unlock(&data->update_lock);
373
374 return ret;
375 }
376
jc42_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)377 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
378 u32 attr, int channel)
379 {
380 const struct jc42_data *data = _data;
381 unsigned int config = data->config;
382 umode_t mode = 0444;
383
384 switch (attr) {
385 case hwmon_temp_min:
386 case hwmon_temp_max:
387 if (!(config & JC42_CFG_EVENT_LOCK))
388 mode |= 0200;
389 break;
390 case hwmon_temp_crit:
391 if (!(config & JC42_CFG_TCRIT_LOCK))
392 mode |= 0200;
393 break;
394 case hwmon_temp_crit_hyst:
395 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
396 mode |= 0200;
397 break;
398 case hwmon_temp_input:
399 case hwmon_temp_max_hyst:
400 case hwmon_temp_min_alarm:
401 case hwmon_temp_max_alarm:
402 case hwmon_temp_crit_alarm:
403 break;
404 default:
405 mode = 0;
406 break;
407 }
408 return mode;
409 }
410
411 /* Return 0 if detection is successful, -ENODEV otherwise */
jc42_detect(struct i2c_client * client,struct i2c_board_info * info)412 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
413 {
414 struct i2c_adapter *adapter = client->adapter;
415 int i, config, cap, manid, devid;
416
417 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
418 I2C_FUNC_SMBUS_WORD_DATA))
419 return -ENODEV;
420
421 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
422 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
423 manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
424 devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
425
426 if (cap < 0 || config < 0 || manid < 0 || devid < 0)
427 return -ENODEV;
428
429 if ((cap & 0xff00) || (config & 0xf800))
430 return -ENODEV;
431
432 for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
433 struct jc42_chips *chip = &jc42_chips[i];
434 if (manid == chip->manid &&
435 (devid & chip->devid_mask) == chip->devid) {
436 strlcpy(info->type, "jc42", I2C_NAME_SIZE);
437 return 0;
438 }
439 }
440 return -ENODEV;
441 }
442
443 static const struct hwmon_channel_info *jc42_info[] = {
444 HWMON_CHANNEL_INFO(temp,
445 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
446 HWMON_T_CRIT | HWMON_T_MAX_HYST |
447 HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
448 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
449 NULL
450 };
451
452 static const struct hwmon_ops jc42_hwmon_ops = {
453 .is_visible = jc42_is_visible,
454 .read = jc42_read,
455 .write = jc42_write,
456 };
457
458 static const struct hwmon_chip_info jc42_chip_info = {
459 .ops = &jc42_hwmon_ops,
460 .info = jc42_info,
461 };
462
jc42_readable_reg(struct device * dev,unsigned int reg)463 static bool jc42_readable_reg(struct device *dev, unsigned int reg)
464 {
465 return (reg >= JC42_REG_CAP && reg <= JC42_REG_DEVICEID) ||
466 reg == JC42_REG_SMBUS;
467 }
468
jc42_writable_reg(struct device * dev,unsigned int reg)469 static bool jc42_writable_reg(struct device *dev, unsigned int reg)
470 {
471 return (reg >= JC42_REG_CONFIG && reg <= JC42_REG_TEMP_CRITICAL) ||
472 reg == JC42_REG_SMBUS;
473 }
474
jc42_volatile_reg(struct device * dev,unsigned int reg)475 static bool jc42_volatile_reg(struct device *dev, unsigned int reg)
476 {
477 return reg == JC42_REG_CONFIG || reg == JC42_REG_TEMP;
478 }
479
480 static const struct regmap_config jc42_regmap_config = {
481 .reg_bits = 8,
482 .val_bits = 16,
483 .val_format_endian = REGMAP_ENDIAN_BIG,
484 .max_register = JC42_REG_SMBUS,
485 .writeable_reg = jc42_writable_reg,
486 .readable_reg = jc42_readable_reg,
487 .volatile_reg = jc42_volatile_reg,
488 .cache_type = REGCACHE_RBTREE,
489 };
490
jc42_probe(struct i2c_client * client)491 static int jc42_probe(struct i2c_client *client)
492 {
493 struct device *dev = &client->dev;
494 struct device *hwmon_dev;
495 unsigned int config, cap;
496 struct jc42_data *data;
497 int ret;
498
499 data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
500 if (!data)
501 return -ENOMEM;
502
503 data->regmap = devm_regmap_init_i2c(client, &jc42_regmap_config);
504 if (IS_ERR(data->regmap))
505 return PTR_ERR(data->regmap);
506
507 i2c_set_clientdata(client, data);
508 mutex_init(&data->update_lock);
509
510 ret = regmap_read(data->regmap, JC42_REG_CAP, &cap);
511 if (ret)
512 return ret;
513
514 data->extended = !!(cap & JC42_CAP_RANGE);
515
516 if (device_property_read_bool(dev, "smbus-timeout-disable")) {
517 /*
518 * Not all chips support this register, but from a
519 * quick read of various datasheets no chip appears
520 * incompatible with the below attempt to disable
521 * the timeout. And the whole thing is opt-in...
522 */
523 ret = regmap_set_bits(data->regmap, JC42_REG_SMBUS,
524 SMBUS_STMOUT);
525 if (ret)
526 return ret;
527 }
528
529 ret = regmap_read(data->regmap, JC42_REG_CONFIG, &config);
530 if (ret)
531 return ret;
532
533 data->orig_config = config;
534 if (config & JC42_CFG_SHUTDOWN) {
535 config &= ~JC42_CFG_SHUTDOWN;
536 regmap_write(data->regmap, JC42_REG_CONFIG, config);
537 }
538 data->config = config;
539
540 hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
541 data, &jc42_chip_info,
542 NULL);
543 return PTR_ERR_OR_ZERO(hwmon_dev);
544 }
545
jc42_remove(struct i2c_client * client)546 static int jc42_remove(struct i2c_client *client)
547 {
548 struct jc42_data *data = i2c_get_clientdata(client);
549
550 /* Restore original configuration except hysteresis */
551 if ((data->config & ~JC42_CFG_HYST_MASK) !=
552 (data->orig_config & ~JC42_CFG_HYST_MASK)) {
553 int config;
554
555 config = (data->orig_config & ~JC42_CFG_HYST_MASK)
556 | (data->config & JC42_CFG_HYST_MASK);
557 regmap_write(data->regmap, JC42_REG_CONFIG, config);
558 }
559 return 0;
560 }
561
562 #ifdef CONFIG_PM
563
jc42_suspend(struct device * dev)564 static int jc42_suspend(struct device *dev)
565 {
566 struct jc42_data *data = dev_get_drvdata(dev);
567
568 data->config |= JC42_CFG_SHUTDOWN;
569 regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
570
571 regcache_cache_only(data->regmap, true);
572 regcache_mark_dirty(data->regmap);
573
574 return 0;
575 }
576
jc42_resume(struct device * dev)577 static int jc42_resume(struct device *dev)
578 {
579 struct jc42_data *data = dev_get_drvdata(dev);
580
581 regcache_cache_only(data->regmap, false);
582
583 data->config &= ~JC42_CFG_SHUTDOWN;
584 regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
585
586 /* Restore cached register values to hardware */
587 return regcache_sync(data->regmap);
588 }
589
590 static const struct dev_pm_ops jc42_dev_pm_ops = {
591 .suspend = jc42_suspend,
592 .resume = jc42_resume,
593 };
594
595 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
596 #else
597 #define JC42_DEV_PM_OPS NULL
598 #endif /* CONFIG_PM */
599
600 static const struct i2c_device_id jc42_id[] = {
601 { "jc42", 0 },
602 { }
603 };
604 MODULE_DEVICE_TABLE(i2c, jc42_id);
605
606 #ifdef CONFIG_OF
607 static const struct of_device_id jc42_of_ids[] = {
608 { .compatible = "jedec,jc-42.4-temp", },
609 { }
610 };
611 MODULE_DEVICE_TABLE(of, jc42_of_ids);
612 #endif
613
614 static struct i2c_driver jc42_driver = {
615 .class = I2C_CLASS_SPD | I2C_CLASS_HWMON,
616 .driver = {
617 .name = "jc42",
618 .pm = JC42_DEV_PM_OPS,
619 .of_match_table = of_match_ptr(jc42_of_ids),
620 },
621 .probe_new = jc42_probe,
622 .remove = jc42_remove,
623 .id_table = jc42_id,
624 .detect = jc42_detect,
625 .address_list = normal_i2c,
626 };
627
628 module_i2c_driver(jc42_driver);
629
630 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
631 MODULE_DESCRIPTION("JC42 driver");
632 MODULE_LICENSE("GPL");
633