1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Xudong Chen <xudong.chen@mediatek.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/completion.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28
29 #define I2C_RS_TRANSFER (1 << 4)
30 #define I2C_ARB_LOST (1 << 3)
31 #define I2C_HS_NACKERR (1 << 2)
32 #define I2C_ACKERR (1 << 1)
33 #define I2C_TRANSAC_COMP (1 << 0)
34 #define I2C_TRANSAC_START (1 << 0)
35 #define I2C_RS_MUL_CNFG (1 << 15)
36 #define I2C_RS_MUL_TRIG (1 << 14)
37 #define I2C_DCM_DISABLE 0x0000
38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
40 #define I2C_SOFT_RST 0x0001
41 #define I2C_HANDSHAKE_RST 0x0020
42 #define I2C_FIFO_ADDR_CLR 0x0001
43 #define I2C_DELAY_LEN 0x0002
44 #define I2C_ST_START_CON 0x8001
45 #define I2C_FS_START_CON 0x1800
46 #define I2C_TIME_CLR_VALUE 0x0000
47 #define I2C_TIME_DEFAULT_VALUE 0x0003
48 #define I2C_WRRD_TRANAC_VALUE 0x0002
49 #define I2C_RD_TRANAC_VALUE 0x0001
50 #define I2C_SCL_MIS_COMP_VALUE 0x0000
51 #define I2C_CHN_CLR_FLAG 0x0000
52
53 #define I2C_DMA_CON_TX 0x0000
54 #define I2C_DMA_CON_RX 0x0001
55 #define I2C_DMA_ASYNC_MODE 0x0004
56 #define I2C_DMA_SKIP_CONFIG 0x0010
57 #define I2C_DMA_DIR_CHANGE 0x0200
58 #define I2C_DMA_START_EN 0x0001
59 #define I2C_DMA_INT_FLAG_NONE 0x0000
60 #define I2C_DMA_CLR_FLAG 0x0000
61 #define I2C_DMA_WARM_RST 0x0001
62 #define I2C_DMA_HARD_RST 0x0002
63 #define I2C_DMA_HANDSHAKE_RST 0x0004
64
65 #define MAX_SAMPLE_CNT_DIV 8
66 #define MAX_STEP_CNT_DIV 64
67 #define MAX_CLOCK_DIV 256
68 #define MAX_HS_STEP_CNT_DIV 8
69 #define I2C_STANDARD_MODE_BUFFER (1000 / 2)
70 #define I2C_FAST_MODE_BUFFER (300 / 2)
71 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2)
72
73 #define I2C_CONTROL_RS (0x1 << 1)
74 #define I2C_CONTROL_DMA_EN (0x1 << 2)
75 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
76 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
77 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
78 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
79 #define I2C_CONTROL_DMAACK_EN (0x1 << 8)
80 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
81 #define I2C_CONTROL_WRAPPER (0x1 << 0)
82
83 #define I2C_DRV_NAME "i2c-mt65xx"
84
85 enum DMA_REGS_OFFSET {
86 OFFSET_INT_FLAG = 0x0,
87 OFFSET_INT_EN = 0x04,
88 OFFSET_EN = 0x08,
89 OFFSET_RST = 0x0c,
90 OFFSET_CON = 0x18,
91 OFFSET_TX_MEM_ADDR = 0x1c,
92 OFFSET_RX_MEM_ADDR = 0x20,
93 OFFSET_TX_LEN = 0x24,
94 OFFSET_RX_LEN = 0x28,
95 OFFSET_TX_4G_MODE = 0x54,
96 OFFSET_RX_4G_MODE = 0x58,
97 };
98
99 enum i2c_trans_st_rs {
100 I2C_TRANS_STOP = 0,
101 I2C_TRANS_REPEATED_START,
102 };
103
104 enum mtk_trans_op {
105 I2C_MASTER_WR = 1,
106 I2C_MASTER_RD,
107 I2C_MASTER_WRRD,
108 };
109
110 enum I2C_REGS_OFFSET {
111 OFFSET_DATA_PORT,
112 OFFSET_SLAVE_ADDR,
113 OFFSET_INTR_MASK,
114 OFFSET_INTR_STAT,
115 OFFSET_CONTROL,
116 OFFSET_TRANSFER_LEN,
117 OFFSET_TRANSAC_LEN,
118 OFFSET_DELAY_LEN,
119 OFFSET_TIMING,
120 OFFSET_START,
121 OFFSET_EXT_CONF,
122 OFFSET_FIFO_STAT,
123 OFFSET_FIFO_THRESH,
124 OFFSET_FIFO_ADDR_CLR,
125 OFFSET_IO_CONFIG,
126 OFFSET_RSV_DEBUG,
127 OFFSET_HS,
128 OFFSET_SOFTRESET,
129 OFFSET_DCM_EN,
130 OFFSET_PATH_DIR,
131 OFFSET_DEBUGSTAT,
132 OFFSET_DEBUGCTRL,
133 OFFSET_TRANSFER_LEN_AUX,
134 OFFSET_CLOCK_DIV,
135 OFFSET_LTIMING,
136 OFFSET_SCL_HIGH_LOW_RATIO,
137 OFFSET_HS_SCL_HIGH_LOW_RATIO,
138 OFFSET_SCL_MIS_COMP_POINT,
139 OFFSET_STA_STO_AC_TIMING,
140 OFFSET_HS_STA_STO_AC_TIMING,
141 OFFSET_SDA_TIMING,
142 };
143
144 static const u16 mt_i2c_regs_v1[] = {
145 [OFFSET_DATA_PORT] = 0x0,
146 [OFFSET_SLAVE_ADDR] = 0x4,
147 [OFFSET_INTR_MASK] = 0x8,
148 [OFFSET_INTR_STAT] = 0xc,
149 [OFFSET_CONTROL] = 0x10,
150 [OFFSET_TRANSFER_LEN] = 0x14,
151 [OFFSET_TRANSAC_LEN] = 0x18,
152 [OFFSET_DELAY_LEN] = 0x1c,
153 [OFFSET_TIMING] = 0x20,
154 [OFFSET_START] = 0x24,
155 [OFFSET_EXT_CONF] = 0x28,
156 [OFFSET_FIFO_STAT] = 0x30,
157 [OFFSET_FIFO_THRESH] = 0x34,
158 [OFFSET_FIFO_ADDR_CLR] = 0x38,
159 [OFFSET_IO_CONFIG] = 0x40,
160 [OFFSET_RSV_DEBUG] = 0x44,
161 [OFFSET_HS] = 0x48,
162 [OFFSET_SOFTRESET] = 0x50,
163 [OFFSET_DCM_EN] = 0x54,
164 [OFFSET_PATH_DIR] = 0x60,
165 [OFFSET_DEBUGSTAT] = 0x64,
166 [OFFSET_DEBUGCTRL] = 0x68,
167 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
168 [OFFSET_CLOCK_DIV] = 0x70,
169 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
170 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
171 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
172 [OFFSET_STA_STO_AC_TIMING] = 0x80,
173 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
174 [OFFSET_SDA_TIMING] = 0x88,
175 };
176
177 static const u16 mt_i2c_regs_v2[] = {
178 [OFFSET_DATA_PORT] = 0x0,
179 [OFFSET_SLAVE_ADDR] = 0x4,
180 [OFFSET_INTR_MASK] = 0x8,
181 [OFFSET_INTR_STAT] = 0xc,
182 [OFFSET_CONTROL] = 0x10,
183 [OFFSET_TRANSFER_LEN] = 0x14,
184 [OFFSET_TRANSAC_LEN] = 0x18,
185 [OFFSET_DELAY_LEN] = 0x1c,
186 [OFFSET_TIMING] = 0x20,
187 [OFFSET_START] = 0x24,
188 [OFFSET_EXT_CONF] = 0x28,
189 [OFFSET_LTIMING] = 0x2c,
190 [OFFSET_HS] = 0x30,
191 [OFFSET_IO_CONFIG] = 0x34,
192 [OFFSET_FIFO_ADDR_CLR] = 0x38,
193 [OFFSET_SDA_TIMING] = 0x3c,
194 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
195 [OFFSET_CLOCK_DIV] = 0x48,
196 [OFFSET_SOFTRESET] = 0x50,
197 [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
198 [OFFSET_DEBUGSTAT] = 0xe4,
199 [OFFSET_DEBUGCTRL] = 0xe8,
200 [OFFSET_FIFO_STAT] = 0xf4,
201 [OFFSET_FIFO_THRESH] = 0xf8,
202 [OFFSET_DCM_EN] = 0xf88,
203 };
204
205 struct mtk_i2c_compatible {
206 const struct i2c_adapter_quirks *quirks;
207 const u16 *regs;
208 unsigned char pmic_i2c: 1;
209 unsigned char dcm: 1;
210 unsigned char auto_restart: 1;
211 unsigned char aux_len_reg: 1;
212 unsigned char timing_adjust: 1;
213 unsigned char dma_sync: 1;
214 unsigned char ltiming_adjust: 1;
215 unsigned char apdma_sync: 1;
216 unsigned char max_dma_support;
217 };
218
219 struct mtk_i2c_ac_timing {
220 u16 htiming;
221 u16 ltiming;
222 u16 hs;
223 u16 ext;
224 u16 inter_clk_div;
225 u16 scl_hl_ratio;
226 u16 hs_scl_hl_ratio;
227 u16 sta_stop;
228 u16 hs_sta_stop;
229 u16 sda_timing;
230 };
231
232 struct mtk_i2c {
233 struct i2c_adapter adap; /* i2c host adapter */
234 struct device *dev;
235 struct completion msg_complete;
236
237 /* set in i2c probe */
238 void __iomem *base; /* i2c base addr */
239 void __iomem *pdmabase; /* dma base address*/
240 struct clk *clk_main; /* main clock for i2c bus */
241 struct clk *clk_dma; /* DMA clock for i2c via DMA */
242 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
243 struct clk *clk_arb; /* Arbitrator clock for i2c */
244 bool have_pmic; /* can use i2c pins from PMIC */
245 bool use_push_pull; /* IO config push-pull mode */
246
247 u16 irq_stat; /* interrupt status */
248 unsigned int clk_src_div;
249 unsigned int speed_hz; /* The speed in transfer */
250 enum mtk_trans_op op;
251 u16 timing_reg;
252 u16 high_speed_reg;
253 u16 ltiming_reg;
254 unsigned char auto_restart;
255 bool ignore_restart_irq;
256 struct mtk_i2c_ac_timing ac_timing;
257 const struct mtk_i2c_compatible *dev_comp;
258 };
259
260 /**
261 * struct i2c_spec_values:
262 * @min_low_ns: min LOW period of the SCL clock
263 * @min_su_sta_ns: min set-up time for a repeated START condition
264 * @max_hd_dat_ns: max data hold time
265 * @min_su_dat_ns: min data set-up time
266 */
267 struct i2c_spec_values {
268 unsigned int min_low_ns;
269 unsigned int min_su_sta_ns;
270 unsigned int max_hd_dat_ns;
271 unsigned int min_su_dat_ns;
272 };
273
274 static const struct i2c_spec_values standard_mode_spec = {
275 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
276 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
277 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
278 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
279 };
280
281 static const struct i2c_spec_values fast_mode_spec = {
282 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
283 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
284 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
285 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
286 };
287
288 static const struct i2c_spec_values fast_mode_plus_spec = {
289 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
290 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
291 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
292 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
293 };
294
295 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
296 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
297 .max_num_msgs = 1,
298 .max_write_len = 255,
299 .max_read_len = 255,
300 .max_comb_1st_msg_len = 255,
301 .max_comb_2nd_msg_len = 31,
302 };
303
304 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
305 .max_num_msgs = 255,
306 };
307
308 static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
309 .flags = I2C_AQ_NO_ZERO_LEN,
310 };
311
312 static const struct mtk_i2c_compatible mt2712_compat = {
313 .regs = mt_i2c_regs_v1,
314 .pmic_i2c = 0,
315 .dcm = 1,
316 .auto_restart = 1,
317 .aux_len_reg = 1,
318 .timing_adjust = 1,
319 .dma_sync = 0,
320 .ltiming_adjust = 0,
321 .apdma_sync = 0,
322 .max_dma_support = 33,
323 };
324
325 static const struct mtk_i2c_compatible mt6577_compat = {
326 .quirks = &mt6577_i2c_quirks,
327 .regs = mt_i2c_regs_v1,
328 .pmic_i2c = 0,
329 .dcm = 1,
330 .auto_restart = 0,
331 .aux_len_reg = 0,
332 .timing_adjust = 0,
333 .dma_sync = 0,
334 .ltiming_adjust = 0,
335 .apdma_sync = 0,
336 .max_dma_support = 32,
337 };
338
339 static const struct mtk_i2c_compatible mt6589_compat = {
340 .quirks = &mt6577_i2c_quirks,
341 .regs = mt_i2c_regs_v1,
342 .pmic_i2c = 1,
343 .dcm = 0,
344 .auto_restart = 0,
345 .aux_len_reg = 0,
346 .timing_adjust = 0,
347 .dma_sync = 0,
348 .ltiming_adjust = 0,
349 .apdma_sync = 0,
350 .max_dma_support = 32,
351 };
352
353 static const struct mtk_i2c_compatible mt7622_compat = {
354 .quirks = &mt7622_i2c_quirks,
355 .regs = mt_i2c_regs_v1,
356 .pmic_i2c = 0,
357 .dcm = 1,
358 .auto_restart = 1,
359 .aux_len_reg = 1,
360 .timing_adjust = 0,
361 .dma_sync = 0,
362 .ltiming_adjust = 0,
363 .apdma_sync = 0,
364 .max_dma_support = 32,
365 };
366
367 static const struct mtk_i2c_compatible mt8173_compat = {
368 .regs = mt_i2c_regs_v1,
369 .pmic_i2c = 0,
370 .dcm = 1,
371 .auto_restart = 1,
372 .aux_len_reg = 1,
373 .timing_adjust = 0,
374 .dma_sync = 0,
375 .ltiming_adjust = 0,
376 .apdma_sync = 0,
377 .max_dma_support = 33,
378 };
379
380 static const struct mtk_i2c_compatible mt8183_compat = {
381 .quirks = &mt8183_i2c_quirks,
382 .regs = mt_i2c_regs_v2,
383 .pmic_i2c = 0,
384 .dcm = 0,
385 .auto_restart = 1,
386 .aux_len_reg = 1,
387 .timing_adjust = 1,
388 .dma_sync = 1,
389 .ltiming_adjust = 1,
390 .apdma_sync = 0,
391 .max_dma_support = 33,
392 };
393
394 static const struct mtk_i2c_compatible mt8192_compat = {
395 .quirks = &mt8183_i2c_quirks,
396 .regs = mt_i2c_regs_v2,
397 .pmic_i2c = 0,
398 .dcm = 0,
399 .auto_restart = 1,
400 .aux_len_reg = 1,
401 .timing_adjust = 1,
402 .dma_sync = 1,
403 .ltiming_adjust = 1,
404 .apdma_sync = 1,
405 .max_dma_support = 36,
406 };
407
408 static const struct of_device_id mtk_i2c_of_match[] = {
409 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
410 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
411 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
412 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
413 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
414 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
415 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
416 {}
417 };
418 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
419
mtk_i2c_readw(struct mtk_i2c * i2c,enum I2C_REGS_OFFSET reg)420 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
421 {
422 return readw(i2c->base + i2c->dev_comp->regs[reg]);
423 }
424
mtk_i2c_writew(struct mtk_i2c * i2c,u16 val,enum I2C_REGS_OFFSET reg)425 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
426 enum I2C_REGS_OFFSET reg)
427 {
428 writew(val, i2c->base + i2c->dev_comp->regs[reg]);
429 }
430
mtk_i2c_clock_enable(struct mtk_i2c * i2c)431 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
432 {
433 int ret;
434
435 ret = clk_prepare_enable(i2c->clk_dma);
436 if (ret)
437 return ret;
438
439 ret = clk_prepare_enable(i2c->clk_main);
440 if (ret)
441 goto err_main;
442
443 if (i2c->have_pmic) {
444 ret = clk_prepare_enable(i2c->clk_pmic);
445 if (ret)
446 goto err_pmic;
447 }
448
449 if (i2c->clk_arb) {
450 ret = clk_prepare_enable(i2c->clk_arb);
451 if (ret)
452 goto err_arb;
453 }
454
455 return 0;
456
457 err_arb:
458 if (i2c->have_pmic)
459 clk_disable_unprepare(i2c->clk_pmic);
460 err_pmic:
461 clk_disable_unprepare(i2c->clk_main);
462 err_main:
463 clk_disable_unprepare(i2c->clk_dma);
464
465 return ret;
466 }
467
mtk_i2c_clock_disable(struct mtk_i2c * i2c)468 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
469 {
470 if (i2c->clk_arb)
471 clk_disable_unprepare(i2c->clk_arb);
472
473 if (i2c->have_pmic)
474 clk_disable_unprepare(i2c->clk_pmic);
475
476 clk_disable_unprepare(i2c->clk_main);
477 clk_disable_unprepare(i2c->clk_dma);
478 }
479
mtk_i2c_init_hw(struct mtk_i2c * i2c)480 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
481 {
482 u16 control_reg;
483 u16 intr_stat_reg;
484 u16 ext_conf_val;
485
486 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
487 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
488 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
489
490 if (i2c->dev_comp->apdma_sync) {
491 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
492 udelay(10);
493 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
494 udelay(10);
495 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
496 i2c->pdmabase + OFFSET_RST);
497 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
498 OFFSET_SOFTRESET);
499 udelay(10);
500 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
501 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
502 } else {
503 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
504 udelay(50);
505 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
506 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
507 }
508
509 /* Set ioconfig */
510 if (i2c->use_push_pull)
511 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
512 else
513 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
514
515 if (i2c->dev_comp->dcm)
516 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
517
518 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
519 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
520 if (i2c->dev_comp->ltiming_adjust)
521 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
522
523 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
524 ext_conf_val = I2C_ST_START_CON;
525 else
526 ext_conf_val = I2C_FS_START_CON;
527
528 if (i2c->dev_comp->timing_adjust) {
529 ext_conf_val = i2c->ac_timing.ext;
530 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
531 OFFSET_CLOCK_DIV);
532 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
533 OFFSET_SCL_MIS_COMP_POINT);
534 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
535 OFFSET_SDA_TIMING);
536
537 if (i2c->dev_comp->ltiming_adjust) {
538 mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
539 OFFSET_TIMING);
540 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
541 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
542 OFFSET_LTIMING);
543 } else {
544 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
545 OFFSET_SCL_HIGH_LOW_RATIO);
546 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
547 OFFSET_HS_SCL_HIGH_LOW_RATIO);
548 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
549 OFFSET_STA_STO_AC_TIMING);
550 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
551 OFFSET_HS_STA_STO_AC_TIMING);
552 }
553 }
554 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
555
556 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
557 if (i2c->have_pmic)
558 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
559
560 control_reg = I2C_CONTROL_ACKERR_DET_EN |
561 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
562 if (i2c->dev_comp->dma_sync)
563 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
564
565 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
566 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
567 }
568
mtk_i2c_get_spec(unsigned int speed)569 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
570 {
571 if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
572 return &standard_mode_spec;
573 else if (speed <= I2C_MAX_FAST_MODE_FREQ)
574 return &fast_mode_spec;
575 else
576 return &fast_mode_plus_spec;
577 }
578
mtk_i2c_max_step_cnt(unsigned int target_speed)579 static int mtk_i2c_max_step_cnt(unsigned int target_speed)
580 {
581 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
582 return MAX_HS_STEP_CNT_DIV;
583 else
584 return MAX_STEP_CNT_DIV;
585 }
586
587 /*
588 * Check and Calculate i2c ac-timing
589 *
590 * Hardware design:
591 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
592 * xxx_cnt_div = spec->min_xxx_ns / sample_ns
593 *
594 * Sample_ns is rounded down for xxx_cnt_div would be greater
595 * than the smallest spec.
596 * The sda_timing is chosen as the middle value between
597 * the largest and smallest.
598 */
mtk_i2c_check_ac_timing(struct mtk_i2c * i2c,unsigned int clk_src,unsigned int check_speed,unsigned int step_cnt,unsigned int sample_cnt)599 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
600 unsigned int clk_src,
601 unsigned int check_speed,
602 unsigned int step_cnt,
603 unsigned int sample_cnt)
604 {
605 const struct i2c_spec_values *spec;
606 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
607 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
608 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
609 clk_src);
610
611 if (!i2c->dev_comp->timing_adjust)
612 return 0;
613
614 if (i2c->dev_comp->ltiming_adjust)
615 max_sta_cnt = 0x100;
616
617 spec = mtk_i2c_get_spec(check_speed);
618
619 if (i2c->dev_comp->ltiming_adjust)
620 clk_ns = 1000000000 / clk_src;
621 else
622 clk_ns = sample_ns / 2;
623
624 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
625 if (su_sta_cnt > max_sta_cnt)
626 return -1;
627
628 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
629 max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
630 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
631 if (low_cnt > step_cnt) {
632 high_cnt = 2 * step_cnt - low_cnt;
633 } else {
634 high_cnt = step_cnt;
635 low_cnt = step_cnt;
636 }
637 } else {
638 return -2;
639 }
640
641 sda_max = spec->max_hd_dat_ns / sample_ns;
642 if (sda_max > low_cnt)
643 sda_max = 0;
644
645 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
646 if (sda_min < low_cnt)
647 sda_min = 0;
648
649 if (sda_min > sda_max)
650 return -3;
651
652 if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
653 if (i2c->dev_comp->ltiming_adjust) {
654 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
655 (sample_cnt << 12) | (high_cnt << 8);
656 i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
657 i2c->ac_timing.ltiming |= (sample_cnt << 12) |
658 (low_cnt << 9);
659 i2c->ac_timing.ext &= ~GENMASK(7, 1);
660 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
661 } else {
662 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
663 (high_cnt << 6) | low_cnt;
664 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
665 su_sta_cnt;
666 }
667 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
668 i2c->ac_timing.sda_timing |= (1 << 12) |
669 ((sda_max + sda_min) / 2) << 6;
670 } else {
671 if (i2c->dev_comp->ltiming_adjust) {
672 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
673 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
674 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
675 } else {
676 i2c->ac_timing.scl_hl_ratio = (1 << 12) |
677 (high_cnt << 6) | low_cnt;
678 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
679 su_sta_cnt;
680 }
681
682 i2c->ac_timing.sda_timing = (1 << 12) |
683 (sda_max + sda_min) / 2;
684 }
685
686 return 0;
687 }
688
689 /*
690 * Calculate i2c port speed
691 *
692 * Hardware design:
693 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
694 * clock_div: fixed in hardware, but may be various in different SoCs
695 *
696 * The calculation want to pick the highest bus frequency that is still
697 * less than or equal to i2c->speed_hz. The calculation try to get
698 * sample_cnt and step_cn
699 */
mtk_i2c_calculate_speed(struct mtk_i2c * i2c,unsigned int clk_src,unsigned int target_speed,unsigned int * timing_step_cnt,unsigned int * timing_sample_cnt)700 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
701 unsigned int target_speed,
702 unsigned int *timing_step_cnt,
703 unsigned int *timing_sample_cnt)
704 {
705 unsigned int step_cnt;
706 unsigned int sample_cnt;
707 unsigned int max_step_cnt;
708 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
709 unsigned int base_step_cnt;
710 unsigned int opt_div;
711 unsigned int best_mul;
712 unsigned int cnt_mul;
713 int ret = -EINVAL;
714
715 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
716 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
717
718 max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
719 base_step_cnt = max_step_cnt;
720 /* Find the best combination */
721 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
722 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
723
724 /* Search for the best pair (sample_cnt, step_cnt) with
725 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
726 * 0 < step_cnt < max_step_cnt
727 * sample_cnt * step_cnt >= opt_div
728 * optimizing for sample_cnt * step_cnt being minimal
729 */
730 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
731 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
732 cnt_mul = step_cnt * sample_cnt;
733 if (step_cnt > max_step_cnt)
734 continue;
735
736 if (cnt_mul < best_mul) {
737 ret = mtk_i2c_check_ac_timing(i2c, clk_src,
738 target_speed, step_cnt - 1, sample_cnt - 1);
739 if (ret)
740 continue;
741
742 best_mul = cnt_mul;
743 base_sample_cnt = sample_cnt;
744 base_step_cnt = step_cnt;
745 if (best_mul == opt_div)
746 break;
747 }
748 }
749
750 if (ret)
751 return -EINVAL;
752
753 sample_cnt = base_sample_cnt;
754 step_cnt = base_step_cnt;
755
756 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
757 /* In this case, hardware can't support such
758 * low i2c_bus_freq
759 */
760 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
761 return -EINVAL;
762 }
763
764 *timing_step_cnt = step_cnt - 1;
765 *timing_sample_cnt = sample_cnt - 1;
766
767 return 0;
768 }
769
mtk_i2c_set_speed(struct mtk_i2c * i2c,unsigned int parent_clk)770 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
771 {
772 unsigned int clk_src;
773 unsigned int step_cnt;
774 unsigned int sample_cnt;
775 unsigned int l_step_cnt;
776 unsigned int l_sample_cnt;
777 unsigned int target_speed;
778 unsigned int clk_div;
779 unsigned int max_clk_div;
780 int ret;
781
782 target_speed = i2c->speed_hz;
783 parent_clk /= i2c->clk_src_div;
784
785 if (i2c->dev_comp->timing_adjust)
786 max_clk_div = MAX_CLOCK_DIV;
787 else
788 max_clk_div = 1;
789
790 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
791 clk_src = parent_clk / clk_div;
792
793 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
794 /* Set master code speed register */
795 ret = mtk_i2c_calculate_speed(i2c, clk_src,
796 I2C_MAX_FAST_MODE_FREQ,
797 &l_step_cnt,
798 &l_sample_cnt);
799 if (ret < 0)
800 continue;
801
802 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
803
804 /* Set the high speed mode register */
805 ret = mtk_i2c_calculate_speed(i2c, clk_src,
806 target_speed, &step_cnt,
807 &sample_cnt);
808 if (ret < 0)
809 continue;
810
811 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
812 (sample_cnt << 12) | (step_cnt << 8);
813
814 if (i2c->dev_comp->ltiming_adjust)
815 i2c->ltiming_reg =
816 (l_sample_cnt << 6) | l_step_cnt |
817 (sample_cnt << 12) | (step_cnt << 9);
818 } else {
819 ret = mtk_i2c_calculate_speed(i2c, clk_src,
820 target_speed, &l_step_cnt,
821 &l_sample_cnt);
822 if (ret < 0)
823 continue;
824
825 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
826
827 /* Disable the high speed transaction */
828 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
829
830 if (i2c->dev_comp->ltiming_adjust)
831 i2c->ltiming_reg =
832 (l_sample_cnt << 6) | l_step_cnt;
833 }
834
835 break;
836 }
837
838 i2c->ac_timing.inter_clk_div = clk_div - 1;
839
840 return 0;
841 }
842
mtk_i2c_do_transfer(struct mtk_i2c * i2c,struct i2c_msg * msgs,int num,int left_num)843 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
844 int num, int left_num)
845 {
846 u16 addr_reg;
847 u16 start_reg;
848 u16 control_reg;
849 u16 restart_flag = 0;
850 u16 dma_sync = 0;
851 u32 reg_4g_mode;
852 u8 *dma_rd_buf = NULL;
853 u8 *dma_wr_buf = NULL;
854 dma_addr_t rpaddr = 0;
855 dma_addr_t wpaddr = 0;
856 int ret;
857
858 i2c->irq_stat = 0;
859
860 if (i2c->auto_restart)
861 restart_flag = I2C_RS_TRANSFER;
862
863 reinit_completion(&i2c->msg_complete);
864
865 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
866 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
867 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
868 control_reg |= I2C_CONTROL_RS;
869
870 if (i2c->op == I2C_MASTER_WRRD)
871 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
872
873 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
874
875 addr_reg = i2c_8bit_addr_from_msg(msgs);
876 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
877
878 /* Clear interrupt status */
879 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
880 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
881
882 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
883
884 /* Enable interrupt */
885 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
886 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
887
888 /* Set transfer and transaction len */
889 if (i2c->op == I2C_MASTER_WRRD) {
890 if (i2c->dev_comp->aux_len_reg) {
891 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
892 mtk_i2c_writew(i2c, (msgs + 1)->len,
893 OFFSET_TRANSFER_LEN_AUX);
894 } else {
895 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
896 OFFSET_TRANSFER_LEN);
897 }
898 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
899 } else {
900 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
901 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
902 }
903
904 if (i2c->dev_comp->apdma_sync) {
905 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
906 if (i2c->op == I2C_MASTER_WRRD)
907 dma_sync |= I2C_DMA_DIR_CHANGE;
908 }
909
910 /* Prepare buffer data to start transfer */
911 if (i2c->op == I2C_MASTER_RD) {
912 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
913 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
914
915 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
916 if (!dma_rd_buf)
917 return -ENOMEM;
918
919 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
920 msgs->len, DMA_FROM_DEVICE);
921 if (dma_mapping_error(i2c->dev, rpaddr)) {
922 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
923
924 return -ENOMEM;
925 }
926
927 if (i2c->dev_comp->max_dma_support > 32) {
928 reg_4g_mode = upper_32_bits(rpaddr);
929 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
930 }
931
932 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
933 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
934 } else if (i2c->op == I2C_MASTER_WR) {
935 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
936 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
937
938 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
939 if (!dma_wr_buf)
940 return -ENOMEM;
941
942 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
943 msgs->len, DMA_TO_DEVICE);
944 if (dma_mapping_error(i2c->dev, wpaddr)) {
945 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
946
947 return -ENOMEM;
948 }
949
950 if (i2c->dev_comp->max_dma_support > 32) {
951 reg_4g_mode = upper_32_bits(wpaddr);
952 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
953 }
954
955 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
956 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
957 } else {
958 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
959 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
960
961 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
962 if (!dma_wr_buf)
963 return -ENOMEM;
964
965 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
966 msgs->len, DMA_TO_DEVICE);
967 if (dma_mapping_error(i2c->dev, wpaddr)) {
968 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
969
970 return -ENOMEM;
971 }
972
973 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
974 if (!dma_rd_buf) {
975 dma_unmap_single(i2c->dev, wpaddr,
976 msgs->len, DMA_TO_DEVICE);
977
978 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
979
980 return -ENOMEM;
981 }
982
983 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
984 (msgs + 1)->len,
985 DMA_FROM_DEVICE);
986 if (dma_mapping_error(i2c->dev, rpaddr)) {
987 dma_unmap_single(i2c->dev, wpaddr,
988 msgs->len, DMA_TO_DEVICE);
989
990 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
991 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
992
993 return -ENOMEM;
994 }
995
996 if (i2c->dev_comp->max_dma_support > 32) {
997 reg_4g_mode = upper_32_bits(wpaddr);
998 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
999
1000 reg_4g_mode = upper_32_bits(rpaddr);
1001 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1002 }
1003
1004 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1005 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1006 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1007 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
1008 }
1009
1010 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
1011
1012 if (!i2c->auto_restart) {
1013 start_reg = I2C_TRANSAC_START;
1014 } else {
1015 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
1016 if (left_num >= 1)
1017 start_reg |= I2C_RS_MUL_CNFG;
1018 }
1019 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
1020
1021 ret = wait_for_completion_timeout(&i2c->msg_complete,
1022 i2c->adap.timeout);
1023
1024 /* Clear interrupt mask */
1025 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1026 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
1027
1028 if (i2c->op == I2C_MASTER_WR) {
1029 dma_unmap_single(i2c->dev, wpaddr,
1030 msgs->len, DMA_TO_DEVICE);
1031
1032 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1033 } else if (i2c->op == I2C_MASTER_RD) {
1034 dma_unmap_single(i2c->dev, rpaddr,
1035 msgs->len, DMA_FROM_DEVICE);
1036
1037 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
1038 } else {
1039 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1040 DMA_TO_DEVICE);
1041 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1042 DMA_FROM_DEVICE);
1043
1044 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1045 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
1046 }
1047
1048 if (ret == 0) {
1049 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1050 mtk_i2c_init_hw(i2c);
1051 return -ETIMEDOUT;
1052 }
1053
1054 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
1055 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1056 mtk_i2c_init_hw(i2c);
1057 return -ENXIO;
1058 }
1059
1060 return 0;
1061 }
1062
mtk_i2c_transfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1063 static int mtk_i2c_transfer(struct i2c_adapter *adap,
1064 struct i2c_msg msgs[], int num)
1065 {
1066 int ret;
1067 int left_num = num;
1068 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1069
1070 ret = mtk_i2c_clock_enable(i2c);
1071 if (ret)
1072 return ret;
1073
1074 i2c->auto_restart = i2c->dev_comp->auto_restart;
1075
1076 /* checking if we can skip restart and optimize using WRRD mode */
1077 if (i2c->auto_restart && num == 2) {
1078 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
1079 msgs[0].addr == msgs[1].addr) {
1080 i2c->auto_restart = 0;
1081 }
1082 }
1083
1084 if (i2c->auto_restart && num >= 2 &&
1085 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1086 /* ignore the first restart irq after the master code,
1087 * otherwise the first transfer will be discarded.
1088 */
1089 i2c->ignore_restart_irq = true;
1090 else
1091 i2c->ignore_restart_irq = false;
1092
1093 while (left_num--) {
1094 if (!msgs->buf) {
1095 dev_dbg(i2c->dev, "data buffer is NULL.\n");
1096 ret = -EINVAL;
1097 goto err_exit;
1098 }
1099
1100 if (msgs->flags & I2C_M_RD)
1101 i2c->op = I2C_MASTER_RD;
1102 else
1103 i2c->op = I2C_MASTER_WR;
1104
1105 if (!i2c->auto_restart) {
1106 if (num > 1) {
1107 /* combined two messages into one transaction */
1108 i2c->op = I2C_MASTER_WRRD;
1109 left_num--;
1110 }
1111 }
1112
1113 /* always use DMA mode. */
1114 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
1115 if (ret < 0)
1116 goto err_exit;
1117
1118 msgs++;
1119 }
1120 /* the return value is number of executed messages */
1121 ret = num;
1122
1123 err_exit:
1124 mtk_i2c_clock_disable(i2c);
1125 return ret;
1126 }
1127
mtk_i2c_irq(int irqno,void * dev_id)1128 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
1129 {
1130 struct mtk_i2c *i2c = dev_id;
1131 u16 restart_flag = 0;
1132 u16 intr_stat;
1133
1134 if (i2c->auto_restart)
1135 restart_flag = I2C_RS_TRANSFER;
1136
1137 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
1138 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
1139
1140 /*
1141 * when occurs ack error, i2c controller generate two interrupts
1142 * first is the ack error interrupt, then the complete interrupt
1143 * i2c->irq_stat need keep the two interrupt value.
1144 */
1145 i2c->irq_stat |= intr_stat;
1146
1147 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
1148 i2c->ignore_restart_irq = false;
1149 i2c->irq_stat = 0;
1150 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
1151 I2C_TRANSAC_START, OFFSET_START);
1152 } else {
1153 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
1154 complete(&i2c->msg_complete);
1155 }
1156
1157 return IRQ_HANDLED;
1158 }
1159
mtk_i2c_functionality(struct i2c_adapter * adap)1160 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
1161 {
1162 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
1163 return I2C_FUNC_I2C |
1164 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1165 else
1166 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1167 }
1168
1169 static const struct i2c_algorithm mtk_i2c_algorithm = {
1170 .master_xfer = mtk_i2c_transfer,
1171 .functionality = mtk_i2c_functionality,
1172 };
1173
mtk_i2c_parse_dt(struct device_node * np,struct mtk_i2c * i2c)1174 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
1175 {
1176 int ret;
1177
1178 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
1179 if (ret < 0)
1180 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
1181
1182 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
1183 if (ret < 0)
1184 return ret;
1185
1186 if (i2c->clk_src_div == 0)
1187 return -EINVAL;
1188
1189 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
1190 i2c->use_push_pull =
1191 of_property_read_bool(np, "mediatek,use-push-pull");
1192
1193 return 0;
1194 }
1195
mtk_i2c_probe(struct platform_device * pdev)1196 static int mtk_i2c_probe(struct platform_device *pdev)
1197 {
1198 int ret = 0;
1199 struct mtk_i2c *i2c;
1200 struct clk *clk;
1201 struct resource *res;
1202 int irq;
1203
1204 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1205 if (!i2c)
1206 return -ENOMEM;
1207
1208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1209 i2c->base = devm_ioremap_resource(&pdev->dev, res);
1210 if (IS_ERR(i2c->base))
1211 return PTR_ERR(i2c->base);
1212
1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1214 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
1215 if (IS_ERR(i2c->pdmabase))
1216 return PTR_ERR(i2c->pdmabase);
1217
1218 irq = platform_get_irq(pdev, 0);
1219 if (irq < 0)
1220 return irq;
1221
1222 init_completion(&i2c->msg_complete);
1223
1224 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1225 i2c->adap.dev.of_node = pdev->dev.of_node;
1226 i2c->dev = &pdev->dev;
1227 i2c->adap.dev.parent = &pdev->dev;
1228 i2c->adap.owner = THIS_MODULE;
1229 i2c->adap.algo = &mtk_i2c_algorithm;
1230 i2c->adap.quirks = i2c->dev_comp->quirks;
1231 i2c->adap.timeout = 2 * HZ;
1232 i2c->adap.retries = 1;
1233
1234 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1235 if (ret)
1236 return -EINVAL;
1237
1238 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1239 return -EINVAL;
1240
1241 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
1242 if (IS_ERR(i2c->clk_main)) {
1243 dev_err(&pdev->dev, "cannot get main clock\n");
1244 return PTR_ERR(i2c->clk_main);
1245 }
1246
1247 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
1248 if (IS_ERR(i2c->clk_dma)) {
1249 dev_err(&pdev->dev, "cannot get dma clock\n");
1250 return PTR_ERR(i2c->clk_dma);
1251 }
1252
1253 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
1254 if (IS_ERR(i2c->clk_arb))
1255 i2c->clk_arb = NULL;
1256
1257 clk = i2c->clk_main;
1258 if (i2c->have_pmic) {
1259 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
1260 if (IS_ERR(i2c->clk_pmic)) {
1261 dev_err(&pdev->dev, "cannot get pmic clock\n");
1262 return PTR_ERR(i2c->clk_pmic);
1263 }
1264 clk = i2c->clk_pmic;
1265 }
1266
1267 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1268
1269 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
1270 if (ret) {
1271 dev_err(&pdev->dev, "Failed to set the speed.\n");
1272 return -EINVAL;
1273 }
1274
1275 if (i2c->dev_comp->max_dma_support > 32) {
1276 ret = dma_set_mask(&pdev->dev,
1277 DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
1278 if (ret) {
1279 dev_err(&pdev->dev, "dma_set_mask return error.\n");
1280 return ret;
1281 }
1282 }
1283
1284 ret = mtk_i2c_clock_enable(i2c);
1285 if (ret) {
1286 dev_err(&pdev->dev, "clock enable failed!\n");
1287 return ret;
1288 }
1289 mtk_i2c_init_hw(i2c);
1290 mtk_i2c_clock_disable(i2c);
1291
1292 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1293 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
1294 I2C_DRV_NAME, i2c);
1295 if (ret < 0) {
1296 dev_err(&pdev->dev,
1297 "Request I2C IRQ %d fail\n", irq);
1298 return ret;
1299 }
1300
1301 i2c_set_adapdata(&i2c->adap, i2c);
1302 ret = i2c_add_adapter(&i2c->adap);
1303 if (ret)
1304 return ret;
1305
1306 platform_set_drvdata(pdev, i2c);
1307
1308 return 0;
1309 }
1310
mtk_i2c_remove(struct platform_device * pdev)1311 static int mtk_i2c_remove(struct platform_device *pdev)
1312 {
1313 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1314
1315 i2c_del_adapter(&i2c->adap);
1316
1317 return 0;
1318 }
1319
1320 #ifdef CONFIG_PM_SLEEP
mtk_i2c_suspend_noirq(struct device * dev)1321 static int mtk_i2c_suspend_noirq(struct device *dev)
1322 {
1323 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1324
1325 i2c_mark_adapter_suspended(&i2c->adap);
1326
1327 return 0;
1328 }
1329
mtk_i2c_resume_noirq(struct device * dev)1330 static int mtk_i2c_resume_noirq(struct device *dev)
1331 {
1332 int ret;
1333 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1334
1335 ret = mtk_i2c_clock_enable(i2c);
1336 if (ret) {
1337 dev_err(dev, "clock enable failed!\n");
1338 return ret;
1339 }
1340
1341 mtk_i2c_init_hw(i2c);
1342
1343 mtk_i2c_clock_disable(i2c);
1344
1345 i2c_mark_adapter_resumed(&i2c->adap);
1346
1347 return 0;
1348 }
1349 #endif
1350
1351 static const struct dev_pm_ops mtk_i2c_pm = {
1352 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
1353 mtk_i2c_resume_noirq)
1354 };
1355
1356 static struct platform_driver mtk_i2c_driver = {
1357 .probe = mtk_i2c_probe,
1358 .remove = mtk_i2c_remove,
1359 .driver = {
1360 .name = I2C_DRV_NAME,
1361 .pm = &mtk_i2c_pm,
1362 .of_match_table = of_match_ptr(mtk_i2c_of_match),
1363 },
1364 };
1365
1366 module_platform_driver(mtk_i2c_driver);
1367
1368 MODULE_LICENSE("GPL v2");
1369 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1370 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
1371