1 /*
2 * Synopsys DW APB ICTL irqchip driver.
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqchip.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/interrupt.h>
21
22 #define APB_INT_ENABLE_L 0x00
23 #define APB_INT_ENABLE_H 0x04
24 #define APB_INT_MASK_L 0x08
25 #define APB_INT_MASK_H 0x0c
26 #define APB_INT_FINALSTATUS_L 0x30
27 #define APB_INT_FINALSTATUS_H 0x34
28 #define APB_INT_BASE_OFFSET 0x04
29
30 /* irq domain of the primary interrupt controller. */
31 static struct irq_domain *dw_apb_ictl_irq_domain;
32
dw_apb_ictl_handle_irq(struct pt_regs * regs)33 static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs)
34 {
35 struct irq_domain *d = dw_apb_ictl_irq_domain;
36 int n;
37
38 for (n = 0; n < d->revmap_size; n += 32) {
39 struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
40 u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
41
42 while (stat) {
43 u32 hwirq = ffs(stat) - 1;
44
45 handle_domain_irq(d, hwirq, regs);
46 stat &= ~BIT(hwirq);
47 }
48 }
49 }
50
dw_apb_ictl_handle_irq_cascaded(struct irq_desc * desc)51 static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc)
52 {
53 struct irq_domain *d = irq_desc_get_handler_data(desc);
54 struct irq_chip *chip = irq_desc_get_chip(desc);
55 int n;
56
57 chained_irq_enter(chip, desc);
58
59 for (n = 0; n < d->revmap_size; n += 32) {
60 struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
61 u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
62
63 while (stat) {
64 u32 hwirq = ffs(stat) - 1;
65 u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);
66
67 generic_handle_irq(virq);
68 stat &= ~BIT(hwirq);
69 }
70 }
71
72 chained_irq_exit(chip, desc);
73 }
74
dw_apb_ictl_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)75 static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
76 unsigned int nr_irqs, void *arg)
77 {
78 int i, ret;
79 irq_hw_number_t hwirq;
80 unsigned int type = IRQ_TYPE_NONE;
81 struct irq_fwspec *fwspec = arg;
82
83 ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
84 if (ret)
85 return ret;
86
87 for (i = 0; i < nr_irqs; i++)
88 irq_map_generic_chip(domain, virq + i, hwirq + i);
89
90 return 0;
91 }
92
93 static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = {
94 .translate = irq_domain_translate_onecell,
95 .alloc = dw_apb_ictl_irq_domain_alloc,
96 .free = irq_domain_free_irqs_top,
97 };
98
99 #ifdef CONFIG_PM
dw_apb_ictl_resume(struct irq_data * d)100 static void dw_apb_ictl_resume(struct irq_data *d)
101 {
102 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
103 struct irq_chip_type *ct = irq_data_get_chip_type(d);
104
105 irq_gc_lock(gc);
106 writel_relaxed(~0, gc->reg_base + ct->regs.enable);
107 writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
108 irq_gc_unlock(gc);
109 }
110 #else
111 #define dw_apb_ictl_resume NULL
112 #endif /* CONFIG_PM */
113
dw_apb_ictl_init(struct device_node * np,struct device_node * parent)114 static int __init dw_apb_ictl_init(struct device_node *np,
115 struct device_node *parent)
116 {
117 const struct irq_domain_ops *domain_ops;
118 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
119 struct resource r;
120 struct irq_domain *domain;
121 struct irq_chip_generic *gc;
122 void __iomem *iobase;
123 int ret, nrirqs, parent_irq, i;
124 u32 reg;
125
126 if (!parent) {
127 /* Used as the primary interrupt controller */
128 parent_irq = 0;
129 domain_ops = &dw_apb_ictl_irq_domain_ops;
130 } else {
131 /* Map the parent interrupt for the chained handler */
132 parent_irq = irq_of_parse_and_map(np, 0);
133 if (parent_irq <= 0) {
134 pr_err("%pOF: unable to parse irq\n", np);
135 return -EINVAL;
136 }
137 domain_ops = &irq_generic_chip_ops;
138 }
139
140 ret = of_address_to_resource(np, 0, &r);
141 if (ret) {
142 pr_err("%pOF: unable to get resource\n", np);
143 return ret;
144 }
145
146 if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
147 pr_err("%pOF: unable to request mem region\n", np);
148 return -ENOMEM;
149 }
150
151 iobase = ioremap(r.start, resource_size(&r));
152 if (!iobase) {
153 pr_err("%pOF: unable to map resource\n", np);
154 ret = -ENOMEM;
155 goto err_release;
156 }
157
158 /*
159 * DW IP can be configured to allow 2-64 irqs. We can determine
160 * the number of irqs supported by writing into enable register
161 * and look for bits not set, as corresponding flip-flops will
162 * have been removed by synthesis tool.
163 */
164
165 /* mask and enable all interrupts */
166 writel_relaxed(~0, iobase + APB_INT_MASK_L);
167 writel_relaxed(~0, iobase + APB_INT_MASK_H);
168 writel_relaxed(~0, iobase + APB_INT_ENABLE_L);
169 writel_relaxed(~0, iobase + APB_INT_ENABLE_H);
170
171 reg = readl_relaxed(iobase + APB_INT_ENABLE_H);
172 if (reg)
173 nrirqs = 32 + fls(reg);
174 else
175 nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
176
177 domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL);
178 if (!domain) {
179 pr_err("%pOF: unable to add irq domain\n", np);
180 ret = -ENOMEM;
181 goto err_unmap;
182 }
183
184 ret = irq_alloc_domain_generic_chips(domain, 32, 1, np->name,
185 handle_level_irq, clr, 0,
186 IRQ_GC_INIT_MASK_CACHE);
187 if (ret) {
188 pr_err("%pOF: unable to alloc irq domain gc\n", np);
189 goto err_unmap;
190 }
191
192 for (i = 0; i < DIV_ROUND_UP(nrirqs, 32); i++) {
193 gc = irq_get_domain_generic_chip(domain, i * 32);
194 gc->reg_base = iobase + i * APB_INT_BASE_OFFSET;
195 gc->chip_types[0].regs.mask = APB_INT_MASK_L;
196 gc->chip_types[0].regs.enable = APB_INT_ENABLE_L;
197 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
198 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
199 gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
200 }
201
202 if (parent_irq) {
203 irq_set_chained_handler_and_data(parent_irq,
204 dw_apb_ictl_handle_irq_cascaded, domain);
205 } else {
206 dw_apb_ictl_irq_domain = domain;
207 set_handle_irq(dw_apb_ictl_handle_irq);
208 }
209
210 return 0;
211
212 err_unmap:
213 iounmap(iobase);
214 err_release:
215 release_mem_region(r.start, resource_size(&r));
216 return ret;
217 }
218 IRQCHIP_DECLARE(dw_apb_ictl,
219 "snps,dw-apb-ictl", dw_apb_ictl_init);
220