1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Jerome Brunet <jbrunet@baylibre.com>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/irqchip.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19
20 #define NUM_CHANNEL 8
21 #define MAX_INPUT_MUX 256
22
23 #define REG_EDGE_POL 0x00
24 #define REG_PIN_03_SEL 0x04
25 #define REG_PIN_47_SEL 0x08
26 #define REG_FILTER_SEL 0x0c
27
28 /* use for A1 like chips */
29 #define REG_PIN_A1_SEL 0x04
30
31 /*
32 * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
33 * bits 24 to 31. Tests on the actual HW show that these bits are
34 * stuck at 0. Bits 8 to 15 are responsive and have the expected
35 * effect.
36 */
37 #define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x))
38 #define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x))
39 #define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x))
40 #define REG_EDGE_POL_MASK(params, x) ( \
41 REG_EDGE_POL_EDGE(params, x) | \
42 REG_EDGE_POL_LOW(params, x) | \
43 REG_BOTH_EDGE(params, x))
44 #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
45 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
46
47 struct meson_gpio_irq_controller;
48 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
49 unsigned int channel, unsigned long hwirq);
50 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
51 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
52 unsigned int channel,
53 unsigned long hwirq);
54 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
55
56 struct irq_ctl_ops {
57 void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
58 unsigned int channel, unsigned long hwirq);
59 void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
60 };
61
62 struct meson_gpio_irq_params {
63 unsigned int nr_hwirq;
64 bool support_edge_both;
65 unsigned int edge_both_offset;
66 unsigned int edge_single_offset;
67 unsigned int pol_low_offset;
68 unsigned int pin_sel_mask;
69 struct irq_ctl_ops ops;
70 };
71
72 #define INIT_MESON_COMMON(irqs, init, sel) \
73 .nr_hwirq = irqs, \
74 .ops = { \
75 .gpio_irq_init = init, \
76 .gpio_irq_sel_pin = sel, \
77 },
78
79 #define INIT_MESON8_COMMON_DATA(irqs) \
80 INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \
81 meson8_gpio_irq_sel_pin) \
82 .edge_single_offset = 0, \
83 .pol_low_offset = 16, \
84 .pin_sel_mask = 0xff, \
85
86 #define INIT_MESON_A1_COMMON_DATA(irqs) \
87 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
88 meson_a1_gpio_irq_sel_pin) \
89 .support_edge_both = true, \
90 .edge_both_offset = 16, \
91 .edge_single_offset = 8, \
92 .pol_low_offset = 0, \
93 .pin_sel_mask = 0x7f, \
94
95 static const struct meson_gpio_irq_params meson8_params = {
96 INIT_MESON8_COMMON_DATA(134)
97 };
98
99 static const struct meson_gpio_irq_params meson8b_params = {
100 INIT_MESON8_COMMON_DATA(119)
101 };
102
103 static const struct meson_gpio_irq_params gxbb_params = {
104 INIT_MESON8_COMMON_DATA(133)
105 };
106
107 static const struct meson_gpio_irq_params gxl_params = {
108 INIT_MESON8_COMMON_DATA(110)
109 };
110
111 static const struct meson_gpio_irq_params axg_params = {
112 INIT_MESON8_COMMON_DATA(100)
113 };
114
115 static const struct meson_gpio_irq_params sm1_params = {
116 INIT_MESON8_COMMON_DATA(100)
117 .support_edge_both = true,
118 .edge_both_offset = 8,
119 };
120
121 static const struct meson_gpio_irq_params a1_params = {
122 INIT_MESON_A1_COMMON_DATA(62)
123 };
124
125 static const struct of_device_id meson_irq_gpio_matches[] = {
126 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
127 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
128 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
129 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
130 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
131 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
132 { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
133 { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
134 { }
135 };
136
137 struct meson_gpio_irq_controller {
138 const struct meson_gpio_irq_params *params;
139 void __iomem *base;
140 struct irq_domain *domain;
141 u32 channel_irqs[NUM_CHANNEL];
142 DECLARE_BITMAP(channel_map, NUM_CHANNEL);
143 spinlock_t lock;
144 };
145
meson_gpio_irq_update_bits(struct meson_gpio_irq_controller * ctl,unsigned int reg,u32 mask,u32 val)146 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
147 unsigned int reg, u32 mask, u32 val)
148 {
149 unsigned long flags;
150 u32 tmp;
151
152 spin_lock_irqsave(&ctl->lock, flags);
153
154 tmp = readl_relaxed(ctl->base + reg);
155 tmp &= ~mask;
156 tmp |= val;
157 writel_relaxed(tmp, ctl->base + reg);
158
159 spin_unlock_irqrestore(&ctl->lock, flags);
160 }
161
meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller * ctl)162 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
163 {
164 }
165
meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller * ctl,unsigned int channel,unsigned long hwirq)166 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
167 unsigned int channel, unsigned long hwirq)
168 {
169 unsigned int reg_offset;
170 unsigned int bit_offset;
171
172 reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
173 bit_offset = REG_PIN_SEL_SHIFT(channel);
174
175 meson_gpio_irq_update_bits(ctl, reg_offset,
176 ctl->params->pin_sel_mask << bit_offset,
177 hwirq << bit_offset);
178 }
179
meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller * ctl,unsigned int channel,unsigned long hwirq)180 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
181 unsigned int channel,
182 unsigned long hwirq)
183 {
184 unsigned int reg_offset;
185 unsigned int bit_offset;
186
187 bit_offset = ((channel % 2) == 0) ? 0 : 16;
188 reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);
189
190 meson_gpio_irq_update_bits(ctl, reg_offset,
191 ctl->params->pin_sel_mask << bit_offset,
192 hwirq << bit_offset);
193 }
194
195 /* For a1 or later chips like a1 there is a switch to enable/disable irq */
meson_a1_gpio_irq_init(struct meson_gpio_irq_controller * ctl)196 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
197 {
198 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
199 }
200
201 static int
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller * ctl,unsigned long hwirq,u32 ** channel_hwirq)202 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
203 unsigned long hwirq,
204 u32 **channel_hwirq)
205 {
206 unsigned long flags;
207 unsigned int idx;
208
209 spin_lock_irqsave(&ctl->lock, flags);
210
211 /* Find a free channel */
212 idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
213 if (idx >= NUM_CHANNEL) {
214 spin_unlock_irqrestore(&ctl->lock, flags);
215 pr_err("No channel available\n");
216 return -ENOSPC;
217 }
218
219 /* Mark the channel as used */
220 set_bit(idx, ctl->channel_map);
221
222 spin_unlock_irqrestore(&ctl->lock, flags);
223
224 /*
225 * Setup the mux of the channel to route the signal of the pad
226 * to the appropriate input of the GIC
227 */
228 ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
229
230 /*
231 * Get the hwirq number assigned to this channel through
232 * a pointer the channel_irq table. The added benefit of this
233 * method is that we can also retrieve the channel index with
234 * it, using the table base.
235 */
236 *channel_hwirq = &(ctl->channel_irqs[idx]);
237
238 pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
239 hwirq, idx, **channel_hwirq);
240
241 return 0;
242 }
243
244 static unsigned int
meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller * ctl,u32 * channel_hwirq)245 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
246 u32 *channel_hwirq)
247 {
248 return channel_hwirq - ctl->channel_irqs;
249 }
250
251 static void
meson_gpio_irq_release_channel(struct meson_gpio_irq_controller * ctl,u32 * channel_hwirq)252 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
253 u32 *channel_hwirq)
254 {
255 unsigned int idx;
256
257 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
258 clear_bit(idx, ctl->channel_map);
259 }
260
meson_gpio_irq_type_setup(struct meson_gpio_irq_controller * ctl,unsigned int type,u32 * channel_hwirq)261 static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
262 unsigned int type,
263 u32 *channel_hwirq)
264 {
265 u32 val = 0;
266 unsigned int idx;
267 const struct meson_gpio_irq_params *params;
268
269 params = ctl->params;
270 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
271
272 /*
273 * The controller has a filter block to operate in either LEVEL or
274 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
275 * EDGE_FALLING support (which the GIC does not support), the filter
276 * block is also able to invert the input signal it gets before
277 * providing it to the GIC.
278 */
279 type &= IRQ_TYPE_SENSE_MASK;
280
281 /*
282 * New controller support EDGE_BOTH trigger. This setting takes
283 * precedence over the other edge/polarity settings
284 */
285 if (type == IRQ_TYPE_EDGE_BOTH) {
286 if (!params->support_edge_both)
287 return -EINVAL;
288
289 val |= REG_BOTH_EDGE(params, idx);
290 } else {
291 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
292 val |= REG_EDGE_POL_EDGE(params, idx);
293
294 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
295 val |= REG_EDGE_POL_LOW(params, idx);
296 }
297
298 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
299 REG_EDGE_POL_MASK(params, idx), val);
300
301 return 0;
302 }
303
meson_gpio_irq_type_output(unsigned int type)304 static unsigned int meson_gpio_irq_type_output(unsigned int type)
305 {
306 unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
307
308 type &= ~IRQ_TYPE_SENSE_MASK;
309
310 /*
311 * The polarity of the signal provided to the GIC should always
312 * be high.
313 */
314 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
315 type |= IRQ_TYPE_LEVEL_HIGH;
316 else
317 type |= IRQ_TYPE_EDGE_RISING;
318
319 return type;
320 }
321
meson_gpio_irq_set_type(struct irq_data * data,unsigned int type)322 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
323 {
324 struct meson_gpio_irq_controller *ctl = data->domain->host_data;
325 u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
326 int ret;
327
328 ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
329 if (ret)
330 return ret;
331
332 return irq_chip_set_type_parent(data,
333 meson_gpio_irq_type_output(type));
334 }
335
336 static struct irq_chip meson_gpio_irq_chip = {
337 .name = "meson-gpio-irqchip",
338 .irq_mask = irq_chip_mask_parent,
339 .irq_unmask = irq_chip_unmask_parent,
340 .irq_eoi = irq_chip_eoi_parent,
341 .irq_set_type = meson_gpio_irq_set_type,
342 .irq_retrigger = irq_chip_retrigger_hierarchy,
343 #ifdef CONFIG_SMP
344 .irq_set_affinity = irq_chip_set_affinity_parent,
345 #endif
346 .flags = IRQCHIP_SET_TYPE_MASKED,
347 };
348
meson_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)349 static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
350 struct irq_fwspec *fwspec,
351 unsigned long *hwirq,
352 unsigned int *type)
353 {
354 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
355 *hwirq = fwspec->param[0];
356 *type = fwspec->param[1];
357 return 0;
358 }
359
360 return -EINVAL;
361 }
362
meson_gpio_irq_allocate_gic_irq(struct irq_domain * domain,unsigned int virq,u32 hwirq,unsigned int type)363 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
364 unsigned int virq,
365 u32 hwirq,
366 unsigned int type)
367 {
368 struct irq_fwspec fwspec;
369
370 fwspec.fwnode = domain->parent->fwnode;
371 fwspec.param_count = 3;
372 fwspec.param[0] = 0; /* SPI */
373 fwspec.param[1] = hwirq;
374 fwspec.param[2] = meson_gpio_irq_type_output(type);
375
376 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
377 }
378
meson_gpio_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)379 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
380 unsigned int virq,
381 unsigned int nr_irqs,
382 void *data)
383 {
384 struct irq_fwspec *fwspec = data;
385 struct meson_gpio_irq_controller *ctl = domain->host_data;
386 unsigned long hwirq;
387 u32 *channel_hwirq;
388 unsigned int type;
389 int ret;
390
391 if (WARN_ON(nr_irqs != 1))
392 return -EINVAL;
393
394 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
395 if (ret)
396 return ret;
397
398 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
399 if (ret)
400 return ret;
401
402 ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
403 *channel_hwirq, type);
404 if (ret < 0) {
405 pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
406 meson_gpio_irq_release_channel(ctl, channel_hwirq);
407 return ret;
408 }
409
410 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
411 &meson_gpio_irq_chip, channel_hwirq);
412
413 return 0;
414 }
415
meson_gpio_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)416 static void meson_gpio_irq_domain_free(struct irq_domain *domain,
417 unsigned int virq,
418 unsigned int nr_irqs)
419 {
420 struct meson_gpio_irq_controller *ctl = domain->host_data;
421 struct irq_data *irq_data;
422 u32 *channel_hwirq;
423
424 if (WARN_ON(nr_irqs != 1))
425 return;
426
427 irq_domain_free_irqs_parent(domain, virq, 1);
428
429 irq_data = irq_domain_get_irq_data(domain, virq);
430 channel_hwirq = irq_data_get_irq_chip_data(irq_data);
431
432 meson_gpio_irq_release_channel(ctl, channel_hwirq);
433 }
434
435 static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
436 .alloc = meson_gpio_irq_domain_alloc,
437 .free = meson_gpio_irq_domain_free,
438 .translate = meson_gpio_irq_domain_translate,
439 };
440
meson_gpio_irq_parse_dt(struct device_node * node,struct meson_gpio_irq_controller * ctl)441 static int meson_gpio_irq_parse_dt(struct device_node *node,
442 struct meson_gpio_irq_controller *ctl)
443 {
444 const struct of_device_id *match;
445 int ret;
446
447 match = of_match_node(meson_irq_gpio_matches, node);
448 if (!match)
449 return -ENODEV;
450
451 ctl->params = match->data;
452
453 ret = of_property_read_variable_u32_array(node,
454 "amlogic,channel-interrupts",
455 ctl->channel_irqs,
456 NUM_CHANNEL,
457 NUM_CHANNEL);
458 if (ret < 0) {
459 pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
460 return ret;
461 }
462
463 ctl->params->ops.gpio_irq_init(ctl);
464
465 return 0;
466 }
467
meson_gpio_intc_probe(struct platform_device * pdev)468 static int meson_gpio_intc_probe(struct platform_device *pdev)
469 {
470 struct device_node *node = pdev->dev.of_node, *parent;
471 struct meson_gpio_irq_controller *ctl;
472 struct irq_domain *parent_domain;
473 struct resource *res;
474 int ret;
475
476 parent = of_irq_find_parent(node);
477 if (!parent) {
478 dev_err(&pdev->dev, "missing parent interrupt node\n");
479 return -ENODEV;
480 }
481
482 parent_domain = irq_find_host(parent);
483 if (!parent_domain) {
484 dev_err(&pdev->dev, "unable to obtain parent domain\n");
485 return -ENXIO;
486 }
487
488 ctl = devm_kzalloc(&pdev->dev, sizeof(*ctl), GFP_KERNEL);
489 if (!ctl)
490 return -ENOMEM;
491
492 spin_lock_init(&ctl->lock);
493
494 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
495 ctl->base = devm_ioremap_resource(&pdev->dev, res);
496 if (IS_ERR(ctl->base))
497 return PTR_ERR(ctl->base);
498
499 ret = meson_gpio_irq_parse_dt(node, ctl);
500 if (ret)
501 return ret;
502
503 ctl->domain = irq_domain_create_hierarchy(parent_domain, 0,
504 ctl->params->nr_hwirq,
505 of_node_to_fwnode(node),
506 &meson_gpio_irq_domain_ops,
507 ctl);
508 if (!ctl->domain) {
509 dev_err(&pdev->dev, "failed to add domain\n");
510 return -ENODEV;
511 }
512
513 platform_set_drvdata(pdev, ctl);
514
515 dev_info(&pdev->dev, "%d to %d gpio interrupt mux initialized\n",
516 ctl->params->nr_hwirq, NUM_CHANNEL);
517
518 return 0;
519 }
520
meson_gpio_intc_remove(struct platform_device * pdev)521 static int meson_gpio_intc_remove(struct platform_device *pdev)
522 {
523 struct meson_gpio_irq_controller *ctl = platform_get_drvdata(pdev);
524
525 irq_domain_remove(ctl->domain);
526
527 return 0;
528 }
529
530 static const struct of_device_id meson_gpio_intc_of_match[] = {
531 { .compatible = "amlogic,meson-gpio-intc", },
532 {},
533 };
534 MODULE_DEVICE_TABLE(of, meson_gpio_intc_of_match);
535
536 static struct platform_driver meson_gpio_intc_driver = {
537 .probe = meson_gpio_intc_probe,
538 .remove = meson_gpio_intc_remove,
539 .driver = {
540 .name = "meson-gpio-intc",
541 .of_match_table = meson_gpio_intc_of_match,
542 },
543 };
544 module_platform_driver(meson_gpio_intc_driver);
545
546 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
547 MODULE_LICENSE("GPL v2");
548 MODULE_ALIAS("platform:meson-gpio-intc");
549