1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * cx18 ADEC firmware functions
4 *
5 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
7 */
8
9 #include "cx18-driver.h"
10 #include "cx18-io.h"
11 #include <linux/firmware.h>
12
13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
19
20 #define FWFILE "v4l-cx23418-dig.fw"
21
cx18_av_verifyfw(struct cx18 * cx,const struct firmware * fw)22 static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
23 {
24 struct v4l2_subdev *sd = &cx->av_state.sd;
25 int ret = 0;
26 const u8 *data;
27 u32 size;
28 int addr;
29 u32 expected, dl_control;
30
31 /* Ensure we put the 8051 in reset and enable firmware upload mode */
32 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
33 do {
34 dl_control &= 0x00ffffff;
35 dl_control |= 0x0f000000;
36 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
37 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
38 } while ((dl_control & 0xff000000) != 0x0f000000);
39
40 /* Read and auto increment until at address 0x0000 */
41 while (dl_control & 0x3fff)
42 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
43
44 data = fw->data;
45 size = fw->size;
46 for (addr = 0; addr < size; addr++) {
47 dl_control &= 0xffff3fff; /* ignore top 2 bits of address */
48 expected = 0x0f000000 | ((u32)data[addr] << 16) | addr;
49 if (expected != dl_control) {
50 CX18_ERR_DEV(sd, "verification of %s firmware load failed: expected %#010x got %#010x\n",
51 FWFILE, expected, dl_control);
52 ret = -EIO;
53 break;
54 }
55 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
56 }
57 if (ret == 0)
58 CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n",
59 FWFILE, size);
60 return ret;
61 }
62
cx18_av_loadfw(struct cx18 * cx)63 int cx18_av_loadfw(struct cx18 *cx)
64 {
65 struct v4l2_subdev *sd = &cx->av_state.sd;
66 const struct firmware *fw = NULL;
67 u32 size;
68 u32 u, v;
69 const u8 *ptr;
70 int i;
71 int retries1 = 0;
72
73 if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) {
74 CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE);
75 return -EINVAL;
76 }
77
78 /* The firmware load often has byte errors, so allow for several
79 retries, both at byte level and at the firmware load level. */
80 while (retries1 < 5) {
81 cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
82 0x00008430, 0xffffffff); /* cx25843 */
83 cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
84
85 /* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */
86 cx18_av_write4_expect(cx, 0x8100, 0x00010000,
87 0x00008430, 0xffffffff); /* cx25843 */
88
89 /* Put the 8051 in reset and enable firmware upload */
90 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
91
92 ptr = fw->data;
93 size = fw->size;
94
95 for (i = 0; i < size; i++) {
96 u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
97 u32 value = 0;
98 int retries2;
99 int unrec_err = 0;
100
101 for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
102 retries2++) {
103 cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
104 dl_control);
105 udelay(10);
106 value = cx18_av_read4(cx, CXADEC_DL_CTL);
107 if (value == dl_control)
108 break;
109 /* Check if we can correct the byte by changing
110 the address. We can only write the lower
111 address byte of the address. */
112 if ((value & 0x3F00) != (dl_control & 0x3F00)) {
113 unrec_err = 1;
114 break;
115 }
116 }
117 if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
118 break;
119 }
120 if (i == size)
121 break;
122 retries1++;
123 }
124 if (retries1 >= 5) {
125 CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE);
126 release_firmware(fw);
127 return -EIO;
128 }
129
130 cx18_av_write4_expect(cx, CXADEC_DL_CTL,
131 0x03000000 | fw->size, 0x03000000, 0x13000000);
132
133 CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
134
135 if (cx18_av_verifyfw(cx, fw) == 0)
136 cx18_av_write4_expect(cx, CXADEC_DL_CTL,
137 0x13000000 | fw->size, 0x13000000, 0x13000000);
138
139 /* Output to the 416 */
140 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
141
142 /* Audio input control 1 set to Sony mode */
143 /* Audio output input 2 is 0 for slave operation input */
144 /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
145 /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
146 after WS transition for first bit of audio word. */
147 cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
148
149 /* Audio output control 1 is set to Sony mode */
150 /* Audio output control 2 is set to 1 for master mode */
151 /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
152 /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
153 after WS transition for first bit of audio word. */
154 /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
155 are generated) */
156 cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
157
158 /* set alt I2s master clock to /0x16 and enable alt divider i2s
159 passthrough */
160 cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
161
162 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
163 0x3F00FFFF);
164 /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
165
166 /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
167 /* Register 0x09CC is defined by the Merlin firmware, and doesn't
168 have a name in the spec. */
169 cx18_av_write4(cx, 0x09CC, 1);
170
171 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
172 /* If bit 11 is 1, clear bit 10 */
173 if (v & 0x800)
174 cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
175 0, 0x400);
176
177 /* Toggle the AI1 MUX */
178 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
179 u = v & CX18_AI1_MUX_MASK;
180 v &= ~CX18_AI1_MUX_MASK;
181 if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) {
182 /* Switch to I2S1 */
183 v |= CX18_AI1_MUX_I2S1;
184 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
185 v, CX18_AI1_MUX_MASK);
186 /* Switch back to the A/V decoder core I2S output */
187 v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
188 } else {
189 /* Switch to the A/V decoder core I2S output */
190 v |= CX18_AI1_MUX_843_I2S;
191 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
192 v, CX18_AI1_MUX_MASK);
193 /* Switch back to I2S1 or I2S2 */
194 v = (v & ~CX18_AI1_MUX_MASK) | u;
195 }
196 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
197 v, CX18_AI1_MUX_MASK);
198
199 /* Enable WW auto audio standard detection */
200 v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
201 v |= 0xFF; /* Auto by default */
202 v |= 0x400; /* Stereo by default */
203 v |= 0x14000000;
204 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
205
206 release_firmware(fw);
207 return 0;
208 }
209
210 MODULE_FIRMWARE(FWFILE);
211