1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_PORT_H 8 #define HINIC_PORT_H 9 10 #include <linux/types.h> 11 #include <linux/etherdevice.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_dev.h" 15 16 #define HINIC_RSS_KEY_SIZE 40 17 #define HINIC_RSS_INDIR_SIZE 256 18 #define HINIC_PORT_STATS_VERSION 0 19 #define HINIC_FW_VERSION_NAME 16 20 #define HINIC_COMPILE_TIME_LEN 20 21 #define HINIC_MGMT_VERSION_MAX_LEN 32 22 23 struct hinic_version_info { 24 u8 status; 25 u8 version; 26 u8 rsvd[6]; 27 28 u8 ver[HINIC_FW_VERSION_NAME]; 29 u8 time[HINIC_COMPILE_TIME_LEN]; 30 }; 31 32 enum hinic_rx_mode { 33 HINIC_RX_MODE_UC = BIT(0), 34 HINIC_RX_MODE_MC = BIT(1), 35 HINIC_RX_MODE_BC = BIT(2), 36 HINIC_RX_MODE_MC_ALL = BIT(3), 37 HINIC_RX_MODE_PROMISC = BIT(4), 38 }; 39 40 enum hinic_port_link_state { 41 HINIC_LINK_STATE_DOWN, 42 HINIC_LINK_STATE_UP, 43 }; 44 45 enum hinic_port_state { 46 HINIC_PORT_DISABLE = 0, 47 HINIC_PORT_ENABLE = 3, 48 }; 49 50 enum hinic_func_port_state { 51 HINIC_FUNC_PORT_DISABLE = 0, 52 HINIC_FUNC_PORT_ENABLE = 2, 53 }; 54 55 enum hinic_autoneg_cap { 56 HINIC_AUTONEG_UNSUPPORTED, 57 HINIC_AUTONEG_SUPPORTED, 58 }; 59 60 enum hinic_autoneg_state { 61 HINIC_AUTONEG_DISABLED, 62 HINIC_AUTONEG_ACTIVE, 63 }; 64 65 enum hinic_duplex { 66 HINIC_DUPLEX_HALF, 67 HINIC_DUPLEX_FULL, 68 }; 69 70 enum hinic_speed { 71 HINIC_SPEED_10MB_LINK = 0, 72 HINIC_SPEED_100MB_LINK, 73 HINIC_SPEED_1000MB_LINK, 74 HINIC_SPEED_10GB_LINK, 75 HINIC_SPEED_25GB_LINK, 76 HINIC_SPEED_40GB_LINK, 77 HINIC_SPEED_100GB_LINK, 78 79 HINIC_SPEED_UNKNOWN = 0xFF, 80 }; 81 82 enum hinic_link_mode { 83 HINIC_10GE_BASE_KR = 0, 84 HINIC_40GE_BASE_KR4 = 1, 85 HINIC_40GE_BASE_CR4 = 2, 86 HINIC_100GE_BASE_KR4 = 3, 87 HINIC_100GE_BASE_CR4 = 4, 88 HINIC_25GE_BASE_KR_S = 5, 89 HINIC_25GE_BASE_CR_S = 6, 90 HINIC_25GE_BASE_KR = 7, 91 HINIC_25GE_BASE_CR = 8, 92 HINIC_GE_BASE_KX = 9, 93 HINIC_LINK_MODE_NUMBERS, 94 95 HINIC_SUPPORTED_UNKNOWN = 0xFFFF, 96 }; 97 98 enum hinic_port_type { 99 HINIC_PORT_TP, /* BASET */ 100 HINIC_PORT_AUI, 101 HINIC_PORT_MII, 102 HINIC_PORT_FIBRE, /* OPTICAL */ 103 HINIC_PORT_BNC, 104 HINIC_PORT_ELEC, 105 HINIC_PORT_COPPER, /* PORT_DA */ 106 HINIC_PORT_AOC, 107 HINIC_PORT_BACKPLANE, 108 HINIC_PORT_NONE = 0xEF, 109 HINIC_PORT_OTHER = 0xFF, 110 }; 111 112 enum hinic_valid_link_settings { 113 HILINK_LINK_SET_SPEED = 0x1, 114 HILINK_LINK_SET_AUTONEG = 0x2, 115 HILINK_LINK_SET_FEC = 0x4, 116 }; 117 118 enum hinic_tso_state { 119 HINIC_TSO_DISABLE = 0, 120 HINIC_TSO_ENABLE = 1, 121 }; 122 123 struct hinic_port_mac_cmd { 124 u8 status; 125 u8 version; 126 u8 rsvd0[6]; 127 128 u16 func_idx; 129 u16 vlan_id; 130 u16 rsvd1; 131 unsigned char mac[ETH_ALEN]; 132 }; 133 134 struct hinic_port_mtu_cmd { 135 u8 status; 136 u8 version; 137 u8 rsvd0[6]; 138 139 u16 func_idx; 140 u16 rsvd1; 141 u32 mtu; 142 }; 143 144 struct hinic_port_vlan_cmd { 145 u8 status; 146 u8 version; 147 u8 rsvd0[6]; 148 149 u16 func_idx; 150 u16 vlan_id; 151 }; 152 153 struct hinic_port_rx_mode_cmd { 154 u8 status; 155 u8 version; 156 u8 rsvd0[6]; 157 158 u16 func_idx; 159 u16 rsvd; 160 u32 rx_mode; 161 }; 162 163 struct hinic_port_link_cmd { 164 u8 status; 165 u8 version; 166 u8 rsvd0[6]; 167 168 u16 func_idx; 169 u8 state; 170 u8 rsvd1; 171 }; 172 173 struct hinic_port_state_cmd { 174 u8 status; 175 u8 version; 176 u8 rsvd0[6]; 177 178 u8 state; 179 u8 rsvd1[3]; 180 }; 181 182 struct hinic_port_link_status { 183 u8 status; 184 u8 version; 185 u8 rsvd0[6]; 186 187 u16 func_id; 188 u8 link; 189 u8 port_id; 190 }; 191 192 struct hinic_cable_plug_event { 193 u8 status; 194 u8 version; 195 u8 rsvd0[6]; 196 197 u16 func_id; 198 u8 plugged; /* 0: unplugged, 1: plugged */ 199 u8 port_id; 200 }; 201 202 enum link_err_type { 203 LINK_ERR_MODULE_UNRECOGENIZED, 204 LINK_ERR_NUM, 205 }; 206 207 struct hinic_link_err_event { 208 u8 status; 209 u8 version; 210 u8 rsvd0[6]; 211 212 u16 func_id; 213 u8 err_type; 214 u8 port_id; 215 }; 216 217 struct hinic_port_func_state_cmd { 218 u8 status; 219 u8 version; 220 u8 rsvd0[6]; 221 222 u16 func_idx; 223 u16 rsvd1; 224 u8 state; 225 u8 rsvd2[3]; 226 }; 227 228 struct hinic_port_cap { 229 u8 status; 230 u8 version; 231 u8 rsvd0[6]; 232 233 u16 func_idx; 234 u16 rsvd1; 235 u8 port_type; 236 u8 autoneg_cap; 237 u8 autoneg_state; 238 u8 duplex; 239 u8 speed; 240 u8 rsvd2[3]; 241 }; 242 243 struct hinic_link_mode_cmd { 244 u8 status; 245 u8 version; 246 u8 rsvd0[6]; 247 248 u16 func_id; 249 u16 rsvd1; 250 u16 supported; /* 0xFFFF represents invalid value */ 251 u16 advertised; 252 }; 253 254 struct hinic_speed_cmd { 255 u8 status; 256 u8 version; 257 u8 rsvd0[6]; 258 259 u16 func_id; 260 u16 speed; 261 }; 262 263 struct hinic_set_autoneg_cmd { 264 u8 status; 265 u8 version; 266 u8 rsvd0[6]; 267 268 u16 func_id; 269 u16 enable; /* 1: enable , 0: disable */ 270 }; 271 272 struct hinic_link_ksettings_info { 273 u8 status; 274 u8 version; 275 u8 rsvd0[6]; 276 277 u16 func_id; 278 u16 rsvd1; 279 280 u32 valid_bitmap; 281 u32 speed; /* enum nic_speed_level */ 282 u8 autoneg; /* 0 - off; 1 - on */ 283 u8 fec; /* 0 - RSFEC; 1 - BASEFEC; 2 - NOFEC */ 284 u8 rsvd2[18]; /* reserved for duplex, port, etc. */ 285 }; 286 287 struct hinic_tso_config { 288 u8 status; 289 u8 version; 290 u8 rsvd0[6]; 291 292 u16 func_id; 293 u16 rsvd1; 294 u8 tso_en; 295 u8 resv2[3]; 296 }; 297 298 struct hinic_checksum_offload { 299 u8 status; 300 u8 version; 301 u8 rsvd0[6]; 302 303 u16 func_id; 304 u16 rsvd1; 305 u32 rx_csum_offload; 306 }; 307 308 struct hinic_rq_num { 309 u8 status; 310 u8 version; 311 u8 rsvd0[6]; 312 313 u16 func_id; 314 u16 rsvd1[33]; 315 u32 num_rqs; 316 u32 rq_depth; 317 }; 318 319 struct hinic_lro_config { 320 u8 status; 321 u8 version; 322 u8 rsvd0[6]; 323 324 u16 func_id; 325 u16 rsvd1; 326 u8 lro_ipv4_en; 327 u8 lro_ipv6_en; 328 u8 lro_max_wqe_num; 329 u8 resv2[13]; 330 }; 331 332 struct hinic_lro_timer { 333 u8 status; 334 u8 version; 335 u8 rsvd0[6]; 336 337 u8 type; /* 0: set timer value, 1: get timer value */ 338 u8 enable; /* when set lro time, enable should be 1 */ 339 u16 rsvd1; 340 u32 timer; 341 }; 342 343 struct hinic_vlan_cfg { 344 u8 status; 345 u8 version; 346 u8 rsvd0[6]; 347 348 u16 func_id; 349 u8 vlan_rx_offload; 350 u8 rsvd1[5]; 351 }; 352 353 struct hinic_rss_template_mgmt { 354 u8 status; 355 u8 version; 356 u8 rsvd0[6]; 357 358 u16 func_id; 359 u8 cmd; 360 u8 template_id; 361 u8 rsvd1[4]; 362 }; 363 364 struct hinic_rss_template_key { 365 u8 status; 366 u8 version; 367 u8 rsvd0[6]; 368 369 u16 func_id; 370 u8 template_id; 371 u8 rsvd1; 372 u8 key[HINIC_RSS_KEY_SIZE]; 373 }; 374 375 struct hinic_rss_context_tbl { 376 u32 group_index; 377 u32 offset; 378 u32 size; 379 u32 rsvd; 380 u32 ctx; 381 }; 382 383 struct hinic_rss_context_table { 384 u8 status; 385 u8 version; 386 u8 rsvd0[6]; 387 388 u16 func_id; 389 u8 template_id; 390 u8 rsvd1; 391 u32 context; 392 }; 393 394 struct hinic_rss_indirect_tbl { 395 u32 group_index; 396 u32 offset; 397 u32 size; 398 u32 rsvd; 399 u8 entry[HINIC_RSS_INDIR_SIZE]; 400 }; 401 402 struct hinic_rss_indir_table { 403 u8 status; 404 u8 version; 405 u8 rsvd0[6]; 406 407 u16 func_id; 408 u8 template_id; 409 u8 rsvd1; 410 u8 indir[HINIC_RSS_INDIR_SIZE]; 411 }; 412 413 struct hinic_rss_key { 414 u8 status; 415 u8 version; 416 u8 rsvd0[6]; 417 418 u16 func_id; 419 u8 template_id; 420 u8 rsvd1; 421 u8 key[HINIC_RSS_KEY_SIZE]; 422 }; 423 424 struct hinic_rss_engine_type { 425 u8 status; 426 u8 version; 427 u8 rsvd0[6]; 428 429 u16 func_id; 430 u8 template_id; 431 u8 hash_engine; 432 u8 rsvd1[4]; 433 }; 434 435 struct hinic_rss_config { 436 u8 status; 437 u8 version; 438 u8 rsvd0[6]; 439 440 u16 func_id; 441 u8 rss_en; 442 u8 template_id; 443 u8 rq_priority_number; 444 u8 rsvd1[11]; 445 }; 446 447 struct hinic_stats { 448 char name[ETH_GSTRING_LEN]; 449 u32 size; 450 int offset; 451 }; 452 453 struct hinic_vport_stats { 454 u64 tx_unicast_pkts_vport; 455 u64 tx_unicast_bytes_vport; 456 u64 tx_multicast_pkts_vport; 457 u64 tx_multicast_bytes_vport; 458 u64 tx_broadcast_pkts_vport; 459 u64 tx_broadcast_bytes_vport; 460 461 u64 rx_unicast_pkts_vport; 462 u64 rx_unicast_bytes_vport; 463 u64 rx_multicast_pkts_vport; 464 u64 rx_multicast_bytes_vport; 465 u64 rx_broadcast_pkts_vport; 466 u64 rx_broadcast_bytes_vport; 467 468 u64 tx_discard_vport; 469 u64 rx_discard_vport; 470 u64 tx_err_vport; 471 u64 rx_err_vport; 472 }; 473 474 struct hinic_phy_port_stats { 475 u64 mac_rx_total_pkt_num; 476 u64 mac_rx_total_oct_num; 477 u64 mac_rx_bad_pkt_num; 478 u64 mac_rx_bad_oct_num; 479 u64 mac_rx_good_pkt_num; 480 u64 mac_rx_good_oct_num; 481 u64 mac_rx_uni_pkt_num; 482 u64 mac_rx_multi_pkt_num; 483 u64 mac_rx_broad_pkt_num; 484 485 u64 mac_tx_total_pkt_num; 486 u64 mac_tx_total_oct_num; 487 u64 mac_tx_bad_pkt_num; 488 u64 mac_tx_bad_oct_num; 489 u64 mac_tx_good_pkt_num; 490 u64 mac_tx_good_oct_num; 491 u64 mac_tx_uni_pkt_num; 492 u64 mac_tx_multi_pkt_num; 493 u64 mac_tx_broad_pkt_num; 494 495 u64 mac_rx_fragment_pkt_num; 496 u64 mac_rx_undersize_pkt_num; 497 u64 mac_rx_undermin_pkt_num; 498 u64 mac_rx_64_oct_pkt_num; 499 u64 mac_rx_65_127_oct_pkt_num; 500 u64 mac_rx_128_255_oct_pkt_num; 501 u64 mac_rx_256_511_oct_pkt_num; 502 u64 mac_rx_512_1023_oct_pkt_num; 503 u64 mac_rx_1024_1518_oct_pkt_num; 504 u64 mac_rx_1519_2047_oct_pkt_num; 505 u64 mac_rx_2048_4095_oct_pkt_num; 506 u64 mac_rx_4096_8191_oct_pkt_num; 507 u64 mac_rx_8192_9216_oct_pkt_num; 508 u64 mac_rx_9217_12287_oct_pkt_num; 509 u64 mac_rx_12288_16383_oct_pkt_num; 510 u64 mac_rx_1519_max_bad_pkt_num; 511 u64 mac_rx_1519_max_good_pkt_num; 512 u64 mac_rx_oversize_pkt_num; 513 u64 mac_rx_jabber_pkt_num; 514 515 u64 mac_rx_pause_num; 516 u64 mac_rx_pfc_pkt_num; 517 u64 mac_rx_pfc_pri0_pkt_num; 518 u64 mac_rx_pfc_pri1_pkt_num; 519 u64 mac_rx_pfc_pri2_pkt_num; 520 u64 mac_rx_pfc_pri3_pkt_num; 521 u64 mac_rx_pfc_pri4_pkt_num; 522 u64 mac_rx_pfc_pri5_pkt_num; 523 u64 mac_rx_pfc_pri6_pkt_num; 524 u64 mac_rx_pfc_pri7_pkt_num; 525 u64 mac_rx_control_pkt_num; 526 u64 mac_rx_y1731_pkt_num; 527 u64 mac_rx_sym_err_pkt_num; 528 u64 mac_rx_fcs_err_pkt_num; 529 u64 mac_rx_send_app_good_pkt_num; 530 u64 mac_rx_send_app_bad_pkt_num; 531 532 u64 mac_tx_fragment_pkt_num; 533 u64 mac_tx_undersize_pkt_num; 534 u64 mac_tx_undermin_pkt_num; 535 u64 mac_tx_64_oct_pkt_num; 536 u64 mac_tx_65_127_oct_pkt_num; 537 u64 mac_tx_128_255_oct_pkt_num; 538 u64 mac_tx_256_511_oct_pkt_num; 539 u64 mac_tx_512_1023_oct_pkt_num; 540 u64 mac_tx_1024_1518_oct_pkt_num; 541 u64 mac_tx_1519_2047_oct_pkt_num; 542 u64 mac_tx_2048_4095_oct_pkt_num; 543 u64 mac_tx_4096_8191_oct_pkt_num; 544 u64 mac_tx_8192_9216_oct_pkt_num; 545 u64 mac_tx_9217_12287_oct_pkt_num; 546 u64 mac_tx_12288_16383_oct_pkt_num; 547 u64 mac_tx_1519_max_bad_pkt_num; 548 u64 mac_tx_1519_max_good_pkt_num; 549 u64 mac_tx_oversize_pkt_num; 550 u64 mac_tx_jabber_pkt_num; 551 552 u64 mac_tx_pause_num; 553 u64 mac_tx_pfc_pkt_num; 554 u64 mac_tx_pfc_pri0_pkt_num; 555 u64 mac_tx_pfc_pri1_pkt_num; 556 u64 mac_tx_pfc_pri2_pkt_num; 557 u64 mac_tx_pfc_pri3_pkt_num; 558 u64 mac_tx_pfc_pri4_pkt_num; 559 u64 mac_tx_pfc_pri5_pkt_num; 560 u64 mac_tx_pfc_pri6_pkt_num; 561 u64 mac_tx_pfc_pri7_pkt_num; 562 u64 mac_tx_control_pkt_num; 563 u64 mac_tx_y1731_pkt_num; 564 u64 mac_tx_1588_pkt_num; 565 u64 mac_tx_err_all_pkt_num; 566 u64 mac_tx_from_app_good_pkt_num; 567 u64 mac_tx_from_app_bad_pkt_num; 568 569 u64 mac_rx_higig2_ext_pkt_num; 570 u64 mac_rx_higig2_message_pkt_num; 571 u64 mac_rx_higig2_error_pkt_num; 572 u64 mac_rx_higig2_cpu_ctrl_pkt_num; 573 u64 mac_rx_higig2_unicast_pkt_num; 574 u64 mac_rx_higig2_broadcast_pkt_num; 575 u64 mac_rx_higig2_l2_multicast_pkt_num; 576 u64 mac_rx_higig2_l3_multicast_pkt_num; 577 578 u64 mac_tx_higig2_message_pkt_num; 579 u64 mac_tx_higig2_ext_pkt_num; 580 u64 mac_tx_higig2_cpu_ctrl_pkt_num; 581 u64 mac_tx_higig2_unicast_pkt_num; 582 u64 mac_tx_higig2_broadcast_pkt_num; 583 u64 mac_tx_higig2_l2_multicast_pkt_num; 584 u64 mac_tx_higig2_l3_multicast_pkt_num; 585 }; 586 587 struct hinic_port_stats_info { 588 u8 status; 589 u8 version; 590 u8 rsvd0[6]; 591 592 u16 func_id; 593 u16 rsvd1; 594 u32 stats_version; 595 u32 stats_size; 596 }; 597 598 struct hinic_port_stats { 599 u8 status; 600 u8 version; 601 u8 rsvd[6]; 602 603 struct hinic_phy_port_stats stats; 604 }; 605 606 struct hinic_cmd_vport_stats { 607 u8 status; 608 u8 version; 609 u8 rsvd0[6]; 610 611 struct hinic_vport_stats stats; 612 }; 613 614 struct hinic_tx_rate_cfg_max_min { 615 u8 status; 616 u8 version; 617 u8 rsvd0[6]; 618 619 u16 func_id; 620 u16 rsvd1; 621 u32 min_rate; 622 u32 max_rate; 623 u8 rsvd2[8]; 624 }; 625 626 struct hinic_tx_rate_cfg { 627 u8 status; 628 u8 version; 629 u8 rsvd0[6]; 630 631 u16 func_id; 632 u16 rsvd1; 633 u32 tx_rate; 634 }; 635 636 enum nic_speed_level { 637 LINK_SPEED_10MB = 0, 638 LINK_SPEED_100MB, 639 LINK_SPEED_1GB, 640 LINK_SPEED_10GB, 641 LINK_SPEED_25GB, 642 LINK_SPEED_40GB, 643 LINK_SPEED_100GB, 644 LINK_SPEED_LEVELS, 645 }; 646 647 struct hinic_spoofchk_set { 648 u8 status; 649 u8 version; 650 u8 rsvd0[6]; 651 652 u8 state; 653 u8 rsvd1; 654 u16 func_id; 655 }; 656 657 struct hinic_pause_config { 658 u8 status; 659 u8 version; 660 u8 rsvd0[6]; 661 662 u16 func_id; 663 u16 rsvd1; 664 u32 auto_neg; 665 u32 rx_pause; 666 u32 tx_pause; 667 }; 668 669 struct hinic_set_pfc { 670 u8 status; 671 u8 version; 672 u8 rsvd0[6]; 673 674 u16 func_id; 675 u8 pfc_en; 676 u8 pfc_bitmap; 677 u8 rsvd1[4]; 678 }; 679 680 /* get or set loopback mode, need to modify by base API */ 681 #define HINIC_INTERNAL_LP_MODE 5 682 #define LOOP_MODE_MIN 1 683 #define LOOP_MODE_MAX 6 684 685 struct hinic_port_loopback { 686 u8 status; 687 u8 version; 688 u8 rsvd[6]; 689 690 u32 mode; 691 u32 en; 692 }; 693 694 struct hinic_led_info { 695 u8 status; 696 u8 version; 697 u8 rsvd0[6]; 698 699 u8 port; 700 u8 type; 701 u8 mode; 702 u8 reset; 703 }; 704 705 #define STD_SFP_INFO_MAX_SIZE 640 706 707 struct hinic_cmd_get_light_module_abs { 708 u8 status; 709 u8 version; 710 u8 rsvd0[6]; 711 712 u8 port_id; 713 u8 abs_status; /* 0:present, 1:absent */ 714 u8 rsv[2]; 715 }; 716 717 #define STD_SFP_INFO_MAX_SIZE 640 718 719 struct hinic_cmd_get_std_sfp_info { 720 u8 status; 721 u8 version; 722 u8 rsvd0[6]; 723 724 u8 port_id; 725 u8 wire_type; 726 u16 eeprom_len; 727 u32 rsvd; 728 u8 sfp_info[STD_SFP_INFO_MAX_SIZE]; 729 }; 730 731 struct hinic_cmd_update_fw { 732 u8 status; 733 u8 version; 734 u8 rsvd0[6]; 735 736 struct { 737 u32 SL:1; 738 u32 SF:1; 739 u32 flag:1; 740 u32 reserved:13; 741 u32 fragment_len:16; 742 } ctl_info; 743 744 struct { 745 u32 FW_section_CRC; 746 u32 FW_section_type; 747 } section_info; 748 749 u32 total_len; 750 u32 setion_total_len; 751 u32 fw_section_version; 752 u32 section_offset; 753 u32 data[384]; 754 }; 755 756 int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr, 757 u16 vlan_id); 758 759 int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr, 760 u16 vlan_id); 761 762 int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr); 763 764 int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu); 765 766 int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id); 767 768 int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id); 769 770 int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode); 771 772 int hinic_port_link_state(struct hinic_dev *nic_dev, 773 enum hinic_port_link_state *link_state); 774 775 int hinic_port_set_state(struct hinic_dev *nic_dev, 776 enum hinic_port_state state); 777 778 int hinic_port_set_func_state(struct hinic_dev *nic_dev, 779 enum hinic_func_port_state state); 780 781 int hinic_port_get_cap(struct hinic_dev *nic_dev, 782 struct hinic_port_cap *port_cap); 783 784 int hinic_set_max_qnum(struct hinic_dev *nic_dev, u8 num_rqs); 785 786 int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state); 787 788 int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en); 789 790 int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en, 791 u32 lro_timer, u32 wqe_num); 792 793 int hinic_set_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx, 794 struct hinic_rss_type rss_type); 795 796 int hinic_rss_set_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx, 797 const u32 *indir_table); 798 799 int hinic_rss_set_template_tbl(struct hinic_dev *nic_dev, u32 template_id, 800 const u8 *temp); 801 802 int hinic_rss_set_hash_engine(struct hinic_dev *nic_dev, u8 template_id, 803 u8 type); 804 805 int hinic_rss_cfg(struct hinic_dev *nic_dev, u8 rss_en, u8 template_id); 806 807 int hinic_rss_template_alloc(struct hinic_dev *nic_dev, u8 *tmpl_idx); 808 809 int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx); 810 811 void hinic_set_ethtool_ops(struct net_device *netdev); 812 813 int hinic_get_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx, 814 struct hinic_rss_type *rss_type); 815 816 int hinic_rss_get_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx, 817 u32 *indir_table); 818 819 int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx, 820 u8 *temp); 821 822 int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx, 823 u8 *type); 824 825 int hinic_get_phy_port_stats(struct hinic_dev *nic_dev, 826 struct hinic_phy_port_stats *stats); 827 828 int hinic_get_vport_stats(struct hinic_dev *nic_dev, 829 struct hinic_vport_stats *stats); 830 831 int hinic_set_rx_vlan_offload(struct hinic_dev *nic_dev, u8 en); 832 833 int hinic_get_mgmt_version(struct hinic_dev *nic_dev, u8 *mgmt_ver); 834 835 int hinic_set_link_settings(struct hinic_hwdev *hwdev, 836 struct hinic_link_ksettings_info *info); 837 838 int hinic_get_link_mode(struct hinic_hwdev *hwdev, 839 struct hinic_link_mode_cmd *link_mode); 840 841 int hinic_set_autoneg(struct hinic_hwdev *hwdev, bool enable); 842 843 int hinic_set_speed(struct hinic_hwdev *hwdev, enum nic_speed_level speed); 844 845 int hinic_get_hw_pause_info(struct hinic_hwdev *hwdev, 846 struct hinic_pause_config *pause_info); 847 848 int hinic_set_hw_pause_info(struct hinic_hwdev *hwdev, 849 struct hinic_pause_config *pause_info); 850 851 int hinic_dcb_set_pfc(struct hinic_hwdev *hwdev, u8 pfc_en, u8 pfc_bitmap); 852 853 int hinic_set_loopback_mode(struct hinic_hwdev *hwdev, u32 mode, u32 enable); 854 855 enum hinic_led_mode { 856 HINIC_LED_MODE_ON, 857 HINIC_LED_MODE_OFF, 858 HINIC_LED_MODE_FORCE_1HZ, 859 HINIC_LED_MODE_FORCE_2HZ, 860 HINIC_LED_MODE_FORCE_4HZ, 861 HINIC_LED_MODE_1HZ, 862 HINIC_LED_MODE_2HZ, 863 HINIC_LED_MODE_4HZ, 864 HINIC_LED_MODE_INVALID, 865 }; 866 867 enum hinic_led_type { 868 HINIC_LED_TYPE_LINK, 869 HINIC_LED_TYPE_LOW_SPEED, 870 HINIC_LED_TYPE_HIGH_SPEED, 871 HINIC_LED_TYPE_INVALID, 872 }; 873 874 int hinic_reset_led_status(struct hinic_hwdev *hwdev, u8 port); 875 876 int hinic_set_led_status(struct hinic_hwdev *hwdev, u8 port, 877 enum hinic_led_type type, enum hinic_led_mode mode); 878 879 int hinic_get_sfp_type(struct hinic_hwdev *hwdev, u8 *data0, u8 *data1); 880 881 int hinic_get_sfp_eeprom(struct hinic_hwdev *hwdev, u8 *data, u16 *len); 882 883 int hinic_open(struct net_device *netdev); 884 885 int hinic_close(struct net_device *netdev); 886 887 #endif 888