1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 Copyright (C) 2013 Vayavya Labs Pvt Ltd
4
5 This implements all the API for managing HW timestamp & PTP.
6
7
8 Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 *******************************************************************************/
11
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include "common.h"
16 #include "stmmac_ptp.h"
17
config_hw_tstamping(void __iomem * ioaddr,u32 data)18 static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
19 {
20 writel(data, ioaddr + PTP_TCR);
21 }
22
config_sub_second_increment(void __iomem * ioaddr,u32 ptp_clock,int gmac4,u32 * ssinc)23 static void config_sub_second_increment(void __iomem *ioaddr,
24 u32 ptp_clock, int gmac4, u32 *ssinc)
25 {
26 u32 value = readl(ioaddr + PTP_TCR);
27 unsigned long data;
28 u32 reg_value;
29
30 /* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
31 * increment to twice the number of nanoseconds of a clock cycle.
32 * The calculation of the default_addend value by the caller will set it
33 * to mid-range = 2^31 when the remainder of this division is zero,
34 * which will make the accumulator overflow once every 2 ptp_clock
35 * cycles, adding twice the number of nanoseconds of a clock cycle :
36 * 2000000000ULL / ptp_clock.
37 */
38 if (value & PTP_TCR_TSCFUPDT)
39 data = (2000000000ULL / ptp_clock);
40 else
41 data = (1000000000ULL / ptp_clock);
42
43 /* 0.465ns accuracy */
44 if (!(value & PTP_TCR_TSCTRLSSR))
45 data = (data * 1000) / 465;
46
47 if (data > PTP_SSIR_SSINC_MAX)
48 data = PTP_SSIR_SSINC_MAX;
49
50 reg_value = data;
51 if (gmac4)
52 reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
53
54 writel(reg_value, ioaddr + PTP_SSIR);
55
56 if (ssinc)
57 *ssinc = data;
58 }
59
init_systime(void __iomem * ioaddr,u32 sec,u32 nsec)60 static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
61 {
62 u32 value;
63
64 writel(sec, ioaddr + PTP_STSUR);
65 writel(nsec, ioaddr + PTP_STNSUR);
66 /* issue command to initialize the system time value */
67 value = readl(ioaddr + PTP_TCR);
68 value |= PTP_TCR_TSINIT;
69 writel(value, ioaddr + PTP_TCR);
70
71 /* wait for present system time initialize to complete */
72 return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
73 !(value & PTP_TCR_TSINIT),
74 10, 100000);
75 }
76
config_addend(void __iomem * ioaddr,u32 addend)77 static int config_addend(void __iomem *ioaddr, u32 addend)
78 {
79 u32 value;
80 int limit;
81
82 writel(addend, ioaddr + PTP_TAR);
83 /* issue command to update the addend value */
84 value = readl(ioaddr + PTP_TCR);
85 value |= PTP_TCR_TSADDREG;
86 writel(value, ioaddr + PTP_TCR);
87
88 /* wait for present addend update to complete */
89 limit = 10;
90 while (limit--) {
91 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
92 break;
93 mdelay(10);
94 }
95 if (limit < 0)
96 return -EBUSY;
97
98 return 0;
99 }
100
adjust_systime(void __iomem * ioaddr,u32 sec,u32 nsec,int add_sub,int gmac4)101 static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
102 int add_sub, int gmac4)
103 {
104 u32 value;
105 int limit;
106
107 if (add_sub) {
108 /* If the new sec value needs to be subtracted with
109 * the system time, then MAC_STSUR reg should be
110 * programmed with (2^32 – <new_sec_value>)
111 */
112 if (gmac4)
113 sec = -sec;
114
115 value = readl(ioaddr + PTP_TCR);
116 if (value & PTP_TCR_TSCTRLSSR)
117 nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
118 else
119 nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
120 }
121
122 writel(sec, ioaddr + PTP_STSUR);
123 value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
124 writel(value, ioaddr + PTP_STNSUR);
125
126 /* issue command to initialize the system time value */
127 value = readl(ioaddr + PTP_TCR);
128 value |= PTP_TCR_TSUPDT;
129 writel(value, ioaddr + PTP_TCR);
130
131 /* wait for present system time adjust/update to complete */
132 limit = 10;
133 while (limit--) {
134 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
135 break;
136 mdelay(10);
137 }
138 if (limit < 0)
139 return -EBUSY;
140
141 return 0;
142 }
143
get_systime(void __iomem * ioaddr,u64 * systime)144 static void get_systime(void __iomem *ioaddr, u64 *systime)
145 {
146 u64 ns, sec0, sec1;
147
148 /* Get the TSS value */
149 sec1 = readl_relaxed(ioaddr + PTP_STSR);
150 do {
151 sec0 = sec1;
152 /* Get the TSSS value */
153 ns = readl_relaxed(ioaddr + PTP_STNSR);
154 /* Get the TSS value */
155 sec1 = readl_relaxed(ioaddr + PTP_STSR);
156 } while (sec0 != sec1);
157
158 if (systime)
159 *systime = ns + (sec1 * 1000000000ULL);
160 }
161
162 const struct stmmac_hwtimestamp stmmac_ptp = {
163 .config_hw_tstamping = config_hw_tstamping,
164 .init_systime = init_systime,
165 .config_sub_second_increment = config_sub_second_increment,
166 .config_addend = config_addend,
167 .adjust_systime = adjust_systime,
168 .get_systime = get_systime,
169 };
170