1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
8 */
9
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
12 #include "mt7615.h"
13 #include "../trace.h"
14 #include "../dma.h"
15 #include "mt7615_trace.h"
16 #include "mac.h"
17
18 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
19
20 static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
21 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
22 .radar_pattern = {
23 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
24 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
25 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
26 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
27 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
28 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
29 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
30 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
31 },
32 };
33
34 static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
35 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
36 .radar_pattern = {
37 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
38 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
39 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
40 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
41 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
42 },
43 };
44
45 static const struct mt7615_dfs_radar_spec jp_radar_specs = {
46 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
47 .radar_pattern = {
48 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
49 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
50 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
51 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
52 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
53 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
54 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
55 },
56 };
57
mt7615_rx_get_wcid(struct mt7615_dev * dev,u8 idx,bool unicast)58 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
59 u8 idx, bool unicast)
60 {
61 struct mt7615_sta *sta;
62 struct mt76_wcid *wcid;
63
64 if (idx >= MT7615_WTBL_SIZE)
65 return NULL;
66
67 wcid = rcu_dereference(dev->mt76.wcid[idx]);
68 if (unicast || !wcid)
69 return wcid;
70
71 if (!wcid->sta)
72 return NULL;
73
74 sta = container_of(wcid, struct mt7615_sta, wcid);
75 if (!sta->vif)
76 return NULL;
77
78 return &sta->vif->sta.wcid;
79 }
80
mt7615_mac_reset_counters(struct mt7615_dev * dev)81 void mt7615_mac_reset_counters(struct mt7615_dev *dev)
82 {
83 int i;
84
85 for (i = 0; i < 4; i++) {
86 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
87 mt76_rr(dev, MT_TX_AGG_CNT(1, i));
88 }
89
90 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
91 dev->mt76.phy.survey_time = ktime_get_boottime();
92 if (dev->mt76.phy2)
93 dev->mt76.phy2->survey_time = ktime_get_boottime();
94
95 /* reset airtime counters */
96 mt76_rr(dev, MT_MIB_SDR9(0));
97 mt76_rr(dev, MT_MIB_SDR9(1));
98
99 mt76_rr(dev, MT_MIB_SDR36(0));
100 mt76_rr(dev, MT_MIB_SDR36(1));
101
102 mt76_rr(dev, MT_MIB_SDR37(0));
103 mt76_rr(dev, MT_MIB_SDR37(1));
104
105 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
106 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
107 }
108
mt7615_mac_set_timing(struct mt7615_phy * phy)109 void mt7615_mac_set_timing(struct mt7615_phy *phy)
110 {
111 s16 coverage_class = phy->coverage_class;
112 struct mt7615_dev *dev = phy->dev;
113 bool ext_phy = phy != &dev->phy;
114 u32 val, reg_offset;
115 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
116 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
117 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
118 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
119 int sifs, offset;
120 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
121
122 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
123 return;
124
125 if (is_5ghz)
126 sifs = 16;
127 else
128 sifs = 10;
129
130 if (ext_phy) {
131 coverage_class = max_t(s16, dev->phy.coverage_class,
132 coverage_class);
133 mt76_set(dev, MT_ARB_SCR,
134 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
135 } else {
136 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
137
138 if (phy_ext)
139 coverage_class = max_t(s16, phy_ext->coverage_class,
140 coverage_class);
141 mt76_set(dev, MT_ARB_SCR,
142 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
143 }
144 udelay(1);
145
146 offset = 3 * coverage_class;
147 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
148 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
149 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
150 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
151
152 mt76_wr(dev, MT_TMAC_ICR(ext_phy),
153 FIELD_PREP(MT_IFS_EIFS, 360) |
154 FIELD_PREP(MT_IFS_RIFS, 2) |
155 FIELD_PREP(MT_IFS_SIFS, sifs) |
156 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
157
158 if (phy->slottime < 20 || is_5ghz)
159 val = MT7615_CFEND_RATE_DEFAULT;
160 else
161 val = MT7615_CFEND_RATE_11B;
162
163 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
164 if (ext_phy)
165 mt76_clear(dev, MT_ARB_SCR,
166 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
167 else
168 mt76_clear(dev, MT_ARB_SCR,
169 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
170
171 }
172
173 static void
mt7615_get_status_freq_info(struct mt7615_dev * dev,struct mt76_phy * mphy,struct mt76_rx_status * status,u8 chfreq)174 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
175 struct mt76_rx_status *status, u8 chfreq)
176 {
177 if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
178 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
179 !test_bit(MT76_STATE_ROC, &mphy->state)) {
180 status->freq = mphy->chandef.chan->center_freq;
181 status->band = mphy->chandef.chan->band;
182 return;
183 }
184
185 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
186 status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
187 }
188
mt7615_mac_fill_tm_rx(struct mt7615_dev * dev,__le32 * rxv)189 static void mt7615_mac_fill_tm_rx(struct mt7615_dev *dev, __le32 *rxv)
190 {
191 #ifdef CONFIG_NL80211_TESTMODE
192 u32 rxv1 = le32_to_cpu(rxv[0]);
193 u32 rxv3 = le32_to_cpu(rxv[2]);
194 u32 rxv4 = le32_to_cpu(rxv[3]);
195 u32 rxv5 = le32_to_cpu(rxv[4]);
196 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1);
197 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1);
198 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5);
199 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000;
200
201 if (!mode) {
202 /* CCK */
203 foe &= ~BIT(11);
204 foe *= 1000;
205 foe >>= 11;
206 } else {
207 if (foe > 2048)
208 foe -= 4096;
209
210 foe = (foe * foe_const) >> 15;
211 }
212
213 dev->test.last_freq_offset = foe;
214 dev->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4);
215 dev->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4);
216 dev->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4);
217 dev->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4);
218 dev->test.last_ib_rssi = FIELD_GET(MT_RXV3_IB_RSSI, rxv3);
219 dev->test.last_wb_rssi = FIELD_GET(MT_RXV3_WB_RSSI, rxv3);
220 #endif
221 }
222
mt7615_mac_fill_rx(struct mt7615_dev * dev,struct sk_buff * skb)223 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
224 {
225 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
226 struct mt76_phy *mphy = &dev->mt76.phy;
227 struct mt7615_phy *phy = &dev->phy;
228 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL;
229 struct ieee80211_supported_band *sband;
230 struct ieee80211_hdr *hdr;
231 __le32 *rxd = (__le32 *)skb->data;
232 u32 rxd0 = le32_to_cpu(rxd[0]);
233 u32 rxd1 = le32_to_cpu(rxd[1]);
234 u32 rxd2 = le32_to_cpu(rxd[2]);
235 __le32 rxd12 = rxd[12];
236 bool unicast, remove_pad, insert_ccmp_hdr = false;
237 int phy_idx;
238 int i, idx;
239 u8 chfreq;
240
241 memset(status, 0, sizeof(*status));
242
243 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
244 if (!phy2)
245 phy_idx = 0;
246 else if (phy2->chfreq == phy->chfreq)
247 phy_idx = -1;
248 else if (phy->chfreq == chfreq)
249 phy_idx = 0;
250 else if (phy2->chfreq == chfreq)
251 phy_idx = 1;
252 else
253 phy_idx = -1;
254
255 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
256 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
257 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
258
259 if (status->wcid) {
260 struct mt7615_sta *msta;
261
262 msta = container_of(status->wcid, struct mt7615_sta, wcid);
263 spin_lock_bh(&dev->sta_poll_lock);
264 if (list_empty(&msta->poll_list))
265 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
266 spin_unlock_bh(&dev->sta_poll_lock);
267 }
268
269 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
270 status->flag |= RX_FLAG_FAILED_FCS_CRC;
271
272 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
273 status->flag |= RX_FLAG_MMIC_ERROR;
274
275 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
276 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
277 status->flag |= RX_FLAG_DECRYPTED;
278 status->flag |= RX_FLAG_IV_STRIPPED;
279 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
280 }
281
282 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
283
284 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
285 return -EINVAL;
286
287 rxd += 4;
288 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
289 rxd += 4;
290 if ((u8 *)rxd - skb->data >= skb->len)
291 return -EINVAL;
292 }
293
294 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
295 u8 *data = (u8 *)rxd;
296
297 if (status->flag & RX_FLAG_DECRYPTED) {
298 status->iv[0] = data[5];
299 status->iv[1] = data[4];
300 status->iv[2] = data[3];
301 status->iv[3] = data[2];
302 status->iv[4] = data[1];
303 status->iv[5] = data[0];
304
305 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
306 }
307 rxd += 4;
308 if ((u8 *)rxd - skb->data >= skb->len)
309 return -EINVAL;
310 }
311
312 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
313 rxd += 2;
314 if ((u8 *)rxd - skb->data >= skb->len)
315 return -EINVAL;
316 }
317
318 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
319 u32 rxdg5 = le32_to_cpu(rxd[5]);
320
321 /*
322 * If both PHYs are on the same channel and we don't have a WCID,
323 * we need to figure out which PHY this packet was received on.
324 * On the primary PHY, the noise value for the chains belonging to the
325 * second PHY will be set to the noise value of the last packet from
326 * that PHY.
327 */
328 if (phy_idx < 0) {
329 int first_chain = ffs(phy2->chainmask) - 1;
330
331 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
332 }
333 }
334
335 if (phy_idx == 1 && phy2) {
336 mphy = dev->mt76.phy2;
337 phy = phy2;
338 status->ext_phy = true;
339 }
340
341 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
342 return -EINVAL;
343
344 mt7615_get_status_freq_info(dev, mphy, status, chfreq);
345 if (status->band == NL80211_BAND_5GHZ)
346 sband = &mphy->sband_5g.sband;
347 else
348 sband = &mphy->sband_2g.sband;
349
350 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
351 return -EINVAL;
352
353 if (!sband->channels)
354 return -EINVAL;
355
356 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
357 MT_RXD2_NORMAL_NON_AMPDU))) {
358 status->flag |= RX_FLAG_AMPDU_DETAILS;
359
360 /* all subframes of an A-MPDU have the same timestamp */
361 if (phy->rx_ampdu_ts != rxd12) {
362 if (!++phy->ampdu_ref)
363 phy->ampdu_ref++;
364 }
365 phy->rx_ampdu_ts = rxd12;
366
367 status->ampdu_ref = phy->ampdu_ref;
368 }
369
370 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
371 u32 rxdg0 = le32_to_cpu(rxd[0]);
372 u32 rxdg1 = le32_to_cpu(rxd[1]);
373 u32 rxdg3 = le32_to_cpu(rxd[3]);
374 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
375 bool cck = false;
376
377 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
378 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
379 case MT_PHY_TYPE_CCK:
380 cck = true;
381 fallthrough;
382 case MT_PHY_TYPE_OFDM:
383 i = mt76_get_rate(&dev->mt76, sband, i, cck);
384 break;
385 case MT_PHY_TYPE_HT_GF:
386 case MT_PHY_TYPE_HT:
387 status->encoding = RX_ENC_HT;
388 if (i > 31)
389 return -EINVAL;
390 break;
391 case MT_PHY_TYPE_VHT:
392 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
393 status->encoding = RX_ENC_VHT;
394 break;
395 default:
396 return -EINVAL;
397 }
398 status->rate_idx = i;
399
400 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
401 case MT_PHY_BW_20:
402 break;
403 case MT_PHY_BW_40:
404 status->bw = RATE_INFO_BW_40;
405 break;
406 case MT_PHY_BW_80:
407 status->bw = RATE_INFO_BW_80;
408 break;
409 case MT_PHY_BW_160:
410 status->bw = RATE_INFO_BW_160;
411 break;
412 default:
413 return -EINVAL;
414 }
415
416 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
417 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
418 if (rxdg0 & MT_RXV1_HT_AD_CODE)
419 status->enc_flags |= RX_ENC_FLAG_LDPC;
420
421 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
422
423 status->chains = mphy->antenna_mask;
424 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
425 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
426 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
427 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
428 status->signal = status->chain_signal[0];
429
430 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
431 if (!(status->chains & BIT(i)))
432 continue;
433
434 status->signal = max(status->signal,
435 status->chain_signal[i]);
436 }
437
438 mt7615_mac_fill_tm_rx(dev, rxd);
439
440 rxd += 6;
441 if ((u8 *)rxd - skb->data >= skb->len)
442 return -EINVAL;
443 }
444
445 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
446
447 if (insert_ccmp_hdr) {
448 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
449
450 mt76_insert_ccmp_hdr(skb, key_id);
451 }
452
453 hdr = (struct ieee80211_hdr *)skb->data;
454 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
455 return 0;
456
457 status->aggr = unicast &&
458 !ieee80211_is_qos_nullfunc(hdr->frame_control);
459 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
460 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
461
462 return 0;
463 }
464
mt7615_sta_ps(struct mt76_dev * mdev,struct ieee80211_sta * sta,bool ps)465 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
466 {
467 }
468 EXPORT_SYMBOL_GPL(mt7615_sta_ps);
469
470 static u16
mt7615_mac_tx_rate_val(struct mt7615_dev * dev,struct mt76_phy * mphy,const struct ieee80211_tx_rate * rate,bool stbc,u8 * bw)471 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
472 struct mt76_phy *mphy,
473 const struct ieee80211_tx_rate *rate,
474 bool stbc, u8 *bw)
475 {
476 u8 phy, nss, rate_idx;
477 u16 rateval = 0;
478
479 *bw = 0;
480
481 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
482 rate_idx = ieee80211_rate_get_vht_mcs(rate);
483 nss = ieee80211_rate_get_vht_nss(rate);
484 phy = MT_PHY_TYPE_VHT;
485 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
486 *bw = 1;
487 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
488 *bw = 2;
489 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
490 *bw = 3;
491 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
492 rate_idx = rate->idx;
493 nss = 1 + (rate->idx >> 3);
494 phy = MT_PHY_TYPE_HT;
495 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
496 phy = MT_PHY_TYPE_HT_GF;
497 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
498 *bw = 1;
499 } else {
500 const struct ieee80211_rate *r;
501 int band = mphy->chandef.chan->band;
502 u16 val;
503
504 nss = 1;
505 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
506 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
507 val = r->hw_value_short;
508 else
509 val = r->hw_value;
510
511 phy = val >> 8;
512 rate_idx = val & 0xff;
513 }
514
515 if (stbc && nss == 1) {
516 nss++;
517 rateval |= MT_TX_RATE_STBC;
518 }
519
520 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
521 FIELD_PREP(MT_TX_RATE_MODE, phy) |
522 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
523
524 return rateval;
525 }
526
mt7615_mac_write_txwi(struct mt7615_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_sta * sta,int pid,struct ieee80211_key_conf * key,bool beacon)527 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
528 struct sk_buff *skb, struct mt76_wcid *wcid,
529 struct ieee80211_sta *sta, int pid,
530 struct ieee80211_key_conf *key, bool beacon)
531 {
532 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
533 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
534 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
535 struct ieee80211_tx_rate *rate = &info->control.rates[0];
536 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
537 bool multicast = is_multicast_ether_addr(hdr->addr1);
538 struct ieee80211_vif *vif = info->control.vif;
539 bool is_mmio = mt76_is_mmio(&dev->mt76);
540 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE;
541 struct mt76_phy *mphy = &dev->mphy;
542 __le16 fc = hdr->frame_control;
543 int tx_count = 8;
544 u16 seqno = 0;
545
546 if (vif) {
547 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
548
549 omac_idx = mvif->omac_idx;
550 wmm_idx = mvif->wmm_idx;
551 }
552
553 if (sta) {
554 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
555
556 tx_count = msta->rate_count;
557 }
558
559 if (ext_phy && dev->mt76.phy2)
560 mphy = dev->mt76.phy2;
561
562 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
563 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
564
565 if (beacon) {
566 p_fmt = MT_TX_TYPE_FW;
567 q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0;
568 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
569 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
570 q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0;
571 } else {
572 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
573 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
574 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb));
575 }
576
577 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
578 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
579 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
580 txwi[0] = cpu_to_le32(val);
581
582 val = MT_TXD1_LONG_FORMAT |
583 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
584 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
585 FIELD_PREP(MT_TXD1_HDR_INFO,
586 ieee80211_get_hdrlen_from_skb(skb) / 2) |
587 FIELD_PREP(MT_TXD1_TID,
588 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
589 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
590 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
591 txwi[1] = cpu_to_le32(val);
592
593 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
594 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
595 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
596 if (key) {
597 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
598 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
599 val |= MT_TXD2_BIP;
600 txwi[3] = 0;
601 } else {
602 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
603 }
604 } else {
605 txwi[3] = 0;
606 }
607 txwi[2] = cpu_to_le32(val);
608
609 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
610 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
611
612 txwi[4] = 0;
613 txwi[6] = 0;
614
615 if (rate->idx >= 0 && rate->count &&
616 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
617 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
618 u8 bw;
619 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
620 &bw);
621
622 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
623
624 val = MT_TXD6_FIXED_BW |
625 FIELD_PREP(MT_TXD6_BW, bw) |
626 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
627 txwi[6] |= cpu_to_le32(val);
628
629 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
630 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
631
632 if (info->flags & IEEE80211_TX_CTL_LDPC)
633 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
634
635 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
636 IEEE80211_TX_RC_VHT_MCS)))
637 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
638
639 tx_count = rate->count;
640 }
641
642 if (!ieee80211_is_beacon(fc)) {
643 struct ieee80211_hw *hw = mt76_hw(dev);
644
645 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
646 if (!ieee80211_hw_check(hw, SUPPORTS_PS))
647 val |= MT_TXD5_SW_POWER_MGMT;
648 txwi[5] = cpu_to_le32(val);
649 } else {
650 txwi[5] = 0;
651 /* use maximum tx count for beacons */
652 tx_count = 0x1f;
653 }
654
655 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
656 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
657 seqno = le16_to_cpu(hdr->seq_ctrl);
658
659 if (ieee80211_is_back_req(hdr->frame_control)) {
660 struct ieee80211_bar *bar;
661
662 bar = (struct ieee80211_bar *)skb->data;
663 seqno = le16_to_cpu(bar->start_seq_num);
664 }
665
666 val |= MT_TXD3_SN_VALID |
667 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
668 }
669
670 txwi[3] |= cpu_to_le32(val);
671
672 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
673 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
674
675 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
676 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) |
677 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18);
678 txwi[7] = cpu_to_le32(val);
679 if (!is_mmio) {
680 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
681 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
682 txwi[8] = cpu_to_le32(val);
683 }
684
685 return 0;
686 }
687 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
688
689 static void
mt7615_txp_skb_unmap_fw(struct mt76_dev * dev,struct mt7615_fw_txp * txp)690 mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp)
691 {
692 int i;
693
694 for (i = 0; i < txp->nbuf; i++)
695 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
696 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
697 }
698
699 static void
mt7615_txp_skb_unmap_hw(struct mt76_dev * dev,struct mt7615_hw_txp * txp)700 mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp)
701 {
702 u32 last_mask;
703 int i;
704
705 last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST;
706
707 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) {
708 struct mt7615_txp_ptr *ptr = &txp->ptr[i];
709 bool last;
710 u16 len;
711
712 len = le16_to_cpu(ptr->len0);
713 last = len & last_mask;
714 len &= MT_TXD_LEN_MASK;
715 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len,
716 DMA_TO_DEVICE);
717 if (last)
718 break;
719
720 len = le16_to_cpu(ptr->len1);
721 last = len & last_mask;
722 len &= MT_TXD_LEN_MASK;
723 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len,
724 DMA_TO_DEVICE);
725 if (last)
726 break;
727 }
728 }
729
mt7615_txp_skb_unmap(struct mt76_dev * dev,struct mt76_txwi_cache * t)730 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
731 struct mt76_txwi_cache *t)
732 {
733 struct mt7615_txp_common *txp;
734
735 txp = mt7615_txwi_to_txp(dev, t);
736 if (is_mt7615(dev))
737 mt7615_txp_skb_unmap_fw(dev, &txp->fw);
738 else
739 mt7615_txp_skb_unmap_hw(dev, &txp->hw);
740 }
741 EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap);
742
mt7615_mac_wtbl_update(struct mt7615_dev * dev,int idx,u32 mask)743 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
744 {
745 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
746 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
747
748 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
749 0, 5000);
750 }
751
mt7615_mac_sta_poll(struct mt7615_dev * dev)752 void mt7615_mac_sta_poll(struct mt7615_dev *dev)
753 {
754 static const u8 ac_to_tid[4] = {
755 [IEEE80211_AC_BE] = 0,
756 [IEEE80211_AC_BK] = 1,
757 [IEEE80211_AC_VI] = 4,
758 [IEEE80211_AC_VO] = 6
759 };
760 static const u8 hw_queue_map[] = {
761 [IEEE80211_AC_BK] = 0,
762 [IEEE80211_AC_BE] = 1,
763 [IEEE80211_AC_VI] = 2,
764 [IEEE80211_AC_VO] = 3,
765 };
766 struct ieee80211_sta *sta;
767 struct mt7615_sta *msta;
768 u32 addr, tx_time[4], rx_time[4];
769 struct list_head sta_poll_list;
770 int i;
771
772 INIT_LIST_HEAD(&sta_poll_list);
773 spin_lock_bh(&dev->sta_poll_lock);
774 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
775 spin_unlock_bh(&dev->sta_poll_lock);
776
777 while (!list_empty(&sta_poll_list)) {
778 bool clear = false;
779
780 msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
781 poll_list);
782
783 spin_lock_bh(&dev->sta_poll_lock);
784 list_del_init(&msta->poll_list);
785 spin_unlock_bh(&dev->sta_poll_lock);
786
787 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
788
789 for (i = 0; i < 4; i++, addr += 8) {
790 u32 tx_last = msta->airtime_ac[i];
791 u32 rx_last = msta->airtime_ac[i + 4];
792
793 msta->airtime_ac[i] = mt76_rr(dev, addr);
794 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
795 tx_time[i] = msta->airtime_ac[i] - tx_last;
796 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
797
798 if ((tx_last | rx_last) & BIT(30))
799 clear = true;
800 }
801
802 if (clear) {
803 mt7615_mac_wtbl_update(dev, msta->wcid.idx,
804 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
805 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
806 }
807
808 if (!msta->wcid.sta)
809 continue;
810
811 sta = container_of((void *)msta, struct ieee80211_sta,
812 drv_priv);
813 for (i = 0; i < 4; i++) {
814 u32 tx_cur = tx_time[i];
815 u32 rx_cur = rx_time[hw_queue_map[i]];
816 u8 tid = ac_to_tid[i];
817
818 if (!tx_cur && !rx_cur)
819 continue;
820
821 ieee80211_sta_register_airtime(sta, tid, tx_cur,
822 rx_cur);
823 }
824 }
825 }
826 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
827
828 static void
mt7615_mac_update_rate_desc(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates,struct mt7615_rate_desc * rd)829 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
830 struct ieee80211_tx_rate *probe_rate,
831 struct ieee80211_tx_rate *rates,
832 struct mt7615_rate_desc *rd)
833 {
834 struct mt7615_dev *dev = phy->dev;
835 struct mt76_phy *mphy = phy->mt76;
836 struct ieee80211_tx_rate *ref;
837 bool rateset, stbc = false;
838 int n_rates = sta->n_rates;
839 u8 bw, bw_prev;
840 int i, j;
841
842 for (i = n_rates; i < 4; i++)
843 rates[i] = rates[n_rates - 1];
844
845 rateset = !(sta->rate_set_tsf & BIT(0));
846 memcpy(sta->rateset[rateset].rates, rates,
847 sizeof(sta->rateset[rateset].rates));
848 if (probe_rate) {
849 sta->rateset[rateset].probe_rate = *probe_rate;
850 ref = &sta->rateset[rateset].probe_rate;
851 } else {
852 sta->rateset[rateset].probe_rate.idx = -1;
853 ref = &sta->rateset[rateset].rates[0];
854 }
855
856 rates = sta->rateset[rateset].rates;
857 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
858 /*
859 * We don't support switching between short and long GI
860 * within the rate set. For accurate tx status reporting, we
861 * need to make sure that flags match.
862 * For improved performance, avoid duplicate entries by
863 * decrementing the MCS index if necessary
864 */
865 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
866 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
867
868 for (j = 0; j < i; j++) {
869 if (rates[i].idx != rates[j].idx)
870 continue;
871 if ((rates[i].flags ^ rates[j].flags) &
872 (IEEE80211_TX_RC_40_MHZ_WIDTH |
873 IEEE80211_TX_RC_80_MHZ_WIDTH |
874 IEEE80211_TX_RC_160_MHZ_WIDTH))
875 continue;
876
877 if (!rates[i].idx)
878 continue;
879
880 rates[i].idx--;
881 }
882 }
883
884 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
885 bw_prev = bw;
886
887 if (probe_rate) {
888 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
889 stbc, &bw);
890 if (bw)
891 rd->bw_idx = 1;
892 else
893 bw_prev = 0;
894 } else {
895 rd->probe_val = rd->val[0];
896 }
897
898 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
899 if (bw_prev) {
900 rd->bw_idx = 3;
901 bw_prev = bw;
902 }
903
904 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
905 if (bw_prev) {
906 rd->bw_idx = 5;
907 bw_prev = bw;
908 }
909
910 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
911 if (bw_prev)
912 rd->bw_idx = 7;
913
914 rd->rateset = rateset;
915 rd->bw = bw;
916 }
917
918 static int
mt7615_mac_queue_rate_update(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates)919 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
920 struct ieee80211_tx_rate *probe_rate,
921 struct ieee80211_tx_rate *rates)
922 {
923 struct mt7615_dev *dev = phy->dev;
924 struct mt7615_wtbl_desc *wd;
925
926 if (work_pending(&dev->wtbl_work))
927 return -EBUSY;
928
929 wd = kzalloc(sizeof(*wd), GFP_ATOMIC);
930 if (!wd)
931 return -ENOMEM;
932
933 wd->type = MT7615_WTBL_RATE_DESC;
934 wd->sta = sta;
935
936 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
937 &wd->rate);
938 list_add_tail(&wd->node, &dev->wd_head);
939 queue_work(dev->mt76.wq, &dev->wtbl_work);
940
941 return 0;
942 }
943
mt7615_mac_get_sta_tid_sn(struct mt7615_dev * dev,int wcid,u8 tid)944 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid)
945 {
946 u32 addr, val, val2;
947 u8 offset;
948
949 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4;
950
951 offset = tid * 12;
952 addr += 4 * (offset / 32);
953 offset %= 32;
954
955 val = mt76_rr(dev, addr);
956 val >>= offset;
957
958 if (offset > 20) {
959 addr += 4;
960 val2 = mt76_rr(dev, addr);
961 val |= val2 << (32 - offset);
962 }
963
964 return val & GENMASK(11, 0);
965 }
966
mt7615_mac_set_rates(struct mt7615_phy * phy,struct mt7615_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates)967 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
968 struct ieee80211_tx_rate *probe_rate,
969 struct ieee80211_tx_rate *rates)
970 {
971 int wcid = sta->wcid.idx, n_rates = sta->n_rates;
972 struct mt7615_dev *dev = phy->dev;
973 struct mt7615_rate_desc rd;
974 u32 w5, w27, addr;
975
976 if (!mt76_is_mmio(&dev->mt76)) {
977 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
978 return;
979 }
980
981 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
982 return;
983
984 memset(&rd, 0, sizeof(struct mt7615_rate_desc));
985 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
986
987 addr = mt7615_mac_wtbl_addr(dev, wcid);
988 w27 = mt76_rr(dev, addr + 27 * 4);
989 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
990 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
991
992 w5 = mt76_rr(dev, addr + 5 * 4);
993 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
994 MT_WTBL_W5_MPDU_OK_COUNT |
995 MT_WTBL_W5_MPDU_FAIL_COUNT |
996 MT_WTBL_W5_RATE_IDX);
997 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
998 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
999 rd.bw_idx ? rd.bw_idx - 1 : 7);
1000
1001 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
1002
1003 mt76_wr(dev, MT_WTBL_RIUCR1,
1004 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
1005 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
1006 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
1007
1008 mt76_wr(dev, MT_WTBL_RIUCR2,
1009 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
1010 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
1011 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
1012 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
1013
1014 mt76_wr(dev, MT_WTBL_RIUCR3,
1015 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
1016 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
1017 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
1018
1019 mt76_wr(dev, MT_WTBL_UPDATE,
1020 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
1021 MT_WTBL_UPDATE_RATE_UPDATE |
1022 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
1023
1024 mt76_wr(dev, addr + 27 * 4, w27);
1025
1026 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
1027 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
1028 sta->rate_set_tsf |= rd.rateset;
1029
1030 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
1031 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
1032
1033 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
1034 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
1035 sta->rate_probe = !!probe_rate;
1036 }
1037 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
1038
mt7615_mac_wtbl_update_key(struct mt7615_dev * dev,struct mt76_wcid * wcid,u8 * key,u8 keylen,enum mt7615_cipher_type cipher,enum set_key_cmd cmd)1039 int mt7615_mac_wtbl_update_key(struct mt7615_dev *dev,
1040 struct mt76_wcid *wcid,
1041 u8 *key, u8 keylen,
1042 enum mt7615_cipher_type cipher,
1043 enum set_key_cmd cmd)
1044 {
1045 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
1046 u8 data[32] = {};
1047
1048 if (keylen > sizeof(data))
1049 return -EINVAL;
1050
1051 mt76_rr_copy(dev, addr, data, sizeof(data));
1052 if (cmd == SET_KEY) {
1053 if (cipher == MT_CIPHER_TKIP) {
1054 /* Rx/Tx MIC keys are swapped */
1055 memcpy(data, key, 16);
1056 memcpy(data + 16, key + 24, 8);
1057 memcpy(data + 24, key + 16, 8);
1058 } else {
1059 if (cipher != MT_CIPHER_BIP_CMAC_128 && wcid->cipher)
1060 memmove(data + 16, data, 16);
1061 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1062 memcpy(data, key, keylen);
1063 else if (cipher == MT_CIPHER_BIP_CMAC_128)
1064 memcpy(data + 16, key, 16);
1065 }
1066 } else {
1067 if (wcid->cipher & ~BIT(cipher)) {
1068 if (cipher != MT_CIPHER_BIP_CMAC_128)
1069 memmove(data, data + 16, 16);
1070 memset(data + 16, 0, 16);
1071 } else {
1072 memset(data, 0, sizeof(data));
1073 }
1074 }
1075 mt76_wr_copy(dev, addr, data, sizeof(data));
1076
1077 return 0;
1078 }
1079 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_key);
1080
mt7615_mac_wtbl_update_pk(struct mt7615_dev * dev,struct mt76_wcid * wcid,enum mt7615_cipher_type cipher,int keyidx,enum set_key_cmd cmd)1081 int mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev,
1082 struct mt76_wcid *wcid,
1083 enum mt7615_cipher_type cipher,
1084 int keyidx, enum set_key_cmd cmd)
1085 {
1086 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1087
1088 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1089 return -ETIMEDOUT;
1090
1091 w0 = mt76_rr(dev, addr);
1092 w1 = mt76_rr(dev, addr + 4);
1093 if (cmd == SET_KEY) {
1094 w0 |= MT_WTBL_W0_RX_KEY_VALID |
1095 FIELD_PREP(MT_WTBL_W0_RX_IK_VALID,
1096 cipher == MT_CIPHER_BIP_CMAC_128);
1097 if (cipher != MT_CIPHER_BIP_CMAC_128 ||
1098 !wcid->cipher)
1099 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1100 } else {
1101 if (!(wcid->cipher & ~BIT(cipher)))
1102 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID |
1103 MT_WTBL_W0_KEY_IDX);
1104 if (cipher == MT_CIPHER_BIP_CMAC_128)
1105 w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1106 }
1107 mt76_wr(dev, MT_WTBL_RICR0, w0);
1108 mt76_wr(dev, MT_WTBL_RICR1, w1);
1109
1110 if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1111 MT_WTBL_UPDATE_RXINFO_UPDATE))
1112 return -ETIMEDOUT;
1113
1114 return 0;
1115 }
1116 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_pk);
1117
mt7615_mac_wtbl_update_cipher(struct mt7615_dev * dev,struct mt76_wcid * wcid,enum mt7615_cipher_type cipher,enum set_key_cmd cmd)1118 void mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev,
1119 struct mt76_wcid *wcid,
1120 enum mt7615_cipher_type cipher,
1121 enum set_key_cmd cmd)
1122 {
1123 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1124
1125 if (cmd == SET_KEY) {
1126 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1127 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1128 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1129 } else {
1130 if (cipher != MT_CIPHER_BIP_CMAC_128 &&
1131 wcid->cipher & BIT(MT_CIPHER_BIP_CMAC_128))
1132 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1133 FIELD_PREP(MT_WTBL_W2_KEY_TYPE,
1134 MT_CIPHER_BIP_CMAC_128));
1135 else if (!(wcid->cipher & ~BIT(cipher)))
1136 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
1137 }
1138 }
1139 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_cipher);
1140
mt7615_mac_wtbl_set_key(struct mt7615_dev * dev,struct mt76_wcid * wcid,struct ieee80211_key_conf * key,enum set_key_cmd cmd)1141 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1142 struct mt76_wcid *wcid,
1143 struct ieee80211_key_conf *key,
1144 enum set_key_cmd cmd)
1145 {
1146 enum mt7615_cipher_type cipher;
1147 int err;
1148
1149 cipher = mt7615_mac_get_cipher(key->cipher);
1150 if (cipher == MT_CIPHER_NONE)
1151 return -EOPNOTSUPP;
1152
1153 spin_lock_bh(&dev->mt76.lock);
1154
1155 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cmd);
1156 err = mt7615_mac_wtbl_update_key(dev, wcid, key->key, key->keylen,
1157 cipher, cmd);
1158 if (err < 0)
1159 goto out;
1160
1161 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, key->keyidx,
1162 cmd);
1163 if (err < 0)
1164 goto out;
1165
1166 if (cmd == SET_KEY)
1167 wcid->cipher |= BIT(cipher);
1168 else
1169 wcid->cipher &= ~BIT(cipher);
1170
1171 out:
1172 spin_unlock_bh(&dev->mt76.lock);
1173
1174 return err;
1175 }
1176
mt7615_fill_txs(struct mt7615_dev * dev,struct mt7615_sta * sta,struct ieee80211_tx_info * info,__le32 * txs_data)1177 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1178 struct ieee80211_tx_info *info, __le32 *txs_data)
1179 {
1180 struct ieee80211_supported_band *sband;
1181 struct mt7615_rate_set *rs;
1182 struct mt76_phy *mphy;
1183 int first_idx = 0, last_idx;
1184 int i, idx, count;
1185 bool fixed_rate, ack_timeout;
1186 bool ampdu, cck = false;
1187 bool rs_idx;
1188 u32 rate_set_tsf;
1189 u32 final_rate, final_rate_flags, final_nss, txs;
1190
1191 txs = le32_to_cpu(txs_data[1]);
1192 ampdu = txs & MT_TXS1_AMPDU;
1193
1194 txs = le32_to_cpu(txs_data[3]);
1195 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1196 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1197
1198 txs = le32_to_cpu(txs_data[0]);
1199 fixed_rate = txs & MT_TXS0_FIXED_RATE;
1200 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1201 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1202
1203 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1204 return false;
1205
1206 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1207 return false;
1208
1209 if (!ack_timeout)
1210 info->flags |= IEEE80211_TX_STAT_ACK;
1211
1212 info->status.ampdu_len = 1;
1213 info->status.ampdu_ack_len = !!(info->flags &
1214 IEEE80211_TX_STAT_ACK);
1215
1216 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1217 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1218
1219 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1220
1221 if (fixed_rate) {
1222 info->status.rates[0].count = count;
1223 i = 0;
1224 goto out;
1225 }
1226
1227 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1228 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
1229 rate_set_tsf) < 1000000);
1230 rs_idx ^= rate_set_tsf & BIT(0);
1231 rs = &sta->rateset[rs_idx];
1232
1233 if (!first_idx && rs->probe_rate.idx >= 0) {
1234 info->status.rates[0] = rs->probe_rate;
1235
1236 spin_lock_bh(&dev->mt76.lock);
1237 if (sta->rate_probe) {
1238 struct mt7615_phy *phy = &dev->phy;
1239
1240 if (sta->wcid.ext_phy && dev->mt76.phy2)
1241 phy = dev->mt76.phy2->priv;
1242
1243 mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1244 }
1245 spin_unlock_bh(&dev->mt76.lock);
1246 } else {
1247 info->status.rates[0] = rs->rates[first_idx / 2];
1248 }
1249 info->status.rates[0].count = 0;
1250
1251 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1252 struct ieee80211_tx_rate *cur_rate;
1253 int cur_count;
1254
1255 cur_rate = &rs->rates[idx / 2];
1256 cur_count = min_t(int, MT7615_RATE_RETRY, count);
1257 count -= cur_count;
1258
1259 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1260 cur_rate->flags != info->status.rates[i].flags)) {
1261 i++;
1262 if (i == ARRAY_SIZE(info->status.rates)) {
1263 i--;
1264 break;
1265 }
1266
1267 info->status.rates[i] = *cur_rate;
1268 info->status.rates[i].count = 0;
1269 }
1270
1271 info->status.rates[i].count += cur_count;
1272 }
1273
1274 out:
1275 final_rate_flags = info->status.rates[i].flags;
1276
1277 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1278 case MT_PHY_TYPE_CCK:
1279 cck = true;
1280 fallthrough;
1281 case MT_PHY_TYPE_OFDM:
1282 mphy = &dev->mphy;
1283 if (sta->wcid.ext_phy && dev->mt76.phy2)
1284 mphy = dev->mt76.phy2;
1285
1286 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1287 sband = &mphy->sband_5g.sband;
1288 else
1289 sband = &mphy->sband_2g.sband;
1290 final_rate &= MT_TX_RATE_IDX;
1291 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1292 cck);
1293 final_rate_flags = 0;
1294 break;
1295 case MT_PHY_TYPE_HT_GF:
1296 case MT_PHY_TYPE_HT:
1297 final_rate_flags |= IEEE80211_TX_RC_MCS;
1298 final_rate &= MT_TX_RATE_IDX;
1299 if (final_rate > 31)
1300 return false;
1301 break;
1302 case MT_PHY_TYPE_VHT:
1303 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1304
1305 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1306 final_nss--;
1307
1308 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1309 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1310 break;
1311 default:
1312 return false;
1313 }
1314
1315 info->status.rates[i].idx = final_rate;
1316 info->status.rates[i].flags = final_rate_flags;
1317
1318 return true;
1319 }
1320
mt7615_mac_add_txs_skb(struct mt7615_dev * dev,struct mt7615_sta * sta,int pid,__le32 * txs_data)1321 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1322 struct mt7615_sta *sta, int pid,
1323 __le32 *txs_data)
1324 {
1325 struct mt76_dev *mdev = &dev->mt76;
1326 struct sk_buff_head list;
1327 struct sk_buff *skb;
1328
1329 if (pid < MT_PACKET_ID_FIRST)
1330 return false;
1331
1332 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1333
1334 mt76_tx_status_lock(mdev, &list);
1335 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1336 if (skb) {
1337 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1338
1339 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1340 ieee80211_tx_info_clear_status(info);
1341 info->status.rates[0].idx = -1;
1342 }
1343
1344 mt76_tx_status_skb_done(mdev, skb, &list);
1345 }
1346 mt76_tx_status_unlock(mdev, &list);
1347
1348 return !!skb;
1349 }
1350
mt7615_mac_add_txs(struct mt7615_dev * dev,void * data)1351 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1352 {
1353 struct ieee80211_tx_info info = {};
1354 struct ieee80211_sta *sta = NULL;
1355 struct mt7615_sta *msta = NULL;
1356 struct mt76_wcid *wcid;
1357 struct mt76_phy *mphy = &dev->mt76.phy;
1358 __le32 *txs_data = data;
1359 u32 txs;
1360 u8 wcidx;
1361 u8 pid;
1362
1363 txs = le32_to_cpu(txs_data[0]);
1364 pid = FIELD_GET(MT_TXS0_PID, txs);
1365 txs = le32_to_cpu(txs_data[2]);
1366 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1367
1368 if (pid == MT_PACKET_ID_NO_ACK)
1369 return;
1370
1371 if (wcidx >= MT7615_WTBL_SIZE)
1372 return;
1373
1374 rcu_read_lock();
1375
1376 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1377 if (!wcid)
1378 goto out;
1379
1380 msta = container_of(wcid, struct mt7615_sta, wcid);
1381 sta = wcid_to_sta(wcid);
1382
1383 spin_lock_bh(&dev->sta_poll_lock);
1384 if (list_empty(&msta->poll_list))
1385 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1386 spin_unlock_bh(&dev->sta_poll_lock);
1387
1388 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1389 goto out;
1390
1391 if (wcidx >= MT7615_WTBL_STA || !sta)
1392 goto out;
1393
1394 if (wcid->ext_phy && dev->mt76.phy2)
1395 mphy = dev->mt76.phy2;
1396
1397 if (mt7615_fill_txs(dev, msta, &info, txs_data))
1398 ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1399
1400 out:
1401 rcu_read_unlock();
1402 }
1403
1404 static void
mt7615_mac_tx_free_token(struct mt7615_dev * dev,u16 token)1405 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1406 {
1407 struct mt76_dev *mdev = &dev->mt76;
1408 struct mt76_txwi_cache *txwi;
1409 __le32 *txwi_data;
1410 u32 val;
1411 u8 wcid;
1412
1413 trace_mac_tx_free(dev, token);
1414
1415 spin_lock_bh(&dev->token_lock);
1416 txwi = idr_remove(&dev->token, token);
1417 spin_unlock_bh(&dev->token_lock);
1418
1419 if (!txwi)
1420 return;
1421
1422 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi);
1423 val = le32_to_cpu(txwi_data[1]);
1424 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val);
1425
1426 mt7615_txp_skb_unmap(mdev, txwi);
1427 if (txwi->skb) {
1428 mt76_tx_complete_skb(mdev, wcid, txwi->skb);
1429 txwi->skb = NULL;
1430 }
1431
1432 mt76_put_txwi(mdev, txwi);
1433 }
1434
mt7615_mac_tx_free(struct mt7615_dev * dev,struct sk_buff * skb)1435 static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
1436 {
1437 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
1438 u8 i, count;
1439
1440 mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false);
1441 if (is_mt7615(&dev->mt76)) {
1442 mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
1443 } else {
1444 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1445 mt76_queue_tx_cleanup(dev, i, false);
1446 }
1447
1448 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
1449 if (is_mt7615(&dev->mt76)) {
1450 __le16 *token = &free->token[0];
1451
1452 for (i = 0; i < count; i++)
1453 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1454 } else {
1455 __le32 *token = (__le32 *)&free->token[0];
1456
1457 for (i = 0; i < count; i++)
1458 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1459 }
1460
1461 dev_kfree_skb(skb);
1462
1463 if (test_bit(MT76_STATE_PM, &dev->phy.mt76->state))
1464 return;
1465
1466 rcu_read_lock();
1467 mt7615_mac_sta_poll(dev);
1468 rcu_read_unlock();
1469
1470 mt7615_pm_power_save_sched(dev);
1471 mt76_worker_schedule(&dev->mt76.tx_worker);
1472 }
1473
mt7615_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb)1474 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1475 struct sk_buff *skb)
1476 {
1477 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1478 __le32 *rxd = (__le32 *)skb->data;
1479 __le32 *end = (__le32 *)&skb->data[skb->len];
1480 enum rx_pkt_type type;
1481 u16 flag;
1482
1483 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
1484 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));
1485 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1486 type = PKT_TYPE_NORMAL_MCU;
1487
1488 switch (type) {
1489 case PKT_TYPE_TXS:
1490 for (rxd++; rxd + 7 <= end; rxd += 7)
1491 mt7615_mac_add_txs(dev, rxd);
1492 dev_kfree_skb(skb);
1493 break;
1494 case PKT_TYPE_TXRX_NOTIFY:
1495 mt7615_mac_tx_free(dev, skb);
1496 break;
1497 case PKT_TYPE_RX_EVENT:
1498 mt7615_mcu_rx_event(dev, skb);
1499 break;
1500 case PKT_TYPE_NORMAL_MCU:
1501 case PKT_TYPE_NORMAL:
1502 if (!mt7615_mac_fill_rx(dev, skb)) {
1503 mt76_rx(&dev->mt76, q, skb);
1504 return;
1505 }
1506 fallthrough;
1507 default:
1508 dev_kfree_skb(skb);
1509 break;
1510 }
1511 }
1512 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1513
1514 static void
mt7615_mac_set_sensitivity(struct mt7615_phy * phy,int val,bool ofdm)1515 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1516 {
1517 struct mt7615_dev *dev = phy->dev;
1518 bool ext_phy = phy != &dev->phy;
1519
1520 if (is_mt7663(&dev->mt76)) {
1521 if (ofdm)
1522 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1523 MT_WF_PHY_PD_OFDM_MASK(0),
1524 MT_WF_PHY_PD_OFDM(0, val));
1525 else
1526 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1527 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1528 MT_WF_PHY_PD_CCK(ext_phy, val));
1529 return;
1530 }
1531
1532 if (ofdm)
1533 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1534 MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1535 MT_WF_PHY_PD_OFDM(ext_phy, val));
1536 else
1537 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1538 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1539 MT_WF_PHY_PD_CCK(ext_phy, val));
1540 }
1541
1542 static void
mt7615_mac_set_default_sensitivity(struct mt7615_phy * phy)1543 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1544 {
1545 /* ofdm */
1546 mt7615_mac_set_sensitivity(phy, 0x13c, true);
1547 /* cck */
1548 mt7615_mac_set_sensitivity(phy, 0x92, false);
1549
1550 phy->ofdm_sensitivity = -98;
1551 phy->cck_sensitivity = -110;
1552 phy->last_cca_adj = jiffies;
1553 }
1554
mt7615_mac_set_scs(struct mt7615_phy * phy,bool enable)1555 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1556 {
1557 struct mt7615_dev *dev = phy->dev;
1558 bool ext_phy = phy != &dev->phy;
1559 u32 reg, mask;
1560
1561 mt7615_mutex_acquire(dev);
1562
1563 if (phy->scs_en == enable)
1564 goto out;
1565
1566 if (is_mt7663(&dev->mt76)) {
1567 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1568 mask = MT_WF_PHY_PD_BLK(0);
1569 } else {
1570 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1571 mask = MT_WF_PHY_PD_BLK(ext_phy);
1572 }
1573
1574 if (enable) {
1575 mt76_set(dev, reg, mask);
1576 if (is_mt7622(&dev->mt76)) {
1577 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1578 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1579 }
1580 } else {
1581 mt76_clear(dev, reg, mask);
1582 }
1583
1584 mt7615_mac_set_default_sensitivity(phy);
1585 phy->scs_en = enable;
1586
1587 out:
1588 mt7615_mutex_release(dev);
1589 }
1590
mt7615_mac_enable_nf(struct mt7615_dev * dev,bool ext_phy)1591 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1592 {
1593 u32 rxtd, reg;
1594
1595 if (is_mt7663(&dev->mt76))
1596 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1597 else
1598 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1599
1600 if (ext_phy)
1601 rxtd = MT_WF_PHY_RXTD2(10);
1602 else
1603 rxtd = MT_WF_PHY_RXTD(12);
1604
1605 mt76_set(dev, rxtd, BIT(18) | BIT(29));
1606 mt76_set(dev, reg, 0x5 << 12);
1607 }
1608
mt7615_mac_cca_stats_reset(struct mt7615_phy * phy)1609 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1610 {
1611 struct mt7615_dev *dev = phy->dev;
1612 bool ext_phy = phy != &dev->phy;
1613 u32 reg;
1614
1615 if (is_mt7663(&dev->mt76))
1616 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1617 else
1618 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1619
1620 /* reset PD and MDRDY counters */
1621 mt76_clear(dev, reg, GENMASK(22, 20));
1622 mt76_set(dev, reg, BIT(22) | BIT(20));
1623 }
1624
1625 static void
mt7615_mac_adjust_sensitivity(struct mt7615_phy * phy,u32 rts_err_rate,bool ofdm)1626 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1627 u32 rts_err_rate, bool ofdm)
1628 {
1629 struct mt7615_dev *dev = phy->dev;
1630 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1631 bool ext_phy = phy != &dev->phy;
1632 s16 def_th = ofdm ? -98 : -110;
1633 bool update = false;
1634 s8 *sensitivity;
1635 int signal;
1636
1637 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1638 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1639 if (!signal) {
1640 mt7615_mac_set_default_sensitivity(phy);
1641 return;
1642 }
1643
1644 signal = min(signal, -72);
1645 if (false_cca > 500) {
1646 if (rts_err_rate > MT_FRAC(40, 100))
1647 return;
1648
1649 /* decrease coverage */
1650 if (*sensitivity == def_th && signal > -90) {
1651 *sensitivity = -90;
1652 update = true;
1653 } else if (*sensitivity + 2 < signal) {
1654 *sensitivity += 2;
1655 update = true;
1656 }
1657 } else if ((false_cca > 0 && false_cca < 50) ||
1658 rts_err_rate > MT_FRAC(60, 100)) {
1659 /* increase coverage */
1660 if (*sensitivity - 2 >= def_th) {
1661 *sensitivity -= 2;
1662 update = true;
1663 }
1664 }
1665
1666 if (*sensitivity > signal) {
1667 *sensitivity = signal;
1668 update = true;
1669 }
1670
1671 if (update) {
1672 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1673
1674 mt7615_mac_set_sensitivity(phy, val, ofdm);
1675 phy->last_cca_adj = jiffies;
1676 }
1677 }
1678
1679 static void
mt7615_mac_scs_check(struct mt7615_phy * phy)1680 mt7615_mac_scs_check(struct mt7615_phy *phy)
1681 {
1682 struct mt7615_dev *dev = phy->dev;
1683 struct mib_stats *mib = &phy->mib;
1684 u32 val, rts_err_rate = 0;
1685 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1686 bool ext_phy = phy != &dev->phy;
1687
1688 if (!phy->scs_en)
1689 return;
1690
1691 if (is_mt7663(&dev->mt76))
1692 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1693 else
1694 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1695 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1696 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1697
1698 if (is_mt7663(&dev->mt76))
1699 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1700 else
1701 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1702 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1703 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1704
1705 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1706 phy->false_cca_cck = pd_cck - mdrdy_cck;
1707 mt7615_mac_cca_stats_reset(phy);
1708
1709 if (mib->rts_cnt + mib->rts_retries_cnt)
1710 rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1711 mib->rts_cnt + mib->rts_retries_cnt);
1712
1713 /* cck */
1714 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1715 /* ofdm */
1716 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1717
1718 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1719 mt7615_mac_set_default_sensitivity(phy);
1720 }
1721
1722 static u8
mt7615_phy_get_nf(struct mt7615_dev * dev,int idx)1723 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1724 {
1725 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1726 u32 reg, val, sum = 0, n = 0;
1727 int i;
1728
1729 if (is_mt7663(&dev->mt76))
1730 reg = MT7663_WF_PHY_RXTD(20);
1731 else
1732 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1733
1734 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1735 val = mt76_rr(dev, reg);
1736 sum += val * nf_power[i];
1737 n += val;
1738 }
1739
1740 if (!n)
1741 return 0;
1742
1743 return sum / n;
1744 }
1745
1746 static void
mt7615_phy_update_channel(struct mt76_phy * mphy,int idx)1747 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1748 {
1749 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1750 struct mt7615_phy *phy = mphy->priv;
1751 struct mt76_channel_state *state;
1752 u64 busy_time, tx_time, rx_time, obss_time;
1753 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1754 int nf;
1755
1756 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1757 MT_MIB_SDR9_BUSY_MASK);
1758 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1759 MT_MIB_SDR36_TXTIME_MASK);
1760 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1761 MT_MIB_SDR37_RXTIME_MASK);
1762 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1763
1764 nf = mt7615_phy_get_nf(dev, idx);
1765 if (!phy->noise)
1766 phy->noise = nf << 4;
1767 else if (nf)
1768 phy->noise += nf - (phy->noise >> 4);
1769
1770 state = mphy->chan_state;
1771 state->cc_busy += busy_time;
1772 state->cc_tx += tx_time;
1773 state->cc_rx += rx_time + obss_time;
1774 state->cc_bss_rx += rx_time;
1775 state->noise = -(phy->noise >> 4);
1776 }
1777
__mt7615_update_channel(struct mt7615_dev * dev)1778 static void __mt7615_update_channel(struct mt7615_dev *dev)
1779 {
1780 struct mt76_dev *mdev = &dev->mt76;
1781
1782 mt7615_phy_update_channel(&mdev->phy, 0);
1783 if (mdev->phy2)
1784 mt7615_phy_update_channel(mdev->phy2, 1);
1785
1786 /* reset obss airtime */
1787 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1788 }
1789
mt7615_update_channel(struct mt76_dev * mdev)1790 void mt7615_update_channel(struct mt76_dev *mdev)
1791 {
1792 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1793
1794 if (mt7615_pm_wake(dev))
1795 return;
1796
1797 __mt7615_update_channel(dev);
1798 mt7615_pm_power_save_sched(dev);
1799 }
1800 EXPORT_SYMBOL_GPL(mt7615_update_channel);
1801
mt7615_update_survey(struct mt7615_dev * dev)1802 static void mt7615_update_survey(struct mt7615_dev *dev)
1803 {
1804 struct mt76_dev *mdev = &dev->mt76;
1805 ktime_t cur_time;
1806
1807 __mt7615_update_channel(dev);
1808 cur_time = ktime_get_boottime();
1809
1810 mt76_update_survey_active_time(&mdev->phy, cur_time);
1811 if (mdev->phy2)
1812 mt76_update_survey_active_time(mdev->phy2, cur_time);
1813 }
1814
1815 static void
mt7615_mac_update_mib_stats(struct mt7615_phy * phy)1816 mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1817 {
1818 struct mt7615_dev *dev = phy->dev;
1819 struct mib_stats *mib = &phy->mib;
1820 bool ext_phy = phy != &dev->phy;
1821 int i, aggr;
1822 u32 val, val2;
1823
1824 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1825 MT_MIB_SDR3_FCS_ERR_MASK);
1826
1827 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
1828 MT_MIB_AMPDU_MPDU_COUNT);
1829 if (val) {
1830 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
1831 MT_MIB_AMPDU_ACK_COUNT);
1832 mib->aggr_per = 1000 * (val - val2) / val;
1833 }
1834
1835 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1836 for (i = 0; i < 4; i++) {
1837 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1838 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1839 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK,
1840 val);
1841
1842 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1843 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1844 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK,
1845 val);
1846
1847 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1848 dev->mt76.aggr_stats[aggr++] += val & 0xffff;
1849 dev->mt76.aggr_stats[aggr++] += val >> 16;
1850 }
1851 }
1852
mt7615_pm_wake_work(struct work_struct * work)1853 void mt7615_pm_wake_work(struct work_struct *work)
1854 {
1855 struct mt7615_dev *dev;
1856 struct mt76_phy *mphy;
1857 int i;
1858
1859 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1860 pm.wake_work);
1861 mphy = dev->phy.mt76;
1862
1863 if (mt7615_mcu_set_drv_ctrl(dev)) {
1864 dev_err(mphy->dev->dev, "failed to wake device\n");
1865 goto out;
1866 }
1867
1868 spin_lock_bh(&dev->pm.txq_lock);
1869 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1870 struct mt7615_sta *msta = dev->pm.tx_q[i].msta;
1871 struct ieee80211_sta *sta = NULL;
1872 struct mt76_wcid *wcid;
1873
1874 if (!dev->pm.tx_q[i].skb)
1875 continue;
1876
1877 wcid = msta ? &msta->wcid : &dev->mt76.global_wcid;
1878 if (msta && wcid->sta)
1879 sta = container_of((void *)msta, struct ieee80211_sta,
1880 drv_priv);
1881
1882 mt76_tx(mphy, sta, wcid, dev->pm.tx_q[i].skb);
1883 dev->pm.tx_q[i].skb = NULL;
1884 }
1885 spin_unlock_bh(&dev->pm.txq_lock);
1886
1887 mt76_worker_schedule(&dev->mt76.tx_worker);
1888
1889 out:
1890 ieee80211_wake_queues(mphy->hw);
1891 complete_all(&dev->pm.wake_cmpl);
1892 }
1893
mt7615_pm_wake(struct mt7615_dev * dev)1894 int mt7615_pm_wake(struct mt7615_dev *dev)
1895 {
1896 struct mt76_phy *mphy = dev->phy.mt76;
1897
1898 if (!mt7615_firmware_offload(dev))
1899 return 0;
1900
1901 if (!mt76_is_mmio(mphy->dev))
1902 return 0;
1903
1904 if (!test_bit(MT76_STATE_PM, &mphy->state))
1905 return 0;
1906
1907 if (test_bit(MT76_HW_SCANNING, &mphy->state) ||
1908 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state))
1909 return 0;
1910
1911 if (queue_work(dev->mt76.wq, &dev->pm.wake_work))
1912 reinit_completion(&dev->pm.wake_cmpl);
1913
1914 if (!wait_for_completion_timeout(&dev->pm.wake_cmpl, 3 * HZ)) {
1915 ieee80211_wake_queues(mphy->hw);
1916 return -ETIMEDOUT;
1917 }
1918
1919 return 0;
1920 }
1921 EXPORT_SYMBOL_GPL(mt7615_pm_wake);
1922
mt7615_pm_power_save_sched(struct mt7615_dev * dev)1923 void mt7615_pm_power_save_sched(struct mt7615_dev *dev)
1924 {
1925 struct mt76_phy *mphy = dev->phy.mt76;
1926
1927 if (!mt7615_firmware_offload(dev))
1928 return;
1929
1930 if (!mt76_is_mmio(mphy->dev))
1931 return;
1932
1933 if (!dev->pm.enable || !test_bit(MT76_STATE_RUNNING, &mphy->state))
1934 return;
1935
1936 dev->pm.last_activity = jiffies;
1937
1938 if (test_bit(MT76_HW_SCANNING, &mphy->state) ||
1939 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state))
1940 return;
1941
1942 if (!test_bit(MT76_STATE_PM, &mphy->state))
1943 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work,
1944 dev->pm.idle_timeout);
1945 }
1946 EXPORT_SYMBOL_GPL(mt7615_pm_power_save_sched);
1947
mt7615_pm_power_save_work(struct work_struct * work)1948 void mt7615_pm_power_save_work(struct work_struct *work)
1949 {
1950 struct mt7615_dev *dev;
1951 unsigned long delta;
1952
1953 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1954 pm.ps_work.work);
1955
1956 delta = dev->pm.idle_timeout;
1957 if (time_is_after_jiffies(dev->pm.last_activity + delta)) {
1958 delta = dev->pm.last_activity + delta - jiffies;
1959 goto out;
1960 }
1961
1962 if (!mt7615_mcu_set_fw_ctrl(dev))
1963 return;
1964 out:
1965 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta);
1966 }
1967
1968 static void
mt7615_pm_interface_iter(void * priv,u8 * mac,struct ieee80211_vif * vif)1969 mt7615_pm_interface_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
1970 {
1971 struct mt7615_phy *phy = priv;
1972 struct mt7615_dev *dev = phy->dev;
1973 bool ext_phy = phy != &dev->phy;
1974
1975 if (mt7615_mcu_set_bss_pm(dev, vif, dev->pm.enable))
1976 return;
1977
1978 if (dev->pm.enable) {
1979 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
1980 mt76_set(dev, MT_WF_RFCR(ext_phy),
1981 MT_WF_RFCR_DROP_OTHER_BEACON);
1982 } else {
1983 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER;
1984 mt76_clear(dev, MT_WF_RFCR(ext_phy),
1985 MT_WF_RFCR_DROP_OTHER_BEACON);
1986 }
1987 }
1988
mt7615_pm_set_enable(struct mt7615_dev * dev,bool enable)1989 int mt7615_pm_set_enable(struct mt7615_dev *dev, bool enable)
1990 {
1991 struct mt76_phy *mphy = dev->phy.mt76;
1992
1993 if (!mt7615_firmware_offload(dev) || !mt76_is_mmio(&dev->mt76))
1994 return -EOPNOTSUPP;
1995
1996 mt7615_mutex_acquire(dev);
1997
1998 if (dev->pm.enable == enable)
1999 goto out;
2000
2001 dev->pm.enable = enable;
2002 ieee80211_iterate_active_interfaces(mphy->hw,
2003 IEEE80211_IFACE_ITER_RESUME_ALL,
2004 mt7615_pm_interface_iter, mphy->priv);
2005 out:
2006 mt7615_mutex_release(dev);
2007
2008 return 0;
2009 }
2010
mt7615_mac_work(struct work_struct * work)2011 void mt7615_mac_work(struct work_struct *work)
2012 {
2013 struct mt7615_phy *phy;
2014 struct mt76_dev *mdev;
2015
2016 phy = (struct mt7615_phy *)container_of(work, struct mt7615_phy,
2017 mac_work.work);
2018 mdev = &phy->dev->mt76;
2019
2020 mt7615_mutex_acquire(phy->dev);
2021
2022 mt7615_update_survey(phy->dev);
2023 if (++phy->mac_work_count == 5) {
2024 phy->mac_work_count = 0;
2025
2026 mt7615_mac_update_mib_stats(phy);
2027 mt7615_mac_scs_check(phy);
2028 }
2029
2030 mt7615_mutex_release(phy->dev);
2031
2032 mt76_tx_status_check(mdev, NULL, false);
2033 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
2034 MT7615_WATCHDOG_TIME);
2035 }
2036
2037 static bool
mt7615_wait_reset_state(struct mt7615_dev * dev,u32 state)2038 mt7615_wait_reset_state(struct mt7615_dev *dev, u32 state)
2039 {
2040 bool ret;
2041
2042 ret = wait_event_timeout(dev->reset_wait,
2043 (READ_ONCE(dev->reset_state) & state),
2044 MT7615_RESET_TIMEOUT);
2045 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
2046 return ret;
2047 }
2048
2049 static void
mt7615_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)2050 mt7615_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
2051 {
2052 struct ieee80211_hw *hw = priv;
2053 struct mt7615_dev *dev = mt7615_hw_dev(hw);
2054
2055 mt7615_mcu_add_beacon(dev, hw, vif, vif->bss_conf.enable_beacon);
2056 }
2057
2058 static void
mt7615_update_beacons(struct mt7615_dev * dev)2059 mt7615_update_beacons(struct mt7615_dev *dev)
2060 {
2061 ieee80211_iterate_active_interfaces(dev->mt76.hw,
2062 IEEE80211_IFACE_ITER_RESUME_ALL,
2063 mt7615_update_vif_beacon, dev->mt76.hw);
2064
2065 if (!dev->mt76.phy2)
2066 return;
2067
2068 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
2069 IEEE80211_IFACE_ITER_RESUME_ALL,
2070 mt7615_update_vif_beacon, dev->mt76.phy2->hw);
2071 }
2072
mt7615_dma_reset(struct mt7615_dev * dev)2073 void mt7615_dma_reset(struct mt7615_dev *dev)
2074 {
2075 int i;
2076
2077 mt76_clear(dev, MT_WPDMA_GLO_CFG,
2078 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
2079 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
2080 usleep_range(1000, 2000);
2081
2082 for (i = 0; i < __MT_TXQ_MAX; i++)
2083 mt76_queue_tx_cleanup(dev, i, true);
2084
2085 mt76_for_each_q_rx(&dev->mt76, i) {
2086 mt76_queue_rx_reset(dev, i);
2087 }
2088
2089 mt76_set(dev, MT_WPDMA_GLO_CFG,
2090 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
2091 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
2092 }
2093 EXPORT_SYMBOL_GPL(mt7615_dma_reset);
2094
mt7615_tx_token_put(struct mt7615_dev * dev)2095 void mt7615_tx_token_put(struct mt7615_dev *dev)
2096 {
2097 struct mt76_txwi_cache *txwi;
2098 int id;
2099
2100 spin_lock_bh(&dev->token_lock);
2101 idr_for_each_entry(&dev->token, txwi, id) {
2102 mt7615_txp_skb_unmap(&dev->mt76, txwi);
2103 if (txwi->skb) {
2104 struct ieee80211_hw *hw;
2105
2106 hw = mt76_tx_status_get_hw(&dev->mt76, txwi->skb);
2107 ieee80211_free_txskb(hw, txwi->skb);
2108 }
2109 mt76_put_txwi(&dev->mt76, txwi);
2110 }
2111 spin_unlock_bh(&dev->token_lock);
2112 idr_destroy(&dev->token);
2113 }
2114 EXPORT_SYMBOL_GPL(mt7615_tx_token_put);
2115
mt7615_mac_reset_work(struct work_struct * work)2116 void mt7615_mac_reset_work(struct work_struct *work)
2117 {
2118 struct mt7615_phy *phy2;
2119 struct mt76_phy *ext_phy;
2120 struct mt7615_dev *dev;
2121
2122 dev = container_of(work, struct mt7615_dev, reset_work);
2123 ext_phy = dev->mt76.phy2;
2124 phy2 = ext_phy ? ext_phy->priv : NULL;
2125
2126 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
2127 return;
2128
2129 ieee80211_stop_queues(mt76_hw(dev));
2130 if (ext_phy)
2131 ieee80211_stop_queues(ext_phy->hw);
2132
2133 set_bit(MT76_RESET, &dev->mphy.state);
2134 set_bit(MT76_MCU_RESET, &dev->mphy.state);
2135 wake_up(&dev->mt76.mcu.wait);
2136 cancel_delayed_work_sync(&dev->phy.mac_work);
2137 del_timer_sync(&dev->phy.roc_timer);
2138 cancel_work_sync(&dev->phy.roc_work);
2139 if (phy2) {
2140 cancel_delayed_work_sync(&phy2->mac_work);
2141 del_timer_sync(&phy2->roc_timer);
2142 cancel_work_sync(&phy2->roc_work);
2143 }
2144
2145 /* lock/unlock all queues to ensure that no tx is pending */
2146 mt76_txq_schedule_all(&dev->mphy);
2147 if (ext_phy)
2148 mt76_txq_schedule_all(ext_phy);
2149
2150 mt76_worker_disable(&dev->mt76.tx_worker);
2151 napi_disable(&dev->mt76.napi[0]);
2152 napi_disable(&dev->mt76.napi[1]);
2153 napi_disable(&dev->mt76.tx_napi);
2154
2155 mt7615_mutex_acquire(dev);
2156
2157 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_STOPPED);
2158
2159 mt7615_tx_token_put(dev);
2160 idr_init(&dev->token);
2161
2162 if (mt7615_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
2163 mt7615_dma_reset(dev);
2164
2165 mt76_wr(dev, MT_WPDMA_MEM_RNG_ERR, 0);
2166
2167 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_INIT);
2168 mt7615_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
2169 }
2170
2171 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
2172 clear_bit(MT76_RESET, &dev->mphy.state);
2173
2174 mt76_worker_enable(&dev->mt76.tx_worker);
2175 napi_enable(&dev->mt76.tx_napi);
2176 napi_schedule(&dev->mt76.tx_napi);
2177
2178 napi_enable(&dev->mt76.napi[0]);
2179 napi_schedule(&dev->mt76.napi[0]);
2180
2181 napi_enable(&dev->mt76.napi[1]);
2182 napi_schedule(&dev->mt76.napi[1]);
2183
2184 ieee80211_wake_queues(mt76_hw(dev));
2185 if (ext_phy)
2186 ieee80211_wake_queues(ext_phy->hw);
2187
2188 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
2189 mt7615_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
2190
2191 mt7615_update_beacons(dev);
2192
2193 mt7615_mutex_release(dev);
2194
2195 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
2196 MT7615_WATCHDOG_TIME);
2197 if (phy2)
2198 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
2199 MT7615_WATCHDOG_TIME);
2200
2201 }
2202
mt7615_dfs_stop_radar_detector(struct mt7615_phy * phy)2203 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
2204 {
2205 struct mt7615_dev *dev = phy->dev;
2206
2207 if (phy->rdd_state & BIT(0))
2208 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
2209 if (phy->rdd_state & BIT(1))
2210 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
2211 }
2212
mt7615_dfs_start_rdd(struct mt7615_dev * dev,int chain)2213 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
2214 {
2215 int err;
2216
2217 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
2218 if (err < 0)
2219 return err;
2220
2221 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
2222 MT_RX_SEL0, 1);
2223 }
2224
mt7615_dfs_start_radar_detector(struct mt7615_phy * phy)2225 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
2226 {
2227 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2228 struct mt7615_dev *dev = phy->dev;
2229 bool ext_phy = phy != &dev->phy;
2230 int err;
2231
2232 /* start CAC */
2233 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
2234 if (err < 0)
2235 return err;
2236
2237 err = mt7615_dfs_start_rdd(dev, ext_phy);
2238 if (err < 0)
2239 return err;
2240
2241 phy->rdd_state |= BIT(ext_phy);
2242
2243 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
2244 chandef->width == NL80211_CHAN_WIDTH_80P80) {
2245 err = mt7615_dfs_start_rdd(dev, 1);
2246 if (err < 0)
2247 return err;
2248
2249 phy->rdd_state |= BIT(1);
2250 }
2251
2252 return 0;
2253 }
2254
2255 static int
mt7615_dfs_init_radar_specs(struct mt7615_phy * phy)2256 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
2257 {
2258 const struct mt7615_dfs_radar_spec *radar_specs;
2259 struct mt7615_dev *dev = phy->dev;
2260 int err, i;
2261
2262 switch (dev->mt76.region) {
2263 case NL80211_DFS_FCC:
2264 radar_specs = &fcc_radar_specs;
2265 err = mt7615_mcu_set_fcc5_lpn(dev, 8);
2266 if (err < 0)
2267 return err;
2268 break;
2269 case NL80211_DFS_ETSI:
2270 radar_specs = &etsi_radar_specs;
2271 break;
2272 case NL80211_DFS_JP:
2273 radar_specs = &jp_radar_specs;
2274 break;
2275 default:
2276 return -EINVAL;
2277 }
2278
2279 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2280 err = mt7615_mcu_set_radar_th(dev, i,
2281 &radar_specs->radar_pattern[i]);
2282 if (err < 0)
2283 return err;
2284 }
2285
2286 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2287 }
2288
mt7615_dfs_init_radar_detector(struct mt7615_phy * phy)2289 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
2290 {
2291 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2292 struct mt7615_dev *dev = phy->dev;
2293 bool ext_phy = phy != &dev->phy;
2294 int err;
2295
2296 if (is_mt7663(&dev->mt76))
2297 return 0;
2298
2299 if (dev->mt76.region == NL80211_DFS_UNSET) {
2300 phy->dfs_state = -1;
2301 if (phy->rdd_state)
2302 goto stop;
2303
2304 return 0;
2305 }
2306
2307 if (test_bit(MT76_SCANNING, &phy->mt76->state))
2308 return 0;
2309
2310 if (phy->dfs_state == chandef->chan->dfs_state)
2311 return 0;
2312
2313 err = mt7615_dfs_init_radar_specs(phy);
2314 if (err < 0) {
2315 phy->dfs_state = -1;
2316 goto stop;
2317 }
2318
2319 phy->dfs_state = chandef->chan->dfs_state;
2320
2321 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
2322 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
2323 return mt7615_dfs_start_radar_detector(phy);
2324
2325 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
2326 MT_RX_SEL0, 0);
2327 }
2328
2329 stop:
2330 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0);
2331 if (err < 0)
2332 return err;
2333
2334 mt7615_dfs_stop_radar_detector(phy);
2335 return 0;
2336 }
2337