1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Rockchip AXI PCIe endpoint controller driver
4 *
5 * Copyright (c) 2018 Rockchip, Inc.
6 *
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
9 */
10
11 #include <linux/configfs.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/pci-epc.h>
16 #include <linux/platform_device.h>
17 #include <linux/pci-epf.h>
18 #include <linux/sizes.h>
19
20 #include "pcie-rockchip.h"
21
22 /**
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
25 * @epc: PCI EPC device
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
29 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
30 * dedicated outbound regions is mapped.
31 * @irq_cpu_addr: base address in the CPU space where a write access triggers
32 * the sending of a memory write (MSI) / normal message (legacy
33 * IRQ) TLP through the PCIe bus.
34 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
35 * dedicated outbound region.
36 * @irq_pci_fn: the latest PCI function that has updated the mapping of
37 * the MSI/legacy IRQ dedicated outbound region.
38 * @irq_pending: bitmask of asserted legacy IRQs.
39 */
40 struct rockchip_pcie_ep {
41 struct rockchip_pcie rockchip;
42 struct pci_epc *epc;
43 u32 max_regions;
44 unsigned long ob_region_map;
45 phys_addr_t *ob_addr;
46 phys_addr_t irq_phys_addr;
47 void __iomem *irq_cpu_addr;
48 u64 irq_pci_addr;
49 u8 irq_pci_fn;
50 u8 irq_pending;
51 };
52
rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie * rockchip,u32 region)53 static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
54 u32 region)
55 {
56 rockchip_pcie_write(rockchip, 0,
57 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
58 rockchip_pcie_write(rockchip, 0,
59 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
60 rockchip_pcie_write(rockchip, 0,
61 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
62 rockchip_pcie_write(rockchip, 0,
63 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
64 rockchip_pcie_write(rockchip, 0,
65 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region));
66 rockchip_pcie_write(rockchip, 0,
67 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region));
68 }
69
rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie * rockchip,u8 fn,u32 r,u32 type,u64 cpu_addr,u64 pci_addr,size_t size)70 static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
71 u32 r, u32 type, u64 cpu_addr,
72 u64 pci_addr, size_t size)
73 {
74 u64 sz = 1ULL << fls64(size - 1);
75 int num_pass_bits = ilog2(sz);
76 u32 addr0, addr1, desc0, desc1;
77 bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG);
78
79 /* The minimal region size is 1MB */
80 if (num_pass_bits < 8)
81 num_pass_bits = 8;
82
83 cpu_addr -= rockchip->mem_res->start;
84 addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) &
85 PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
86 (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
87 addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr);
88 desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type;
89 desc1 = 0;
90
91 if (is_nor_msg) {
92 rockchip_pcie_write(rockchip, 0,
93 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
94 rockchip_pcie_write(rockchip, 0,
95 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
96 rockchip_pcie_write(rockchip, desc0,
97 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
98 rockchip_pcie_write(rockchip, desc1,
99 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
100 } else {
101 /* PCI bus address region */
102 rockchip_pcie_write(rockchip, addr0,
103 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
104 rockchip_pcie_write(rockchip, addr1,
105 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
106 rockchip_pcie_write(rockchip, desc0,
107 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
108 rockchip_pcie_write(rockchip, desc1,
109 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
110
111 addr0 =
112 ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
113 (lower_32_bits(cpu_addr) &
114 PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
115 addr1 = upper_32_bits(cpu_addr);
116 }
117
118 /* CPU bus address region */
119 rockchip_pcie_write(rockchip, addr0,
120 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r));
121 rockchip_pcie_write(rockchip, addr1,
122 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r));
123 }
124
rockchip_pcie_ep_write_header(struct pci_epc * epc,u8 fn,struct pci_epf_header * hdr)125 static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
126 struct pci_epf_header *hdr)
127 {
128 u32 reg;
129 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
130 struct rockchip_pcie *rockchip = &ep->rockchip;
131
132 /* All functions share the same vendor ID with function 0 */
133 if (fn == 0) {
134 u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
135 (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
136
137 rockchip_pcie_write(rockchip, vid_regs,
138 PCIE_CORE_CONFIG_VENDOR);
139 }
140
141 reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID);
142 reg = (reg & 0xFFFF) | (hdr->deviceid << 16);
143 rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID);
144
145 rockchip_pcie_write(rockchip,
146 hdr->revid |
147 hdr->progif_code << 8 |
148 hdr->subclass_code << 16 |
149 hdr->baseclass_code << 24,
150 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID);
151 rockchip_pcie_write(rockchip, hdr->cache_line_size,
152 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
153 PCI_CACHE_LINE_SIZE);
154 rockchip_pcie_write(rockchip, hdr->subsys_id << 16,
155 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
156 PCI_SUBSYSTEM_VENDOR_ID);
157 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8,
158 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
159 PCI_INTERRUPT_LINE);
160
161 return 0;
162 }
163
rockchip_pcie_ep_set_bar(struct pci_epc * epc,u8 fn,struct pci_epf_bar * epf_bar)164 static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
165 struct pci_epf_bar *epf_bar)
166 {
167 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
168 struct rockchip_pcie *rockchip = &ep->rockchip;
169 dma_addr_t bar_phys = epf_bar->phys_addr;
170 enum pci_barno bar = epf_bar->barno;
171 int flags = epf_bar->flags;
172 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
173 u64 sz;
174
175 /* BAR size is 2^(aperture + 7) */
176 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE);
177
178 /*
179 * roundup_pow_of_two() returns an unsigned long, which is not suited
180 * for 64bit values.
181 */
182 sz = 1ULL << fls64(sz - 1);
183 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
184
185 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
186 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
187 } else {
188 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
189 bool is_64bits = sz > SZ_2G;
190
191 if (is_64bits && (bar & 1))
192 return -EINVAL;
193
194 if (is_64bits && is_prefetch)
195 ctrl =
196 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
197 else if (is_prefetch)
198 ctrl =
199 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
200 else if (is_64bits)
201 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
202 else
203 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
204 }
205
206 if (bar < BAR_4) {
207 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
208 b = bar;
209 } else {
210 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
211 b = bar - BAR_4;
212 }
213
214 addr0 = lower_32_bits(bar_phys);
215 addr1 = upper_32_bits(bar_phys);
216
217 cfg = rockchip_pcie_read(rockchip, reg);
218 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
219 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
220 cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
221 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
222
223 rockchip_pcie_write(rockchip, cfg, reg);
224 rockchip_pcie_write(rockchip, addr0,
225 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
226 rockchip_pcie_write(rockchip, addr1,
227 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
228
229 return 0;
230 }
231
rockchip_pcie_ep_clear_bar(struct pci_epc * epc,u8 fn,struct pci_epf_bar * epf_bar)232 static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
233 struct pci_epf_bar *epf_bar)
234 {
235 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
236 struct rockchip_pcie *rockchip = &ep->rockchip;
237 u32 reg, cfg, b, ctrl;
238 enum pci_barno bar = epf_bar->barno;
239
240 if (bar < BAR_4) {
241 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
242 b = bar;
243 } else {
244 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
245 b = bar - BAR_4;
246 }
247
248 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED;
249 cfg = rockchip_pcie_read(rockchip, reg);
250 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
251 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
252 cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
253
254 rockchip_pcie_write(rockchip, cfg, reg);
255 rockchip_pcie_write(rockchip, 0x0,
256 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
257 rockchip_pcie_write(rockchip, 0x0,
258 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
259 }
260
rockchip_pcie_ep_map_addr(struct pci_epc * epc,u8 fn,phys_addr_t addr,u64 pci_addr,size_t size)261 static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn,
262 phys_addr_t addr, u64 pci_addr,
263 size_t size)
264 {
265 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
266 struct rockchip_pcie *pcie = &ep->rockchip;
267 u32 r;
268
269 r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
270 /*
271 * Region 0 is reserved for configuration space and shouldn't
272 * be used elsewhere per TRM, so leave it out.
273 */
274 if (r >= ep->max_regions - 1) {
275 dev_err(&epc->dev, "no free outbound region\n");
276 return -EINVAL;
277 }
278
279 rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr,
280 pci_addr, size);
281
282 set_bit(r, &ep->ob_region_map);
283 ep->ob_addr[r] = addr;
284
285 return 0;
286 }
287
rockchip_pcie_ep_unmap_addr(struct pci_epc * epc,u8 fn,phys_addr_t addr)288 static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
289 phys_addr_t addr)
290 {
291 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
292 struct rockchip_pcie *rockchip = &ep->rockchip;
293 u32 r;
294
295 for (r = 0; r < ep->max_regions - 1; r++)
296 if (ep->ob_addr[r] == addr)
297 break;
298
299 /*
300 * Region 0 is reserved for configuration space and shouldn't
301 * be used elsewhere per TRM, so leave it out.
302 */
303 if (r == ep->max_regions - 1)
304 return;
305
306 rockchip_pcie_clear_ep_ob_atu(rockchip, r);
307
308 ep->ob_addr[r] = 0;
309 clear_bit(r, &ep->ob_region_map);
310 }
311
rockchip_pcie_ep_set_msi(struct pci_epc * epc,u8 fn,u8 multi_msg_cap)312 static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn,
313 u8 multi_msg_cap)
314 {
315 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
316 struct rockchip_pcie *rockchip = &ep->rockchip;
317 u32 flags;
318
319 flags = rockchip_pcie_read(rockchip,
320 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
321 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
322 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
323 flags |=
324 (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
325 (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
326 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
327 rockchip_pcie_write(rockchip, flags,
328 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
329 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
330 return 0;
331 }
332
rockchip_pcie_ep_get_msi(struct pci_epc * epc,u8 fn)333 static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
334 {
335 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
336 struct rockchip_pcie *rockchip = &ep->rockchip;
337 u32 flags;
338
339 flags = rockchip_pcie_read(rockchip,
340 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
341 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
342 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
343 return -EINVAL;
344
345 return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
346 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
347 }
348
rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep * ep,u8 fn,u8 intx,bool do_assert)349 static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
350 u8 intx, bool do_assert)
351 {
352 struct rockchip_pcie *rockchip = &ep->rockchip;
353
354 intx &= 3;
355
356 if (do_assert) {
357 ep->irq_pending |= BIT(intx);
358 rockchip_pcie_write(rockchip,
359 PCIE_CLIENT_INT_IN_ASSERT |
360 PCIE_CLIENT_INT_PEND_ST_PEND,
361 PCIE_CLIENT_LEGACY_INT_CTRL);
362 } else {
363 ep->irq_pending &= ~BIT(intx);
364 rockchip_pcie_write(rockchip,
365 PCIE_CLIENT_INT_IN_DEASSERT |
366 PCIE_CLIENT_INT_PEND_ST_NORMAL,
367 PCIE_CLIENT_LEGACY_INT_CTRL);
368 }
369 }
370
rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep * ep,u8 fn,u8 intx)371 static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
372 u8 intx)
373 {
374 u16 cmd;
375
376 cmd = rockchip_pcie_read(&ep->rockchip,
377 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
378 ROCKCHIP_PCIE_EP_CMD_STATUS);
379
380 if (cmd & PCI_COMMAND_INTX_DISABLE)
381 return -EINVAL;
382
383 /*
384 * Should add some delay between toggling INTx per TRM vaguely saying
385 * it depends on some cycles of the AHB bus clock to function it. So
386 * add sufficient 1ms here.
387 */
388 rockchip_pcie_ep_assert_intx(ep, fn, intx, true);
389 mdelay(1);
390 rockchip_pcie_ep_assert_intx(ep, fn, intx, false);
391 return 0;
392 }
393
rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep * ep,u8 fn,u8 interrupt_num)394 static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
395 u8 interrupt_num)
396 {
397 struct rockchip_pcie *rockchip = &ep->rockchip;
398 u32 flags, mme, data, data_mask;
399 u8 msi_count;
400 u64 pci_addr, pci_addr_mask = 0xff;
401
402 /* Check MSI enable bit */
403 flags = rockchip_pcie_read(&ep->rockchip,
404 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
405 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
406 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
407 return -EINVAL;
408
409 /* Get MSI numbers from MME */
410 mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
411 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
412 msi_count = 1 << mme;
413 if (!interrupt_num || interrupt_num > msi_count)
414 return -EINVAL;
415
416 /* Set MSI private data */
417 data_mask = msi_count - 1;
418 data = rockchip_pcie_read(rockchip,
419 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
420 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
421 PCI_MSI_DATA_64);
422 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
423
424 /* Get MSI PCI address */
425 pci_addr = rockchip_pcie_read(rockchip,
426 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
427 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
428 PCI_MSI_ADDRESS_HI);
429 pci_addr <<= 32;
430 pci_addr |= rockchip_pcie_read(rockchip,
431 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
432 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
433 PCI_MSI_ADDRESS_LO);
434 pci_addr &= GENMASK_ULL(63, 2);
435
436 /* Set the outbound region if needed. */
437 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
438 ep->irq_pci_fn != fn)) {
439 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1,
440 AXI_WRAPPER_MEM_WRITE,
441 ep->irq_phys_addr,
442 pci_addr & ~pci_addr_mask,
443 pci_addr_mask + 1);
444 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
445 ep->irq_pci_fn = fn;
446 }
447
448 writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
449 return 0;
450 }
451
rockchip_pcie_ep_raise_irq(struct pci_epc * epc,u8 fn,enum pci_epc_irq_type type,u16 interrupt_num)452 static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
453 enum pci_epc_irq_type type,
454 u16 interrupt_num)
455 {
456 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
457
458 switch (type) {
459 case PCI_EPC_IRQ_LEGACY:
460 return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
461 case PCI_EPC_IRQ_MSI:
462 return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
463 default:
464 return -EINVAL;
465 }
466 }
467
rockchip_pcie_ep_start(struct pci_epc * epc)468 static int rockchip_pcie_ep_start(struct pci_epc *epc)
469 {
470 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
471 struct rockchip_pcie *rockchip = &ep->rockchip;
472 struct pci_epf *epf;
473 u32 cfg;
474
475 cfg = BIT(0);
476 list_for_each_entry(epf, &epc->pci_epf, list)
477 cfg |= BIT(epf->func_no);
478
479 rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
480
481 return 0;
482 }
483
484 static const struct pci_epc_features rockchip_pcie_epc_features = {
485 .linkup_notifier = false,
486 .msi_capable = true,
487 .msix_capable = false,
488 .align = 256,
489 };
490
491 static const struct pci_epc_features*
rockchip_pcie_ep_get_features(struct pci_epc * epc,u8 func_no)492 rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
493 {
494 return &rockchip_pcie_epc_features;
495 }
496
497 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
498 .write_header = rockchip_pcie_ep_write_header,
499 .set_bar = rockchip_pcie_ep_set_bar,
500 .clear_bar = rockchip_pcie_ep_clear_bar,
501 .map_addr = rockchip_pcie_ep_map_addr,
502 .unmap_addr = rockchip_pcie_ep_unmap_addr,
503 .set_msi = rockchip_pcie_ep_set_msi,
504 .get_msi = rockchip_pcie_ep_get_msi,
505 .raise_irq = rockchip_pcie_ep_raise_irq,
506 .start = rockchip_pcie_ep_start,
507 .get_features = rockchip_pcie_ep_get_features,
508 };
509
rockchip_pcie_parse_ep_dt(struct rockchip_pcie * rockchip,struct rockchip_pcie_ep * ep)510 static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
511 struct rockchip_pcie_ep *ep)
512 {
513 struct device *dev = rockchip->dev;
514 int err;
515
516 err = rockchip_pcie_parse_dt(rockchip);
517 if (err)
518 return err;
519
520 err = rockchip_pcie_get_phys(rockchip);
521 if (err)
522 return err;
523
524 err = of_property_read_u32(dev->of_node,
525 "rockchip,max-outbound-regions",
526 &ep->max_regions);
527 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
528 ep->max_regions = MAX_REGION_LIMIT;
529
530 err = of_property_read_u8(dev->of_node, "max-functions",
531 &ep->epc->max_functions);
532 if (err < 0)
533 ep->epc->max_functions = 1;
534
535 return 0;
536 }
537
538 static const struct of_device_id rockchip_pcie_ep_of_match[] = {
539 { .compatible = "rockchip,rk3399-pcie-ep"},
540 {},
541 };
542
rockchip_pcie_ep_probe(struct platform_device * pdev)543 static int rockchip_pcie_ep_probe(struct platform_device *pdev)
544 {
545 struct device *dev = &pdev->dev;
546 struct rockchip_pcie_ep *ep;
547 struct rockchip_pcie *rockchip;
548 struct pci_epc *epc;
549 size_t max_regions;
550 int err;
551
552 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
553 if (!ep)
554 return -ENOMEM;
555
556 rockchip = &ep->rockchip;
557 rockchip->is_rc = false;
558 rockchip->dev = dev;
559
560 epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
561 if (IS_ERR(epc)) {
562 dev_err(dev, "failed to create epc device\n");
563 return PTR_ERR(epc);
564 }
565
566 ep->epc = epc;
567 epc_set_drvdata(epc, ep);
568
569 err = rockchip_pcie_parse_ep_dt(rockchip, ep);
570 if (err)
571 return err;
572
573 err = rockchip_pcie_enable_clocks(rockchip);
574 if (err)
575 return err;
576
577 err = rockchip_pcie_init_port(rockchip);
578 if (err)
579 goto err_disable_clocks;
580
581 /* Establish the link automatically */
582 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
583 PCIE_CLIENT_CONFIG);
584
585 max_regions = ep->max_regions;
586 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr),
587 GFP_KERNEL);
588
589 if (!ep->ob_addr) {
590 err = -ENOMEM;
591 goto err_uninit_port;
592 }
593
594 /* Only enable function 0 by default */
595 rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
596
597 err = pci_epc_mem_init(epc, rockchip->mem_res->start,
598 resource_size(rockchip->mem_res), PAGE_SIZE);
599 if (err < 0) {
600 dev_err(dev, "failed to initialize the memory space\n");
601 goto err_uninit_port;
602 }
603
604 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
605 SZ_128K);
606 if (!ep->irq_cpu_addr) {
607 dev_err(dev, "failed to reserve memory space for MSI\n");
608 err = -ENOMEM;
609 goto err_epc_mem_exit;
610 }
611
612 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
613
614 rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,
615 PCIE_CLIENT_CONFIG);
616
617 return 0;
618 err_epc_mem_exit:
619 pci_epc_mem_exit(epc);
620 err_uninit_port:
621 rockchip_pcie_deinit_phys(rockchip);
622 err_disable_clocks:
623 rockchip_pcie_disable_clocks(rockchip);
624 return err;
625 }
626
627 static struct platform_driver rockchip_pcie_ep_driver = {
628 .driver = {
629 .name = "rockchip-pcie-ep",
630 .of_match_table = rockchip_pcie_ep_of_match,
631 },
632 .probe = rockchip_pcie_ep_probe,
633 };
634
635 builtin_platform_driver(rockchip_pcie_ep_driver);
636