1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Marvell
4 *
5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
6 *
7 * This file helps PCI controller drivers implement a fake root port
8 * PCI bridge when the HW doesn't provide such a root port PCI
9 * bridge.
10 *
11 * It emulates a PCI bridge by providing a fake PCI configuration
12 * space (and optionally a PCIe capability configuration space) in
13 * memory. By default the read/write operations simply read and update
14 * this fake configuration space in memory. However, PCI controller
15 * drivers can provide through the 'struct pci_sw_bridge_ops'
16 * structure a set of operations to override or complement this
17 * default behavior.
18 */
19
20 #include <linux/pci.h>
21 #include "pci-bridge-emul.h"
22
23 #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
24 #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2)
25 #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
26 #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
27
28 /**
29 * struct pci_bridge_reg_behavior - register bits behaviors
30 * @ro: Read-Only bits
31 * @rw: Read-Write bits
32 * @w1c: Write-1-to-Clear bits
33 *
34 * Reads and Writes will be filtered by specified behavior. All other bits not
35 * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
36 * "Reserved register fields must be read only and must return 0 (all 0's for
37 * multi-bit fields) when read".
38 */
39 struct pci_bridge_reg_behavior {
40 /* Read-only bits */
41 u32 ro;
42
43 /* Read-write bits */
44 u32 rw;
45
46 /* Write-1-to-clear bits */
47 u32 w1c;
48 };
49
50 static const
51 struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
52 [PCI_VENDOR_ID / 4] = { .ro = ~0 },
53 [PCI_COMMAND / 4] = {
54 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
55 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
56 PCI_COMMAND_SERR),
57 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
58 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
59 PCI_COMMAND_FAST_BACK) |
60 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
61 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
62 .w1c = PCI_STATUS_ERROR_BITS << 16,
63 },
64 [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
65
66 /*
67 * Cache Line Size register: implement as read-only, we do not
68 * pretend implementing "Memory Write and Invalidate"
69 * transactions"
70 *
71 * Latency Timer Register: implemented as read-only, as "A
72 * bridge that is not capable of a burst transfer of more than
73 * two data phases on its primary interface is permitted to
74 * hardwire the Latency Timer to a value of 16 or less"
75 *
76 * Header Type: always read-only
77 *
78 * BIST register: implemented as read-only, as "A bridge that
79 * does not support BIST must implement this register as a
80 * read-only register that returns 0 when read"
81 */
82 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
83
84 /*
85 * Base Address registers not used must be implemented as
86 * read-only registers that return 0 when read.
87 */
88 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
89 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
90
91 [PCI_PRIMARY_BUS / 4] = {
92 /* Primary, secondary and subordinate bus are RW */
93 .rw = GENMASK(24, 0),
94 /* Secondary latency is read-only */
95 .ro = GENMASK(31, 24),
96 },
97
98 [PCI_IO_BASE / 4] = {
99 /* The high four bits of I/O base/limit are RW */
100 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
101
102 /* The low four bits of I/O base/limit are RO */
103 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
104 PCI_STATUS_DEVSEL_MASK) << 16) |
105 GENMASK(11, 8) | GENMASK(3, 0)),
106
107 .w1c = PCI_STATUS_ERROR_BITS << 16,
108 },
109
110 [PCI_MEMORY_BASE / 4] = {
111 /* The high 12-bits of mem base/limit are RW */
112 .rw = GENMASK(31, 20) | GENMASK(15, 4),
113
114 /* The low four bits of mem base/limit are RO */
115 .ro = GENMASK(19, 16) | GENMASK(3, 0),
116 },
117
118 [PCI_PREF_MEMORY_BASE / 4] = {
119 /* The high 12-bits of pref mem base/limit are RW */
120 .rw = GENMASK(31, 20) | GENMASK(15, 4),
121
122 /* The low four bits of pref mem base/limit are RO */
123 .ro = GENMASK(19, 16) | GENMASK(3, 0),
124 },
125
126 [PCI_PREF_BASE_UPPER32 / 4] = {
127 .rw = ~0,
128 },
129
130 [PCI_PREF_LIMIT_UPPER32 / 4] = {
131 .rw = ~0,
132 },
133
134 [PCI_IO_BASE_UPPER16 / 4] = {
135 .rw = ~0,
136 },
137
138 [PCI_CAPABILITY_LIST / 4] = {
139 .ro = GENMASK(7, 0),
140 },
141
142 /*
143 * If expansion ROM is unsupported then ROM Base Address register must
144 * be implemented as read-only register that return 0 when read, same
145 * as for unused Base Address registers.
146 */
147 [PCI_ROM_ADDRESS1 / 4] = {
148 .ro = ~0,
149 },
150
151 /*
152 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
153 * are RO, and bridge control (31:16) are a mix of RW, RO,
154 * reserved and W1C bits
155 */
156 [PCI_INTERRUPT_LINE / 4] = {
157 /* Interrupt line is RW */
158 .rw = (GENMASK(7, 0) |
159 ((PCI_BRIDGE_CTL_PARITY |
160 PCI_BRIDGE_CTL_SERR |
161 PCI_BRIDGE_CTL_ISA |
162 PCI_BRIDGE_CTL_VGA |
163 PCI_BRIDGE_CTL_MASTER_ABORT |
164 PCI_BRIDGE_CTL_BUS_RESET |
165 BIT(8) | BIT(9) | BIT(11)) << 16)),
166
167 /* Interrupt pin is RO */
168 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
169
170 .w1c = BIT(10) << 16,
171 },
172 };
173
174 static const
175 struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
176 [PCI_CAP_LIST_ID / 4] = {
177 /*
178 * Capability ID, Next Capability Pointer and
179 * bits [14:0] of Capabilities register are all read-only.
180 * Bit 15 of Capabilities register is reserved.
181 */
182 .ro = GENMASK(30, 0),
183 },
184
185 [PCI_EXP_DEVCAP / 4] = {
186 /*
187 * Bits [31:29] and [17:16] are reserved.
188 * Bits [27:18] are reserved for non-upstream ports.
189 * Bits 28 and [14:6] are reserved for non-endpoint devices.
190 * Other bits are read-only.
191 */
192 .ro = BIT(15) | GENMASK(5, 0),
193 },
194
195 [PCI_EXP_DEVCTL / 4] = {
196 /*
197 * Device control register is RW, except bit 15 which is
198 * reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
199 */
200 .rw = GENMASK(14, 0),
201
202 /*
203 * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
204 * the rest is reserved. Also bit 6 is reserved for non-upstream
205 * ports.
206 */
207 .w1c = GENMASK(3, 0) << 16,
208 .ro = GENMASK(5, 4) << 16,
209 },
210
211 [PCI_EXP_LNKCAP / 4] = {
212 /*
213 * All bits are RO, except bit 23 which is reserved and
214 * bit 18 which is reserved for non-upstream ports.
215 */
216 .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
217 },
218
219 [PCI_EXP_LNKCTL / 4] = {
220 /*
221 * Link control has bits [15:14], [11:3] and [1:0] RW, the
222 * rest is reserved. Bit 8 is reserved for non-upstream ports.
223 *
224 * Link status has bits [13:0] RO, and bits [15:14]
225 * W1C.
226 */
227 .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
228 .ro = GENMASK(13, 0) << 16,
229 .w1c = GENMASK(15, 14) << 16,
230 },
231
232 [PCI_EXP_SLTCAP / 4] = {
233 .ro = ~0,
234 },
235
236 [PCI_EXP_SLTCTL / 4] = {
237 /*
238 * Slot control has bits [14:0] RW, the rest is
239 * reserved.
240 *
241 * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
242 * rest is reserved.
243 */
244 .rw = GENMASK(14, 0),
245 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
246 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
247 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
248 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
249 PCI_EXP_SLTSTA_EIS) << 16,
250 },
251
252 [PCI_EXP_RTCTL / 4] = {
253 /*
254 * Root control has bits [4:0] RW, the rest is
255 * reserved.
256 *
257 * Root capabilities has bit 0 RO, the rest is reserved.
258 */
259 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
260 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
261 PCI_EXP_RTCTL_CRSSVE),
262 .ro = PCI_EXP_RTCAP_CRSVIS << 16,
263 },
264
265 [PCI_EXP_RTSTA / 4] = {
266 /*
267 * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
268 * is reserved.
269 */
270 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
271 .w1c = PCI_EXP_RTSTA_PME,
272 },
273 };
274
275 /*
276 * Initialize a pci_bridge_emul structure to represent a fake PCI
277 * bridge configuration space. The caller needs to have initialized
278 * the PCI configuration space with whatever values make sense
279 * (typically at least vendor, device, revision), the ->ops pointer,
280 * and optionally ->data and ->has_pcie.
281 */
pci_bridge_emul_init(struct pci_bridge_emul * bridge,unsigned int flags)282 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
283 unsigned int flags)
284 {
285 BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
286
287 bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
288 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
289 bridge->conf.cache_line_size = 0x10;
290 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
291 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
292 sizeof(pci_regs_behavior),
293 GFP_KERNEL);
294 if (!bridge->pci_regs_behavior)
295 return -ENOMEM;
296
297 if (bridge->has_pcie) {
298 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
299 bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
300 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
301 bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
302 bridge->pcie_cap_regs_behavior =
303 kmemdup(pcie_cap_regs_behavior,
304 sizeof(pcie_cap_regs_behavior),
305 GFP_KERNEL);
306 if (!bridge->pcie_cap_regs_behavior) {
307 kfree(bridge->pci_regs_behavior);
308 return -ENOMEM;
309 }
310 /* These bits are applicable only for PCI and reserved on PCIe */
311 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
312 ~GENMASK(15, 8);
313 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
314 ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
315 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
316 PCI_COMMAND_FAST_BACK) |
317 (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
318 PCI_STATUS_DEVSEL_MASK) << 16);
319 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
320 ~GENMASK(31, 24);
321 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
322 ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
323 PCI_STATUS_DEVSEL_MASK) << 16);
324 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
325 ~((PCI_BRIDGE_CTL_MASTER_ABORT |
326 BIT(8) | BIT(9) | BIT(11)) << 16);
327 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
328 ~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
329 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
330 ~(BIT(10) << 16);
331 }
332
333 if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
334 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
335 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
336 }
337
338 return 0;
339 }
340 EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
341
342 /*
343 * Cleanup a pci_bridge_emul structure that was previously initialized
344 * using pci_bridge_emul_init().
345 */
pci_bridge_emul_cleanup(struct pci_bridge_emul * bridge)346 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
347 {
348 if (bridge->has_pcie)
349 kfree(bridge->pcie_cap_regs_behavior);
350 kfree(bridge->pci_regs_behavior);
351 }
352 EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
353
354 /*
355 * Should be called by the PCI controller driver when reading the PCI
356 * configuration space of the fake bridge. It will call back the
357 * ->ops->read_base or ->ops->read_pcie operations.
358 */
pci_bridge_emul_conf_read(struct pci_bridge_emul * bridge,int where,int size,u32 * value)359 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
360 int size, u32 *value)
361 {
362 int ret;
363 int reg = where & ~3;
364 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
365 int reg, u32 *value);
366 __le32 *cfgspace;
367 const struct pci_bridge_reg_behavior *behavior;
368
369 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
370 *value = 0;
371 return PCIBIOS_SUCCESSFUL;
372 }
373
374 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
375 *value = 0;
376 return PCIBIOS_SUCCESSFUL;
377 }
378
379 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
380 reg -= PCI_CAP_PCIE_START;
381 read_op = bridge->ops->read_pcie;
382 cfgspace = (__le32 *) &bridge->pcie_conf;
383 behavior = bridge->pcie_cap_regs_behavior;
384 } else {
385 read_op = bridge->ops->read_base;
386 cfgspace = (__le32 *) &bridge->conf;
387 behavior = bridge->pci_regs_behavior;
388 }
389
390 if (read_op)
391 ret = read_op(bridge, reg, value);
392 else
393 ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
394
395 if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
396 *value = le32_to_cpu(cfgspace[reg / 4]);
397
398 /*
399 * Make sure we never return any reserved bit with a value
400 * different from 0.
401 */
402 *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
403 behavior[reg / 4].w1c;
404
405 if (size == 1)
406 *value = (*value >> (8 * (where & 3))) & 0xff;
407 else if (size == 2)
408 *value = (*value >> (8 * (where & 3))) & 0xffff;
409 else if (size != 4)
410 return PCIBIOS_BAD_REGISTER_NUMBER;
411
412 return PCIBIOS_SUCCESSFUL;
413 }
414 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
415
416 /*
417 * Should be called by the PCI controller driver when writing the PCI
418 * configuration space of the fake bridge. It will call back the
419 * ->ops->write_base or ->ops->write_pcie operations.
420 */
pci_bridge_emul_conf_write(struct pci_bridge_emul * bridge,int where,int size,u32 value)421 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
422 int size, u32 value)
423 {
424 int reg = where & ~3;
425 int mask, ret, old, new, shift;
426 void (*write_op)(struct pci_bridge_emul *bridge, int reg,
427 u32 old, u32 new, u32 mask);
428 __le32 *cfgspace;
429 const struct pci_bridge_reg_behavior *behavior;
430
431 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
432 return PCIBIOS_SUCCESSFUL;
433
434 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
435 return PCIBIOS_SUCCESSFUL;
436
437 shift = (where & 0x3) * 8;
438
439 if (size == 4)
440 mask = 0xffffffff;
441 else if (size == 2)
442 mask = 0xffff << shift;
443 else if (size == 1)
444 mask = 0xff << shift;
445 else
446 return PCIBIOS_BAD_REGISTER_NUMBER;
447
448 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
449 if (ret != PCIBIOS_SUCCESSFUL)
450 return ret;
451
452 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
453 reg -= PCI_CAP_PCIE_START;
454 write_op = bridge->ops->write_pcie;
455 cfgspace = (__le32 *) &bridge->pcie_conf;
456 behavior = bridge->pcie_cap_regs_behavior;
457 } else {
458 write_op = bridge->ops->write_base;
459 cfgspace = (__le32 *) &bridge->conf;
460 behavior = bridge->pci_regs_behavior;
461 }
462
463 /* Keep all bits, except the RW bits */
464 new = old & (~mask | ~behavior[reg / 4].rw);
465
466 /* Update the value of the RW bits */
467 new |= (value << shift) & (behavior[reg / 4].rw & mask);
468
469 /* Clear the W1C bits */
470 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
471
472 /* Save the new value with the cleared W1C bits into the cfgspace */
473 cfgspace[reg / 4] = cpu_to_le32(new);
474
475 /*
476 * Clear the W1C bits not specified by the write mask, so that the
477 * write_op() does not clear them.
478 */
479 new &= ~(behavior[reg / 4].w1c & ~mask);
480
481 /*
482 * Set the W1C bits specified by the write mask, so that write_op()
483 * knows about that they are to be cleared.
484 */
485 new |= (value << shift) & (behavior[reg / 4].w1c & mask);
486
487 if (write_op)
488 write_op(bridge, reg, old, new, mask);
489
490 return PCIBIOS_SUCCESSFUL;
491 }
492 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);
493