1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/pwm/pwm-vt8500.c
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/pwm.h>
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18
19 #include <asm/div64.h>
20
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/of_address.h>
24
25 /*
26 * SoC architecture allocates register space for 4 PWMs but only
27 * 2 are currently implemented.
28 */
29 #define VT8500_NR_PWMS 2
30
31 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
32 #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
33 #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
34 #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
35 #define REG_STATUS 0x40
36
37 #define CTRL_ENABLE BIT(0)
38 #define CTRL_INVERT BIT(1)
39 #define CTRL_AUTOLOAD BIT(2)
40 #define CTRL_STOP_IMM BIT(3)
41 #define CTRL_LOAD_PRESCALE BIT(4)
42 #define CTRL_LOAD_PERIOD BIT(5)
43
44 #define STATUS_CTRL_UPDATE BIT(0)
45 #define STATUS_SCALAR_UPDATE BIT(1)
46 #define STATUS_PERIOD_UPDATE BIT(2)
47 #define STATUS_DUTY_UPDATE BIT(3)
48 #define STATUS_ALL_UPDATE 0x0F
49
50 struct vt8500_chip {
51 struct pwm_chip chip;
52 void __iomem *base;
53 struct clk *clk;
54 };
55
56 #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
57
58 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
pwm_busy_wait(struct vt8500_chip * vt8500,int nr,u8 bitmask)59 static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
60 {
61 int loops = msecs_to_loops(10);
62 u32 mask = bitmask << (nr << 8);
63
64 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
65 cpu_relax();
66
67 if (unlikely(!loops))
68 dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
69 mask);
70 }
71
vt8500_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)72 static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
73 int duty_ns, int period_ns)
74 {
75 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
76 unsigned long long c;
77 unsigned long period_cycles, prescale, pv, dc;
78 int err;
79 u32 val;
80
81 err = clk_enable(vt8500->clk);
82 if (err < 0) {
83 dev_err(chip->dev, "failed to enable clock\n");
84 return err;
85 }
86
87 c = clk_get_rate(vt8500->clk);
88 c = c * period_ns;
89 do_div(c, 1000000000);
90 period_cycles = c;
91
92 if (period_cycles < 1)
93 period_cycles = 1;
94 prescale = (period_cycles - 1) / 4096;
95 pv = period_cycles / (prescale + 1) - 1;
96 if (pv > 4095)
97 pv = 4095;
98
99 if (prescale > 1023) {
100 clk_disable(vt8500->clk);
101 return -EINVAL;
102 }
103
104 c = (unsigned long long)pv * duty_ns;
105 do_div(c, period_ns);
106 dc = c;
107
108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
109 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
110
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
112 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
113
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
115 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
116
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
118 val |= CTRL_AUTOLOAD;
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
120 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
121
122 clk_disable(vt8500->clk);
123 return 0;
124 }
125
vt8500_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)126 static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
127 {
128 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
129 int err;
130 u32 val;
131
132 err = clk_enable(vt8500->clk);
133 if (err < 0) {
134 dev_err(chip->dev, "failed to enable clock\n");
135 return err;
136 }
137
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
139 val |= CTRL_ENABLE;
140 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
141 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
142
143 return 0;
144 }
145
vt8500_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)146 static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
147 {
148 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
149 u32 val;
150
151 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
152 val &= ~CTRL_ENABLE;
153 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
154 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
155
156 clk_disable(vt8500->clk);
157 }
158
vt8500_pwm_set_polarity(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)159 static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
160 struct pwm_device *pwm,
161 enum pwm_polarity polarity)
162 {
163 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
164 u32 val;
165
166 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
167
168 if (polarity == PWM_POLARITY_INVERSED)
169 val |= CTRL_INVERT;
170 else
171 val &= ~CTRL_INVERT;
172
173 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
174 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
175
176 return 0;
177 }
178
179 static const struct pwm_ops vt8500_pwm_ops = {
180 .enable = vt8500_pwm_enable,
181 .disable = vt8500_pwm_disable,
182 .config = vt8500_pwm_config,
183 .set_polarity = vt8500_pwm_set_polarity,
184 .owner = THIS_MODULE,
185 };
186
187 static const struct of_device_id vt8500_pwm_dt_ids[] = {
188 { .compatible = "via,vt8500-pwm", },
189 { /* Sentinel */ }
190 };
191 MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
192
vt8500_pwm_probe(struct platform_device * pdev)193 static int vt8500_pwm_probe(struct platform_device *pdev)
194 {
195 struct vt8500_chip *chip;
196 struct resource *r;
197 struct device_node *np = pdev->dev.of_node;
198 int ret;
199
200 if (!np) {
201 dev_err(&pdev->dev, "invalid devicetree node\n");
202 return -EINVAL;
203 }
204
205 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
206 if (chip == NULL)
207 return -ENOMEM;
208
209 chip->chip.dev = &pdev->dev;
210 chip->chip.ops = &vt8500_pwm_ops;
211 chip->chip.of_xlate = of_pwm_xlate_with_flags;
212 chip->chip.of_pwm_n_cells = 3;
213 chip->chip.base = -1;
214 chip->chip.npwm = VT8500_NR_PWMS;
215
216 chip->clk = devm_clk_get(&pdev->dev, NULL);
217 if (IS_ERR(chip->clk)) {
218 dev_err(&pdev->dev, "clock source not specified\n");
219 return PTR_ERR(chip->clk);
220 }
221
222 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
223 chip->base = devm_ioremap_resource(&pdev->dev, r);
224 if (IS_ERR(chip->base))
225 return PTR_ERR(chip->base);
226
227 ret = clk_prepare(chip->clk);
228 if (ret < 0) {
229 dev_err(&pdev->dev, "failed to prepare clock\n");
230 return ret;
231 }
232
233 ret = pwmchip_add(&chip->chip);
234 if (ret < 0) {
235 dev_err(&pdev->dev, "failed to add PWM chip\n");
236 clk_unprepare(chip->clk);
237 return ret;
238 }
239
240 platform_set_drvdata(pdev, chip);
241 return ret;
242 }
243
vt8500_pwm_remove(struct platform_device * pdev)244 static int vt8500_pwm_remove(struct platform_device *pdev)
245 {
246 struct vt8500_chip *chip;
247
248 chip = platform_get_drvdata(pdev);
249 if (chip == NULL)
250 return -ENODEV;
251
252 clk_unprepare(chip->clk);
253
254 return pwmchip_remove(&chip->chip);
255 }
256
257 static struct platform_driver vt8500_pwm_driver = {
258 .probe = vt8500_pwm_probe,
259 .remove = vt8500_pwm_remove,
260 .driver = {
261 .name = "vt8500-pwm",
262 .of_match_table = vt8500_pwm_dt_ids,
263 },
264 };
265 module_platform_driver(vt8500_pwm_driver);
266
267 MODULE_DESCRIPTION("VT8500 PWM Driver");
268 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
269 MODULE_LICENSE("GPL v2");
270